[LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

[lh03061238]

Summary

Add floating-point branch Instructions for EmulateInstructionLoongArch and
add relevant unit tests.

Without this patch:

$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.45s
  Passed: 1044

With this patch:

$ ninja check-lldb-unit
[0/1] Running lldb unit test suite

Testing Time: 10.20s
  Passed: 1048

Depends on D140615 and D140386

[SixWeining]

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

43

It should be 0xfc000300. BCEQZ and BCNEZ should be seperated.
See https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-Vol1-EN/table-of-instruction-encoding.adoc

310

A single space is enough.

319

Is this number of FPRs? Would it be changed in future when we support vertor registers? Adding some comment may help future readers.

lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

157

The opcode is 8 bits 0b01001000. See: https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td#L109

I think you can remove the third argument bcxxz.

256

Ditto.

[lh03061238]

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

43

My understanding of this opcode is not accurate, This will be modified.
Thanks for pointing out.

310

will be modified， thanks

319

It's a little complicated here, I will use “Bits32(inst, 7, 5) + fpr_fcc0_loongarch” to make it clearer.
will be modified， thanks

lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

157

This will be modified.
Thanks for pointing out.

256

will be modified， thanks

[lh03061238]

1、Modify BCEQZ/BCNEZ instruction opcode and mask
2、Separate BCEQZ and BCNEZ
3、Use "Bits32(inst, 7, 5) + fpr_fcc0_loongarch" to calculate cj

[SixWeining]

LGTM from the LoongArch side. Thanks.

lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

154

Seems you can use opcode & 0b11 directly.

[lh03061238]

lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

154

will be modified,
thanks.

[lh03061238]

Modified the EncodeBCZcondType function

[DavidSpickett]

Thanks for adding the testing in earlier patches.

At this point my review isn't adding much value and @SixWeining has the ISA details covered. So changes like this can go in without extra approval in future unless there is some major code structure change.

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h

struct Opcode {
     const char *name;
   };
 
   llvm::Triple::ArchType m_arch_subtype;
   Opcode *GetOpcodeForInstruction(uint32_t inst);
 
   bool EmulateBEQZ(uint32_t inst);
   bool EmulateBNEZ(uint32_t inst);
+  bool EmulateBCEQZ(uint32_t inst);
+  bool EmulateBCNEZ(uint32_t inst);
   bool EmulateJIRL(uint32_t inst);
   bool EmulateB(uint32_t inst);
   bool EmulateBL(uint32_t inst);
   bool EmulateBEQ(uint32_t inst);
   bool EmulateBNE(uint32_t inst);
   bool EmulateBLT(uint32_t inst);
   bool EmulateBGE(uint32_t inst);
   bool EmulateBLTU(uint32_t inst);
   bool EmulateBGEU(uint32_t inst);
   bool EmulateNonJMP(uint32_t inst);
 
   bool EmulateBEQZ64(uint32_t inst);
   bool EmulateBNEZ64(uint32_t inst);
+  bool EmulateBCEQZ64(uint32_t inst);
+  bool EmulateBCNEZ64(uint32_t inst);
   bool EmulateJIRL64(uint32_t inst);
   bool EmulateB64(uint32_t inst);
   bool EmulateBL64(uint32_t inst);
   bool EmulateBEQ64(uint32_t inst);
   bool EmulateBNE64(uint32_t inst);
   bool EmulateBLT64(uint32_t inst);
   bool EmulateBGE64(uint32_t inst);
   bool EmulateBLTU64(uint32_t inst);
   bool EmulateBGEU64(uint32_t inst);
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_LOONGARCH_EMULATEINSTRUCTIONLOONGARCH_H

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

 EmulateInstructionLoongArch::Opcode *
 EmulateInstructionLoongArch::GetOpcodeForInstruction(uint32_t inst) {
   // TODO: Add the mask for other instruction.
   static EmulateInstructionLoongArch::Opcode g_opcodes[] = {
       {0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ,
        "beqz rj, offs21"},
       {0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ,
        "bnez rj, offs21"},
+      {0xfc000300, 0x48000000, &EmulateInstructionLoongArch::EmulateBCEQZ,
+       "bceqz cj, offs21"},
+      {0xfc000300, 0x48000100, &EmulateInstructionLoongArch::EmulateBCNEZ,
+       "bcnez cj, offs21"},
       {0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL,
        "jirl rd, rj, offs16"},
       {0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB,
        " b  offs26"},
       {0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL,
        "bl  offs26"},
       {0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ,
        "beq  rj, rd, offs16"},

 bool EmulateInstructionLoongArch::EmulateBEQZ(uint32_t inst) {
   return IsLoongArch64() ? EmulateBEQZ64(inst) : false;
 }
 
 bool EmulateInstructionLoongArch::EmulateBNEZ(uint32_t inst) {
   return IsLoongArch64() ? EmulateBNEZ64(inst) : false;
 }
 
+bool EmulateInstructionLoongArch::EmulateBCEQZ(uint32_t inst) {
+  return IsLoongArch64() ? EmulateBCEQZ64(inst) : false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBCNEZ(uint32_t inst) {
+  return IsLoongArch64() ? EmulateBCNEZ64(inst) : false;
+}
+
 bool EmulateInstructionLoongArch::EmulateJIRL(uint32_t inst) {
   return IsLoongArch64() ? EmulateJIRL64(inst) : false;
 }
 
 bool EmulateInstructionLoongArch::EmulateB(uint32_t inst) {
   return IsLoongArch64() ? EmulateB64(inst) : false;
 }
 
if (!success)
     return false;
   if (rj_val != 0) {
     uint64_t next_pc = pc + llvm::SignExtend64<23>(offs21 << 2);
     return WritePC(next_pc);
   } else
     return WritePC(pc + 4);
 }
 
+// bceqz cj, offs21
+// if CFR[cj] == 0:
+//  PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBCEQZ64(uint32_t inst) {
+  bool success = false;
+  uint32_t cj = Bits32(inst, 7, 5) + fpr_fcc0_loongarch;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
+  uint8_t cj_val =
+      (uint8_t)ReadRegisterUnsigned(eRegisterKindLLDB, cj, 0, &success);
+  if (!success)
+    return false;
+  if (cj_val == 0) {
+    uint64_t next_pc = pc + llvm::SignExtend64<23>(offs21 << 2);
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+  return false;
+}
+
+// bcnez cj, offs21
+// if CFR[cj] != 0:
+//  PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBCNEZ64(uint32_t inst) {
+  bool success = false;
+  uint32_t cj = Bits32(inst, 7, 5) + fpr_fcc0_loongarch;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
+  uint8_t cj_val =
+      (uint8_t)ReadRegisterUnsigned(eRegisterKindLLDB, cj, 0, &success);
+  if (!success)
+    return false;
+  if (cj_val != 0) {
+    uint64_t next_pc = pc + llvm::SignExtend64<23>(offs21 << 2);
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+  return false;
+}
+
 // jirl rd, rj, offs16
 // GR[rd] = PC + 4
 // PC = GR[rj] + SignExtend({offs16, 2'b0}, GRLEN)
 bool EmulateInstructionLoongArch::EmulateJIRL64(uint32_t inst) {
   uint32_t rj = Bits32(inst, 9, 5);
   uint32_t rd = Bits32(inst, 4, 0);
   bool success = false;
   uint64_t pc = ReadPC(&success);

lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

 #define GEN_BZCOND_TEST(bit, name, rj_val_branched, rj_val_continued)          \
   TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {               \
     testBZcondBranch(this, name, true, rj_val_branched);                       \
   }                                                                            \
   TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {              \
     testBZcondBranch(this, name, false, rj_val_continued);                     \
   }
 
+#define GEN_BCZCOND_TEST(bit, name, cj_val_branched, cj_val_continued)         \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {               \
+    testBCZcondBranch(this, name, true, cj_val_branched);                      \
+  }                                                                            \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {              \
+    testBCZcondBranch(this, name, false, cj_val_continued);                    \
+  }
+
 struct LoongArch64EmulatorTester : public EmulateInstructionLoongArch,
                                    testing::Test {
   RegisterInfoPOSIX_loongarch64::GPR gpr;
   RegisterInfoPOSIX_loongarch64::FPR fpr;
 
   LoongArch64EmulatorTester(
       std::string triple = "loongarch64-unknown-linux-gnu")
       : EmulateInstructionLoongArch(ArchSpec(triple)) {

 static uint32_t BEQZ(uint32_t rj, int32_t offs21) {
   return EncodeBZcondType(0b010000, rj, uint32_t(offs21));
 }
 
 static uint32_t BNEZ(uint32_t rj, int32_t offs21) {
   return EncodeBZcondType(0b010001, rj, uint32_t(offs21));
 }
 
+// BCEQZ BCNEZ
+static uint32_t EncodeBCZcondType(uint32_t opcode, uint8_t cj,
+                                  uint32_t offs21) {
+  uint32_t offs20_16 = (offs21 & 0x001f0000) >> 16;
+  uint32_t offs15_0 = offs21 & 0x0000ffff;
+  return (opcode >> 2) << 26 | offs15_0 << 10 | (opcode & 0b11) << 8 | cj << 5 |
+         offs20_16;
+}
+
+static uint32_t BCEQZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b01001000, cj, uint32_t(offs21));
+}
+
+static uint32_t BCNEZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b01001001, cj, uint32_t(offs21));
+}
+
 using EncoderBcond = uint32_t (*)(uint32_t rj, uint32_t rd, int32_t offs16);
 using EncoderBZcond = uint32_t (*)(uint32_t rj, int32_t offs21);
+using EncoderBCZcond = uint32_t (*)(uint8_t cj, int32_t offs21);
 
 TEST_F(LoongArch64EmulatorTester, testJIRL) {
   bool success = false;
   addr_t old_pc = 0x12000600;
   WritePC(old_pc);
   // JIRL r1, r12, 0x10
   // | 31       26 | 25                           15 | 9       5 | 4       0 |
   // | 0 1 0 0 1 1 | 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 | 0 1 1 0 0 | 0 0 0 0 1 |
static void testBZcondBranch(LoongArch64EmulatorTester *tester,
   // b<cmp>z  r4, (-256)
   uint32_t inst = encoder(4, -256);
   ASSERT_TRUE(tester->TestExecute(inst));
   auto pc = tester->ReadPC(&success);
   ASSERT_TRUE(success);
   ASSERT_EQ(pc, old_pc + (branched ? (-256 * 4) : 4));
 }
 
+static void testBCZcondBranch(LoongArch64EmulatorTester *tester,
+                              EncoderBCZcond encoder, bool branched,
+                              uint32_t cj_val) {
+  bool success = false;
+  addr_t old_pc = 0x12000600;
+  tester->WritePC(old_pc);
+  tester->fpr.fcc = cj_val;
+  // bc<cmp>z fcc0, 256
+  uint32_t inst = encoder(0, 256);
+  ASSERT_TRUE(tester->TestExecute(inst));
+  auto pc = tester->ReadPC(&success);
+  ASSERT_TRUE(success);
+  ASSERT_EQ(pc, old_pc + (branched ? (256 * 4) : 4));
+}
+
 GEN_BCOND_TEST(64, BEQ, 1, 1, 0)
 GEN_BCOND_TEST(64, BNE, 1, 0, 1)
 GEN_BCOND_TEST(64, BLT, -2, 1, -3)
 GEN_BCOND_TEST(64, BGE, -2, -3, 1)
 GEN_BCOND_TEST(64, BLTU, -2, -1, 1)
 GEN_BCOND_TEST(64, BGEU, -2, 1, -1)
 GEN_BZCOND_TEST(64, BEQZ, 0, 1)
 GEN_BZCOND_TEST(64, BNEZ, 1, 0)
+GEN_BCZCOND_TEST(64, BCEQZ, 0, 1)
+GEN_BCZCOND_TEST(64, BCNEZ, 1, 0)