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Differential D140470

[AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16
ClosedPublic

Authored by dp on Dec 21 2022, 3:14 AM.

Details

Reviewers
Joe_Nash
foad
Commits
rG9f40d9ffd186: [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16
Summary

Fix a bug with neg_lo:[0,1,0] and neg_hi:[0,1,0] modifiers - they are accepted but not encoded.

Diff Detail

Event Timeline

dp created this revision.Dec 21 2022, 3:14 AM
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dp requested review of this revision.Dec 21 2022, 3:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 21 2022, 3:14 AM
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Harbormaster completed remote builds in B204346: Diff 484511.Dec 21 2022, 4:13 AM
Joe_Nash accepted this revision.Dec 29 2022, 11:49 AM

LGTM

This revision is now accepted and ready to land.Dec 29 2022, 11:49 AM
Closed by commit rG9f40d9ffd186: [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16 (authored by dp). · Explain WhyDec 30 2022, 5:25 AM
This revision was automatically updated to reflect the committed changes.
dp added a commit: rG9f40d9ffd186: [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
4 lines
2 lines
Disassembler/
AMDGPU/
3 lines

Diff 485687

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

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defm V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8", defm V_DOT4_I32_I8 : VOP3PInst<"v_dot4_i32_i8",
VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot4, 1>; VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot4, 1>;
defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4", defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4",
VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot8, 1>; VOP3P_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot8, 1>;
} // End SubtargetPredicate = HasDot1Insts } // End SubtargetPredicate = HasDot1Insts
def DOT2_BF16_Profile
: VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1> {
let HasSrc1Mods = 1;
}
let SubtargetPredicate = HasDot8Insts in { let SubtargetPredicate = HasDot8Insts in {
defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", defm V_DOT2_F32_BF16 : VOP3PInst<"v_dot2_f32_bf16", DOT2_BF16_Profile,
VOP3P_Profile<VOP_F32_V2I16_V2I16_F32, VOP3_REGULAR, /*HasDPP*/ 1>,
int_amdgcn_fdot2_f32_bf16, 1>; int_amdgcn_fdot2_f32_bf16, 1>;
} // End SubtargetPredicate = HasDot8Insts } // End SubtargetPredicate = HasDot8Insts
} // End let IsDOT = 1 } // End let IsDOT = 1
multiclass VOP3PDOTIUInst <string OpName, SDPatternOperator intrinsic_node> { multiclass VOP3PDOTIUInst <string OpName, SDPatternOperator intrinsic_node> {
let IsDOT = 1 in let IsDOT = 1 in
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llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s

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// GFX11: [0x05,0x40,0x1a,0xcc,0x7c,0xfe,0x04,0x1b] // GFX11: [0x05,0x40,0x1a,0xcc,0x7c,0xfe,0x04,0x1b]
v_dot2_f32_bf16 v5, -1, m0, 0xaf123456 v_dot2_f32_bf16 v5, -1, m0, 0xaf123456
// GFX11: [0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf] // GFX11: [0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf]
v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0] v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc neg_lo:[1,0,0] neg_hi:[1,0,0]
// GFX11: [0x05,0x41,0x1a,0xcc,0xfd,0xd4,0xf4,0x3b] // GFX11: [0x05,0x41,0x1a,0xcc,0xfd,0xd4,0xf4,0x3b]
v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,0,0] neg_hi:[0,0,0] clamp v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,1,0] neg_hi:[0,1,0] clamp
// GFX11: [0xff,0xc0,0x1a,0xcc,0xff,0xd6,0xc0,0x1b,0x0b,0xfe,0x00,0x00] // GFX11: [0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00]
v_dot2_f32_f16 v5, v1, v2, s3 v_dot2_f32_f16 v5, v1, v2, s3
// GFX11: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18] // GFX11: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]
v_dot2_f32_f16 v5, v255, s2, s105 v_dot2_f32_f16 v5, v255, s2, s105
// GFX11: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19] // GFX11: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19]
v_dot2_f32_f16 v5, s1, v255, exec_hi v_dot2_f32_f16 v5, s1, v255, exec_hi
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llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s

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v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1]
// GFX11: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x13,0xcc,0x01,0x05,0x0e,0x7c] // GFX11: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x13,0xcc,0x01,0x05,0x0e,0x7c]
v_dot2_f32_bf16 v0, v1, v2, v3 v_dot2_f32_bf16 v0, v1, v2, v3
// GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c] // GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1]
// GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x1a,0xcc,0x01,0x05,0x0e,0x3c] // GFX11: v_dot2_f32_bf16 v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] ; encoding: [0x00,0x45,0x1a,0xcc,0x01,0x05,0x0e,0x7c]

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt

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0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf 0x05,0x40,0x1a,0xcc,0xc1,0xfa,0xfc,0x1b,0x56,0x34,0x12,0xaf
# GFX11: v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b] # GFX11: v_dot2_f32_bf16 v5, src_scc, vcc_lo, src_scc ; encoding: [0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b]
0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b 0x05,0x40,0x1a,0xcc,0xfd,0xd4,0xf4,0x1b
# GFX11: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[1,0,0] neg_hi:[1,0,0] clamp ; encoding: [0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00] # GFX11: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[1,0,0] neg_hi:[1,0,0] clamp ; encoding: [0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00]
0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00 0xff,0xc1,0x1a,0xcc,0xff,0xd6,0xc0,0x3b,0x0b,0xfe,0x00,0x00
# GFX11: v_dot2_f32_bf16 v255, 0xfe0b, vcc_hi, 0.5 neg_lo:[0,1,0] neg_hi:[0,1,0] clamp ; encoding: [0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00]
0xff,0xc2,0x1a,0xcc,0xff,0xd6,0xc0,0x5b,0x0b,0xfe,0x00,0x00
# GFX11: v_dot2_f32_f16 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18] # GFX11: v_dot2_f32_f16 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18]
0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18 0x05,0x40,0x13,0xcc,0x01,0x05,0x0e,0x18
# GFX11: v_dot2_f32_f16 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19] # GFX11: v_dot2_f32_f16 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19]
0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19 0x05,0x40,0x13,0xcc,0xff,0x05,0xa4,0x19
# GFX11: v_dot2_f32_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19] # GFX11: v_dot2_f32_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19]
0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19 0x05,0x40,0x13,0xcc,0x01,0xfe,0xff,0x19
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