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Differential D140301

[AArch64] Add alias predicate-as-counter register for PFALSE
ClosedPublic

Authored by CarolineConcatto on Dec 19 2022, 6:22 AM.

Details

Reviewers
sdesmalen
david-arm
Commits
rG0d6d05bb7628: [AArch64] Add alias predicate-as-counter register for PFALSE
Summary

According to:
https://developer.arm.com/documentation/ddi0602/2022-09/
PFALSE should:
"...an assembler must also accept predicate-as-counter register
name for the destination predicate register."

Diff Detail

Event Timeline

CarolineConcatto created this revision.Dec 19 2022, 6:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 19 2022, 6:22 AM
Herald added subscribers: jeroen.dobbelaere, hiraditya, kristof.beyls. · View Herald Transcript
CarolineConcatto requested review of this revision.Dec 19 2022, 6:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 19 2022, 6:22 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
CarolineConcatto added reviewers: sdesmalen, david-arm.Dec 19 2022, 6:26 AM
sdesmalen accepted this revision.Dec 19 2022, 6:34 AM
This revision is now accepted and ready to land.Dec 19 2022, 6:34 AM
Harbormaster completed remote builds in B203901: Diff 483944.Dec 19 2022, 7:39 AM
This revision was landed with ongoing or failed builds.Dec 19 2022, 7:51 AM
Closed by commit rG0d6d05bb7628: [AArch64] Add alias predicate-as-counter register for PFALSE (authored by Caroline.Concatto@arm.com <carcon01@ip-10-252-16-47.eu-west-1.compute.internal>). · Explain Why
This revision was automatically updated to reflect the committed changes.
Caroline.Concatto@arm.com <carcon01@ip-10-252-16-47.eu-west-1.compute.internal> added a commit: rG0d6d05bb7628: [AArch64] Add alias predicate-as-counter register for PFALSE.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
test/
MC/
AArch64/
SVE/
7 lines
6 lines

Diff 483967

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 653 Lines • ▼ Show 20 Lines: I<(outs PPR8:$Pd), (ins),
let Inst{3-0} = Pd; let Inst{3-0} = Pd;
let isReMaterializable = 1; let isReMaterializable = 1;
} }
multiclass sve_int_pfalse<bits<6> opc, string asm> { multiclass sve_int_pfalse<bits<6> opc, string asm> {
def NAME : sve_int_pfalse<opc, asm>; def NAME : sve_int_pfalse<opc, asm>;
def : InstAlias<"pfalse\t$Pd", (!cast<Instruction>(NAME) PNR8:$Pd), 0>;
def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>; def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>; def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>; def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;
def : Pat<(nxv2i1 immAllZerosV), (!cast<Instruction>(NAME))>; def : Pat<(nxv2i1 immAllZerosV), (!cast<Instruction>(NAME))>;
def : Pat<(nxv1i1 immAllZerosV), (!cast<Instruction>(NAME))>; def : Pat<(nxv1i1 immAllZerosV), (!cast<Instruction>(NAME))>;
} }
class sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op> class sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op>
▲ Show 20 Lines • Show All 8,872 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Only .b is supported // Only .b is supported
pfalse p15.h pfalse p15.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: pfalse p15.h // CHECK-NEXT: pfalse p15.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Support until pn15.b
pfalse pn16.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pfalse pn16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE/pfalse.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pfalse p15.b pfalse p15.b
// CHECK-INST: pfalse p15.b // CHECK-INST: pfalse p15.b
// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25] // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
// CHECK-ERROR: instruction requires: sve or sme // CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 2518e40f <unknown> // CHECK-UNKNOWN: 2518e40f <unknown>
pfalse pn15.b
// CHECK-INST: pfalse p15.b
// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 2518e40f <unknown>