[LLDB][LoongArch] Add branch instructions for EmulateInstructionLoongArch

[lh03061238]

Summary

Add conditional and unconditional branch instructions for loongarch64.
Note that this does not include floating-point branch instructions, that will come in a later patch.

[SixWeining]

1. Does the directory lldb/source/Plugins/Instruction/LoongArch/ target both LoongArch64 and LoongArch32?
2. Will you handle floating pointer branching instructions bceqz and bcnez in future?

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

205

On LoongArch32, it should be uint32_t, right?

208

On LoongArch32, it should be uint32_t, right?

213

Should success be checked after call ?

215

On LoongArch32, it should be llvm::SignExtend32, right?

258

Return value should be checked ?

269

Should it be checked ?

306

Ditto.

[lh03061238]

In D139833#3990635, @SixWeining wrote:

1. Does the directory lldb/source/Plugins/Instruction/LoongArch/ target both LoongArch64 and LoongArch32?

Yes, both LoongArch64 and LoongArch32 are supported in EmulateInstructionLoongArch
I will modify it to distinguish between LoongArch64 and LoongArch32 operations.
thank you.

2. Will you handle floating pointer branching instructions bceqz and bcnez in future?

Yes, floating-point branch instructions Will be added After more test, for now add the most commonly used
branch instructions.
thank you.

[lh03061238]

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

205

will modify to distinguish between LoongArch64 and LoongArch32 operations.

213

yes, will modify it .
thank you.

258

yes, will modify it .
thank you.

269

yes, will modify it .
thank you.

306

will modify all .
thank you.

[lh03061238]

(1) distinguish between LoongArch64 and LoongArch32 operations in EmulateInstructionLoongArch

(2) check the return values of some functions

[DavidSpickett]

Is the further work in the commit message work you intended to include in this patch? I appreciate the status update might be useful for some but commit messages are for describing what's in a commit (among other things).

If you think people might wrongly assume that this commit contains support for "floating-point branch instructions", I would write something more explicit. For example "note that this does not include <things>, that will come in a later patch".

[DavidSpickett]

This is all very repetitive, but that's to be expected. Whatever you can do to reduce boilerplate in future patches would be great. For example, can 32 and 64 bit variants of some instructions be emulated in the same way? Perhaps with a template parameter for the return types.

This LGTM with a few comments you can do/not do/keep in mind for future patches.

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

276

All these could be of the form:

bool EmulateInstructionLoongArch::EmulateBGEU(uint32_t inst) {
  return IsLoongArch64()) ? EmulateBGEU64(inst) : false;
}

Generally I'd advise coming up with a different way of doing this, that checks up front that you won't call EmulateBGEU and friends when you are emulating 32 bit. Perhaps some table lookup first.

That said perhaps you intend to replace the else here with a call to EmulateBGEU32 in future. Up to you how to structure that.

In any case I'd slim down these functions as suggested for now.

368

This is what I mean about using optionals.

std::optional<uint64_t> pc = ReadPC(&success);
if (!pc)
  return false;
EmulateInstruction::Context ctx;
if (!WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_loongarch, *pc + 4))
  return false;

It's a small saving and ok you have to * some places but when this stuff gets more complicated it can help.

Anyway, up to you but keep it in mind as things get more complicated.

[DavidSpickett]

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

287

I would declare this where it is assigned. The llvm standards don't mandate that but in this case you save a line and IMO, declare as close to use is clearer.

Same for rj.

[SixWeining]

LGTM from the LoongArch side.

[lh03061238]

In D139833#3997386, @DavidSpickett wrote:

Is the further work in the commit message work you intended to include in this patch? I appreciate the status update might be useful for some but commit messages are for describing what's in a commit (among other things).

If you think people might wrongly assume that this commit contains support for "floating-point branch instructions", I would write something more explicit. For example "note that this does not include <things>, that will come in a later patch".

The code submissions for the EmulateInstruction section refer to some ways of riscv and sometimes record further work. You are right, should only describe what this patch does.

In D139833#3997409, @DavidSpickett wrote:

This is all very repetitive, but that's to be expected. Whatever you can do to reduce boilerplate in future patches would be great. For example, can 32 and 64 bit variants of some instructions be emulated in the same way? Perhaps with a template parameter for the return types.

This LGTM with a few comments you can do/not do/keep in mind for future patches.

This patch simply separates 32 and 64 bit processing, make sure the 64-bit works properly. During the continuous
improvement of EmulateInstruction code, the details or some ways to reduce repetition you mentioned will be given
priority consideration.

Thank you very much for your detailed and reasonable suggestions.

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h

public:
   static lldb_private::EmulateInstruction *
   CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type);
 
   static void Initialize();
 
   static void Terminate();
 
 public:
-  EmulateInstructionLoongArch(const ArchSpec &arch)
-      : EmulateInstruction(arch) {}
+  EmulateInstructionLoongArch(const ArchSpec &arch) : EmulateInstruction(arch) {
+    m_arch_subtype = arch.GetMachine();
+  }
 
   llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
 
   bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
     return SupportsThisInstructionType(inst_type);
   }
 
   bool SetTargetTriple(const ArchSpec &arch) override;
   bool ReadInstruction() override;
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
 
   llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
                                                uint32_t reg_num) override;
   lldb::addr_t ReadPC(bool *success);
   bool WritePC(lldb::addr_t pc);
+  bool IsLoongArch64() { return m_arch_subtype == llvm::Triple::loongarch64; }
 
 private:
   struct Opcode {
     uint32_t mask;
     uint32_t value;
     bool (EmulateInstructionLoongArch::*callback)(uint32_t opcode);
     const char *name;
   };
 
+  llvm::Triple::ArchType m_arch_subtype;
   Opcode *GetOpcodeForInstruction(uint32_t inst);
 
+  bool EmulateBEQZ(uint32_t inst);
+  bool EmulateBNEZ(uint32_t inst);
+  bool EmulateJIRL(uint32_t inst);
+  bool EmulateB(uint32_t inst);
+  bool EmulateBL(uint32_t inst);
+  bool EmulateBEQ(uint32_t inst);
+  bool EmulateBNE(uint32_t inst);
+  bool EmulateBLT(uint32_t inst);
+  bool EmulateBGE(uint32_t inst);
+  bool EmulateBLTU(uint32_t inst);
+  bool EmulateBGEU(uint32_t inst);
   bool EmulateNonJMP(uint32_t inst);
+
+  bool EmulateBEQZ64(uint32_t inst);
+  bool EmulateBNEZ64(uint32_t inst);
+  bool EmulateJIRL64(uint32_t inst);
+  bool EmulateB64(uint32_t inst);
+  bool EmulateBL64(uint32_t inst);
+  bool EmulateBEQ64(uint32_t inst);
+  bool EmulateBNE64(uint32_t inst);
+  bool EmulateBLT64(uint32_t inst);
+  bool EmulateBGE64(uint32_t inst);
+  bool EmulateBLTU64(uint32_t inst);
+  bool EmulateBGEU64(uint32_t inst);
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_LOONGARCH_EMULATEINSTRUCTIONLOONGARCH_H

lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp

 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionLoongArch, InstructionLoongArch)
 
 namespace lldb_private {
 
 EmulateInstructionLoongArch::Opcode *
 EmulateInstructionLoongArch::GetOpcodeForInstruction(uint32_t inst) {
-  // TODO: Add the mask of jump instruction.
+  // TODO: Add the mask for other instruction.
   static EmulateInstructionLoongArch::Opcode g_opcodes[] = {
+      {0xfc000000, 0x40000000, &EmulateInstructionLoongArch::EmulateBEQZ,
+       "beqz rj, offs21"},
+      {0xfc000000, 0x44000000, &EmulateInstructionLoongArch::EmulateBNEZ,
+       "bnez rj, offs21"},
+      {0xfc000000, 0x4c000000, &EmulateInstructionLoongArch::EmulateJIRL,
+       "jirl rd, rj, offs16"},
+      {0xfc000000, 0x50000000, &EmulateInstructionLoongArch::EmulateB,
+       " b  offs26"},
+      {0xfc000000, 0x54000000, &EmulateInstructionLoongArch::EmulateBL,
+       "bl  offs26"},
+      {0xfc000000, 0x58000000, &EmulateInstructionLoongArch::EmulateBEQ,
+       "beq  rj, rd, offs16"},
+      {0xfc000000, 0x5c000000, &EmulateInstructionLoongArch::EmulateBNE,
+       "bne  rj, rd, offs16"},
+      {0xfc000000, 0x60000000, &EmulateInstructionLoongArch::EmulateBLT,
+       "blt  rj, rd, offs16"},
+      {0xfc000000, 0x64000000, &EmulateInstructionLoongArch::EmulateBGE,
+       "bge  rj, rd, offs16"},
+      {0xfc000000, 0x68000000, &EmulateInstructionLoongArch::EmulateBLTU,
+       "bltu rj, rd, offs16"},
+      {0xfc000000, 0x6c000000, &EmulateInstructionLoongArch::EmulateBGEU,
+       "bgeu rj, rd, offs16"},
       {0x00000000, 0x00000000, &EmulateInstructionLoongArch::EmulateNonJMP,
        "NonJMP"}};
   static const size_t num_loongarch_opcodes = std::size(g_opcodes);
 
   for (size_t i = 0; i < num_loongarch_opcodes; ++i)
     if ((g_opcodes[i].mask & inst) == g_opcodes[i].value)
       return &g_opcodes[i];
   return nullptr;
if (EmulateInstructionLoongArch::SupportsThisInstructionType(inst_type) &&
     return new EmulateInstructionLoongArch(arch);
   return nullptr;
 }
 
 bool EmulateInstructionLoongArch::SupportsThisArch(const ArchSpec &arch) {
   return arch.GetTriple().isLoongArch();
 }
 
+bool EmulateInstructionLoongArch::EmulateBEQZ(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBEQZ64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBNEZ(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBNEZ64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateJIRL(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateJIRL64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateB(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateB64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBL(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBL64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBEQ(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBEQ64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBNE(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateJIRL64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBLT(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBLT64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBGE(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBGE64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBLTU(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBLTU64(inst);
+  else
+    return false;
+}
+
+bool EmulateInstructionLoongArch::EmulateBGEU(uint32_t inst) {
+  if (IsLoongArch64())
+    return EmulateBGEU64(inst);
+  else
+    return false;
+}
+
 bool EmulateInstructionLoongArch::EmulateNonJMP(uint32_t inst) { return false; }
 
+// beqz rj, offs21
+// if GR[rj] == 0:
+//   PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBEQZ64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint64_t rj_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val == 0) {
+    imm_sign_extend = llvm::SignExtend64<23>(offs21 << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// bnez rj, offs21
+// if GR[rj] != 0:
+//   PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBNEZ64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint64_t rj_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  uint32_t offs21 = Bits32(inst, 25, 10) + (Bits32(inst, 4, 0) << 16);
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val != 0) {
+    imm_sign_extend = llvm::SignExtend64<23>(offs21 << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// jirl rd, rj, offs16
+// GR[rd] = PC + 4
+// PC = GR[rj] + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateJIRL64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  RegisterValue value;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  bool success = false;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  EmulateInstruction::Context ctx;
+  if (!WriteRegisterUnsigned(ctx, eRegisterKindLLDB, rd, pc + 4))
+    return false;
+  if (!ReadRegister(eRegisterKindLLDB, rj, value))
+    return false;
+  imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+  next_pc = value.GetAsUInt64() + imm_sign_extend;
+  return WritePC(next_pc);
+}
+
+// b offs26
+// PC = PC + SignExtend({offs26, 2' b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateB64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  uint32_t offs26 = Bits32(inst, 25, 10) + (Bits32(inst, 9, 0) << 16);
+  imm_sign_extend = llvm::SignExtend64<28>(offs26 << 2);
+  next_pc = pc + imm_sign_extend;
+  return WritePC(next_pc);
+}
+
+// bl offs26
+// GR[1] = PC + 4
+// PC = PC + SignExtend({offs26, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBL64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  EmulateInstruction::Context ctx;
+  if (!WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_loongarch, pc + 4))
+    return false;
+  uint32_t offs26 = Bits32(inst, 25, 10) + (Bits32(inst, 9, 0) << 16);
+  imm_sign_extend = llvm::SignExtend64<28>(offs26 << 2);
+  next_pc = pc + imm_sign_extend;
+  return WritePC(next_pc);
+}
+
+// beq rj, rd, offs16
+// if GR[rj] == GR[rd]:
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBEQ64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  uint64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val == rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// bne rj, rd, offs16
+// if GR[rj] != GR[rd]:
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBNE64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  uint64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val != rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// blt rj, rd, offs16
+// if signed(GR[rj]) < signed(GR[rd]):
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBLT64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  int64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val < rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// bge rj, rd, offs16
+// if signed(GR[rj]) >= signed(GR[rd]):
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBGE64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  int64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = (int64_t)ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val >= rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// bltu rj, rd, offs16
+// if unsigned(GR[rj]) < unsigned(GR[rd]):
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBLTU64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  uint64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val < rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
+// bgeu rj, rd, offs16
+// if unsigned(GR[rj]) >= unsigned(GR[rd]):
+//   PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+bool EmulateInstructionLoongArch::EmulateBGEU64(uint32_t inst) {
+  uint64_t next_pc, imm_sign_extend;
+  bool success = false;
+  uint32_t rj = Bits32(inst, 9, 5);
+  uint32_t rd = Bits32(inst, 4, 0);
+  uint64_t rj_val, rd_val;
+  uint64_t pc = ReadPC(&success);
+  if (!success)
+    return false;
+  rj_val = ReadRegisterUnsigned(eRegisterKindLLDB, rj, 0, &success);
+  if (!success)
+    return false;
+  rd_val = ReadRegisterUnsigned(eRegisterKindLLDB, rd, 0, &success);
+  if (!success)
+    return false;
+  if (rj_val >= rd_val) {
+    imm_sign_extend = llvm::SignExtend64<18>(Bits32(inst, 25, 10) << 2);
+    next_pc = pc + imm_sign_extend;
+    return WritePC(next_pc);
+  } else
+    return WritePC(pc + 4);
+}
+
 } // namespace lldb_private