[AArch64][DAGCombiner] fold instruction EON from ISD::XOR

[bcl5980]

Summary

This patch add a new target ISD AArch64ISD::SEON to represent scalar version instruction eon.
And select the ISD in the stage combine from this pattern:
((X & Z) ^ Y) ^ Z --> eon Y, (X | ~Z)

[bcl5980]

rebase code

[bcl5980]

needn't limit one of the op to constant.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
   ADDS,
   SUBS,
   ADCS,
   SBCS,
   ANDS,
 
   // Scalar logical instructions with not operand
   SBIC,
+  SEON,
 
   // Conditional compares. Operands: left,right,falsecc,cc,flags
   CCMP,
   CCMN,
   FCCMP,
 
   // Floating point comparison
   FCMP,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case AArch64ISD::FIRST_NUMBER:
     MAKE_CASE(AArch64ISD::ADC)
     MAKE_CASE(AArch64ISD::SBC)
     MAKE_CASE(AArch64ISD::ADDS)
     MAKE_CASE(AArch64ISD::SUBS)
     MAKE_CASE(AArch64ISD::ADCS)
     MAKE_CASE(AArch64ISD::SBCS)
     MAKE_CASE(AArch64ISD::ANDS)
     MAKE_CASE(AArch64ISD::SBIC)
+    MAKE_CASE(AArch64ISD::SEON)
     MAKE_CASE(AArch64ISD::CCMP)
     MAKE_CASE(AArch64ISD::CCMN)
     MAKE_CASE(AArch64ISD::FCCMP)
     MAKE_CASE(AArch64ISD::FCMP)
     MAKE_CASE(AArch64ISD::STRICT_FCMP)
     MAKE_CASE(AArch64ISD::STRICT_FCMPE)
     MAKE_CASE(AArch64ISD::DUP)
     MAKE_CASE(AArch64ISD::DUPLANE8)
if (A.getOpcode() == ISD::ADD) {
     if (SDValue R = DetectAddExtract(A.getOperand(1)))
       return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
                          DAG.getNode(ISD::ADD, SDLoc(A), A.getValueType(), R,
                                      A.getOperand(0)));
   }
   return SDValue();
 }
 
+// ((X & Z) ^ Y) ^ Z --> eon Y, (X | ~Z)
+static SDValue performXORCombineWithNotOp(SDNode *N, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32 && VT != MVT::i64)
+    return SDValue();
+
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+
+  SDLoc DL(N);
+  SDValue X, Y, NewZ;
+  auto canGetNotFromXorAnd = [&](SDNode *N, SDValue Op0, SDValue Op1) {
+    if (Op0.getOpcode() != ISD::XOR || !Op0.hasOneUse())
+      return false;
+
+    Y = Op0.getOperand(1);
+    if (isa<ConstantSDNode>(Y))
+      return false;
+
+    SDValue AndVal = Op0.getOperand(0);
+    if (AndVal.getOpcode() != ISD::AND || !AndVal.hasOneUse())
+      return false;
+
+    if (Op1 == AndVal.getOperand(0)) {
+      NewZ = DAG.getNOT(DL, Op1, VT);
+      X = AndVal.getOperand(1);
+      return true;
+    } else if (Op1 == AndVal.getOperand(1)) {
+      NewZ = DAG.getNOT(DL, Op1, VT);
+      X = AndVal.getOperand(0);
+      return true;
+    }
+
+    return false;
+  };
+
+  if (canGetNotFromXorAnd(N, LHS, RHS) || canGetNotFromXorAnd(N, RHS, LHS)) {
+    SDValue OrVal = DAG.getNode(ISD::OR, DL, VT, X, NewZ);
+    return DAG.getNode(AArch64ISD::SEON, DL, VT, Y, OrVal);
+  }
+
+  return SDValue();
+}
 
 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const AArch64Subtarget *Subtarget) {
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
 
+  if (SDValue R = performXORCombineWithNotOp(N, DAG))
+    return R;
+
   return foldVectorXorShiftIntoCmp(N, DAG, Subtarget);
 }
 
 SDValue
 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
                                      SelectionDAG &DAG,
                                      SmallVectorImpl<SDNode *> &Created) const {
   AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def AArch64adc_flag  : SDNode<"AArch64ISD::ADCS",  SDTBinaryArithWithFlagsInOut>;
 def AArch64sbc_flag  : SDNode<"AArch64ISD::SBCS",  SDTBinaryArithWithFlagsInOut>;
 
 def AArch64ccmp      : SDNode<"AArch64ISD::CCMP",  SDT_AArch64CCMP>;
 def AArch64ccmn      : SDNode<"AArch64ISD::CCMN",  SDT_AArch64CCMP>;
 def AArch64fccmp     : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
 
 def AArch64sbic  : SDNode<"AArch64ISD::SBIC",  SDTIntBinOp>;
+def AArch64seon  : SDNode<"AArch64ISD::SEON",  SDTIntBinOp>;
 
 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
 
 def AArch64fcmp         : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
 def AArch64strict_fcmp  : SDNode<"AArch64ISD::STRICT_FCMP", SDT_AArch64FCmp,
                                  [SDNPHasChain]>;
 def AArch64strict_fcmpe : SDNode<"AArch64ISD::STRICT_FCMPE", SDT_AArch64FCmp,
                                  [SDNPHasChain]>;
multiclass LogicalRegPat<SDPatternOperator OpNode, string INST> {
 
   def : Pat<(OpNode GPR64:$Xn, 
               (logical_shifted_reg64 GPR64:$Xm, logical_shift64:$shift)), 
             (!cast<Instruction>(INST # Xrs) GPR64:$Xn, GPR64:$Xm, 
               logical_shift64:$shift)>;
 }
 
 defm : LogicalRegPat<AArch64sbic, "BIC">;
+defm : LogicalRegPat<AArch64seon, "EON">;
 
 
 //===----------------------------------------------------------------------===//
 // One operand data processing instructions.
 //===----------------------------------------------------------------------===//
 
 defm CLS    : OneOperandData<0b000101, "cls">;
 defm CLZ    : OneOperandData<0b000100, "clz", ctlz>;

llvm/test/CodeGen/AArch64/logical-op-with-not.ll

; CHECK-NEXT:    ret
   %5 = zext i32 %4 to i64
   %6 = or i64 %5, %1
   ret i64 %6
 }
 
 define i64 @_Z6or_eon(i64 %0, i64 %1) {
 ; CHECK-LABEL: _Z6or_eon:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and x8, x0, #0xfffffffffffff000
-; CHECK-NEXT:    eor x8, x8, x1
-; CHECK-NEXT:    eor x0, x8, #0xfffffffffffff000
+; CHECK-NEXT:    orr x8, x0, #0xfff
+; CHECK-NEXT:    eon x0, x1, x8
 ; CHECK-NEXT:    ret
   %3 = and i64 %0, -4096
   %4 = xor i64 %3, %1
   %5 = xor i64 %4, -4096
   ret i64 %5
 }
 
 define i64 @or_eon2(i32 %0, i64 %1) {

 ; CHECK-NEXT:    eor x0, x8, x1
 ; CHECK-NEXT:    ret
   %3 = and i32 %0, -4096
   %4 = xor i32 %3, -4096
   %5 = zext i32 %4 to i64
   %6 = xor i64 %5, %1
   ret i64 %6
 }
+
+define i64 @_Z6or_eon4(i64 %0, i64 %1, i64 %2) {
+; CHECK-LABEL: _Z6or_eon4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orn x8, x0, x2
+; CHECK-NEXT:    eon x0, x1, x8
+; CHECK-NEXT:    ret
+  %4 = and i64 %0, %2
+  %5 = xor i64 %4, %1
+  %6 = xor i64 %5, %2
+  ret i64 %6
+}