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Differential D139492

[PowerPC][NFC] Test case update on ppc64-acc-regalloc-bugfix.ll
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Authored by tingwang on Dec 6 2022, 5:33 PM.

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Reviewers
nemanjai
stefanp
shchenz
Group Reviewers
Restricted Project
Commits
rG140a83e32f64: [PowerPC][NFC] Test case update on ppc64-acc-regalloc-bugfix.ll
Summary

Store initialized lane to get rid of undef behavior.

There is one case blocked by this undef behavior: by enable ppc-track-subreg-liveness and Policy.ShouldTrackLaneMasks together, we will observe verification failure in this original case due to the undefined behavior. To get rid of road block, we decided to remove this undef behavior.

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Event Timeline

tingwang created this revision.Dec 6 2022, 5:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 6 2022, 5:33 PM
Herald added subscribers: kbarton, qcolombet, MatzeB. · View Herald Transcript
tingwang requested review of this revision.Dec 6 2022, 5:33 PM
Herald added a subscriber: llvm-commits. · View Herald TranscriptDec 6 2022, 5:33 PM
Harbormaster completed remote builds in B201572: Diff 480719.Dec 6 2022, 5:35 PM
shchenz accepted this revision as: shchenz.Dec 7 2022, 12:15 AM

LGTM. Maybe it is better to explicitly indicate what will happen without this testcase change in the patch description.

This revision is now accepted and ready to land.Dec 7 2022, 12:15 AM
tingwang edited the summary of this revision. (Show Details)Dec 7 2022, 4:27 PM
This revision was landed with ongoing or failed builds.Dec 7 2022, 5:17 PM
Closed by commit rG140a83e32f64: [PowerPC][NFC] Test case update on ppc64-acc-regalloc-bugfix.ll (authored by tingwang). · Explain Why
This revision was automatically updated to reflect the committed changes.
tingwang added a commit: rG140a83e32f64: [PowerPC][NFC] Test case update on ppc64-acc-regalloc-bugfix.ll.
shchenz mentioned this in D109302: [PowerPC] Check subregister defines before removing XXMFACC/XXMTACC.Dec 13 2022, 5:52 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
4 lines

Diff 481115

llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
define void @copy_novsrp() local_unnamed_addr { define void @copy_novsrp() local_unnamed_addr {
; CHECK-LABEL: copy_novsrp: ; CHECK-LABEL: copy_novsrp:
; CHECK: # %bb.0: # %dmblvi_entry ; CHECK: # %bb.0: # %dmblvi_entry
; CHECK-NEXT: xxlxor v2, v2, v2 ; CHECK-NEXT: xxlxor v2, v2, v2
; CHECK-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-NEXT: xxlxor vs0, vs0, vs0
; CHECK-NEXT: xxlor vs3, v2, v2 ; CHECK-NEXT: xxlor vs3, v2, v2
; CHECK-NEXT: stxv vs1, 0(0) ; CHECK-NEXT: stxv vs0, 0(0)
dmblvi_entry: dmblvi_entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer) %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
%1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0) %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
%2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
store <16 x i8> %2, ptr null, align 1 store <16 x i8> %2, ptr null, align 1
unreachable unreachable
} }
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)