[PowerPC] remove XXSWAPD after load from CP which is a splat value

[tingwang]

Summary

If the value from constant-pool is a splat value of vector type, do not need swap after load from constant-pool.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

656

Seems for swap XXPERMDI (Immed == 0 || Immed == 3), if the input is a splat constant value, there is also an opportunity to optimize the swap away?

675

Can we also improve these opcodes with splat constant inputs?

[tingwang]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

656

Sure. I did not see any existing case improved by 0 or 3, and cannot see why we will hit these due to my limited knowledge. Since these two looks no harm to me, I will add them anyway. Thank you for pointing out and let me know if you have any IR case to show.

675

Sure. I will address those in separate patch if there is any opportunity. Thank you!

[tingwang]

Address comment.

[shchenz]

LGTM now. Thanks for the improvement.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

class PPCInstrInfo : public PPCGenInstrInfo {
   ArrayRef<unsigned> getStoreOpcodesForSpillArray() const;
   ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
   unsigned getSpillIndex(const TargetRegisterClass *RC) const;
   int16_t getFMAOpIdxInfo(unsigned Opcode) const;
   void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
                       SmallVectorImpl<MachineInstr *> &InsInstrs,
                       SmallVectorImpl<MachineInstr *> &DelInstrs,
                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
-  bool isLoadFromConstantPool(MachineInstr *I) const;
   Register
   generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
                           SmallVectorImpl<MachineInstr *> &InsInstrs) const;
-  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
   virtual void anchor();
 
 protected:
   /// Commutes the operands in the given instruction.
   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
   ///
   /// Do not call this method for a non-commutable instruction or for
   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
   /// Even though the instruction is commutable, the method may still
   /// fail to commute the operands, null pointer is returned in such cases.
   ///
   /// For example, we can commute rlwimi instructions, but only if the
   /// rotate amt is zero.  We also have to munge the immediates a bit.
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                        unsigned OpIdx1,
                                        unsigned OpIdx2) const override;
 
 public:
   explicit PPCInstrInfo(PPCSubtarget &STI);
 
+  bool isLoadFromConstantPool(MachineInstr *I) const;
+  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
+
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
   const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 
   bool isXFormMemOp(unsigned Opcode) const {
     return get(Opcode).TSFlags & PPCII::XFormMemOp;

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
           ToErase = &MI;
           Simplified = true;
           LLVM_DEBUG(dbgs() << "Optimizing swap(vsplt[b|h|w]|xxspltw) => "
                                "copy(vsplt[b|h|w]|xxspltw): ");
           LLVM_DEBUG(MI.dump());
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .add(MI.getOperand(1));
+        } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
+                   TII->isLoadFromConstantPool(DefMI)) {
+          const Constant *C = TII->getConstantFromConstantPool(DefMI);
+          if (C && C->getType()->isVectorTy() && C->getSplatValue()) {
+            ToErase = &MI;
+            Simplified = true;
+            LLVM_DEBUG(dbgs()
+                       << "Optimizing swap(splat pattern from constant-pool) "
+                          "=> copy(splat pattern from constant-pool): ");
+            LLVM_DEBUG(MI.dump());
+            BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
+                    MI.getOperand(0).getReg())
+                .add(MI.getOperand(1));
+          }
         }
         break;
       }
       case PPC::VSPLTB:
       case PPC::VSPLTH:
       case PPC::XXSPLTW: {
         unsigned MyOpcode = MI.getOpcode();
         unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
         Register TrueReg =
           TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
         if (!TrueReg.isVirtual())
           break;
         MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
         if (!DefMI)

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 ; P8BE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst1ll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
 define <2 x i64> @spltConst16kll() {
 ; P9BE-LABEL: spltConst16kll:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst16kll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI66_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 32767, i64 32767>
 }
 
 define <2 x i64> @spltConst32kll() {
 ; P9BE-LABEL: spltConst32kll:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst32kll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI67_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 65535, i64 65535>
 }
 
 define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
 ; P9BE-LABEL: fromRegsll:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvftoll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI78_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
 ; P9BE-LABEL: fromRegsConvftoll:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvdtoll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI87_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
 ; P9BE-LABEL: fromRegsConvdtoll:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst1ull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI97_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
 define <2 x i64> @spltConst16kull() {
 ; P9BE-LABEL: spltConst16kull:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst16kull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI98_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 32767, i64 32767>
 }
 
 define <2 x i64> @spltConst32kull() {
 ; P9BE-LABEL: spltConst32kull:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst32kull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI99_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 65535, i64 65535>
 }
 
 define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
 ; P9BE-LABEL: fromRegsull:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvftoull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI110_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
 ; P9BE-LABEL: fromRegsConvftoull:
 ; P9BE:       # %bb.0: # %entry

 ; P8BE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvdtoull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r3, r2, .LCPI119_0@toc@ha
 ; P8LE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lxvd2x v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
 ; P9BE-LABEL: fromRegsConvdtoull:
 ; P9BE:       # %bb.0: # %entry

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

entry:
   ret <16 x i8> %ret
 }
 
 define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: replace_undefs_in_splat:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P8-NEXT:    xxswapd v3, vs0
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r3
 ; CHECK-P8-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: replace_undefs_in_splat:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-P9-NEXT:    lxv v3, 0(r3)

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 ; Infinite loop identified in D62963.
 define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {
 ; CHECK-LABEL: fneg_fdiv_splat:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; CHECK-NEXT:    xxspltd 0, 1, 0
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-NEXT:    lxvd2x 1, 0, 3
-; CHECK-NEXT:    xvredp 2, 0
-; CHECK-NEXT:    xxswapd 1, 1
-; CHECK-NEXT:    xxlor 3, 1, 1
-; CHECK-NEXT:    xvnmsubadp 3, 0, 2
-; CHECK-NEXT:    xvmaddadp 2, 2, 3
-; CHECK-NEXT:    xvnmsubadp 1, 0, 2
-; CHECK-NEXT:    xvnmaddadp 2, 2, 1
-; CHECK-NEXT:    xvmuldp 34, 34, 2
-; CHECK-NEXT:    xvmuldp 35, 35, 2
+; CHECK-NEXT:    lxvd2x 2, 0, 3
+; CHECK-NEXT:    xvredp 1, 0
+; CHECK-NEXT:    xxlor 3, 2, 2
+; CHECK-NEXT:    xvnmsubadp 3, 0, 1
+; CHECK-NEXT:    xvmaddadp 1, 1, 3
+; CHECK-NEXT:    xvnmsubadp 2, 0, 1
+; CHECK-NEXT:    xvnmaddadp 1, 1, 2
+; CHECK-NEXT:    xvmuldp 34, 34, 1
+; CHECK-NEXT:    xvmuldp 35, 35, 1
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
   %div = fdiv contract reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
   %sub = fsub contract reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/fma-combine.ll

 }
 
 define <2 x double> @vec_neg_fma_flag_propagation(<2 x double> %a) {
 ; CHECK-FAST-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; CHECK-FAST-NEXT:    addi 3, 3, .LCPI8_0@toc@l
 ; CHECK-FAST-NEXT:    lxvd2x 0, 0, 3
-; CHECK-FAST-NEXT:    xxswapd 0, 0
 ; CHECK-FAST-NEXT:    xvmaddadp 34, 34, 0
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    lfs 1, .LCPI8_0@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmr 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI8_0@toc@l
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 0, 0
 ; CHECK-NEXT:    xvmaddadp 34, 34, 0
 ; CHECK-NEXT:    blr
 entry:
   %0 = call reassoc nnan <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> <double -1.0, double -1.0>, <2 x double> %a)
   ret <2 x double> %0
 }
 
 define dso_local double @fma_combine_const(double %a, double %b) {

llvm/test/CodeGen/PowerPC/fp-classify.ll

entry:
   %0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
   %cmpinf = fcmp oeq fp128 %0, 0xL00000000000000007FFF000000000000
   ret i1 %cmpinf
 }
 
 define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {
 ; P8-LABEL: abs_isinfv4f32:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P8-NEXT:    xvabssp 0, 34
+; P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; P8-NEXT:    lxvd2x 1, 0, 3
-; P8-NEXT:    xxswapd 1, 1
 ; P8-NEXT:    xvcmpeqsp 34, 0, 1
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfv4f32:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P9-NEXT:    xvabssp 0, 34
 ; P9-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; P9-NEXT:    lxv 1, 0(3)
 ; P9-NEXT:    xvcmpeqsp 34, 0, 1
 ; P9-NEXT:    blr
 entry:
   %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
   %cmpinf = fcmp oeq <4 x float> %0, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
   ret <4 x i1> %cmpinf
 }
 
 define <2 x i1> @abs_isinfv2f64(<2 x double> %x) {
 ; P8-LABEL: abs_isinfv2f64:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; P8-NEXT:    xvabsdp 0, 34
+; P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; P8-NEXT:    addi 3, 3, .LCPI4_0@toc@l
 ; P8-NEXT:    lxvd2x 1, 0, 3
-; P8-NEXT:    xxswapd 1, 1
 ; P8-NEXT:    xvcmpeqdp 34, 0, 1
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: abs_isinfv2f64:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; P9-NEXT:    xvabsdp 0, 34
 ; P9-NEXT:    addi 3, 3, .LCPI4_0@toc@l

llvm/test/CodeGen/PowerPC/mul-const-vector.ll

 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
 ; CHECK-NEXT: vsubuwm v[[REG6:[0-9]+]], v[[REG5]], v2
 
 define <2 x i64> @test1_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 ; CHECK-LABEL: test1_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]
 
 define <2 x i64> @test2_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test2_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]]
 
 define <2 x i64> @test3_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test3_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
 
 ; negtive constant
 
 define <2 x i64> @test4_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test4_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
 ; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
 ; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]
 
 define <2 x i64> @test5_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test5_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]]
 ; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]],
 ; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]]
 ; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]
 
 define <2 x i64> @test6_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15>         ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test6_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]]
 
 
 ; boundary case
 
 define <2 x i64> @test7_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test7_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
 
 define <2 x i64> @test8_v2i64(<2 x i64> %a) {
         %tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1]
         ret <2 x i64> %tmp.1
 }
 
 ; CHECK-LABEL: test8_v2i64:
-; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
-; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
+; CHECK-P8: lxvd2x v[[REG1:[0-9]+]], 0, r{{[0-9]+}}
 ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
 ; CHECK-NOT: vmul
 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
 ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2

llvm/test/CodeGen/PowerPC/pr25080.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
 
 define <8 x i16> @pr25080(<8 x i32> %a) {
 ; LE-LABEL: pr25080:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; LE-NEXT:    xxlxor 37, 37, 37
+; LE-NEXT:    xxlxor 36, 36, 36
 ; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; LE-NEXT:    lxvd2x 0, 0, 3
-; LE-NEXT:    xxswapd 36, 0
-; LE-NEXT:    xxland 34, 34, 36
-; LE-NEXT:    xxland 35, 35, 36
-; LE-NEXT:    vcmpequw 2, 2, 5
-; LE-NEXT:    vcmpequw 3, 3, 5
+; LE-NEXT:    xxland 34, 34, 0
+; LE-NEXT:    xxland 35, 35, 0
+; LE-NEXT:    vcmpequw 2, 2, 4
+; LE-NEXT:    vcmpequw 3, 3, 4
 ; LE-NEXT:    xxswapd 0, 34
 ; LE-NEXT:    mfvsrwz 3, 34
 ; LE-NEXT:    xxsldwi 1, 34, 34, 1
 ; LE-NEXT:    mfvsrwz 4, 35
 ; LE-NEXT:    xxsldwi 2, 34, 34, 3
 ; LE-NEXT:    mtvsrd 36, 3
 ; LE-NEXT:    mffprwz 3, 0
 ; LE-NEXT:    xxswapd 0, 35

llvm/test/CodeGen/PowerPC/pr47891.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 %struct.poly2 = type { [11 x i64] }
 
 ; Function Attrs: nofree norecurse nounwind
 define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
 ; CHECK-LABEL: poly2_lshift1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r4, 72
-; CHECK-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addis r6, r2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    ld r7, 64(r3)
-; CHECK-NEXT:    ld r8, 16(r3)
+; CHECK-NEXT:    ld r5, 64(r3)
+; CHECK-NEXT:    addis r6, r2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    addis r7, r2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    ld r8, 0(r3)
 ; CHECK-NEXT:    ld r10, 24(r3)
 ; CHECK-NEXT:    ld r11, 32(r3)
 ; CHECK-NEXT:    lxvd2x vs0, r3, r4
-; CHECK-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; CHECK-NEXT:    addi r6, r6, .LCPI0_1@toc@l
+; CHECK-NEXT:    addi r6, r6, .LCPI0_0@toc@l
+; CHECK-NEXT:    addi r7, r7, .LCPI0_1@toc@l
 ; CHECK-NEXT:    ld r12, 56(r3)
-; CHECK-NEXT:    lxvd2x vs1, 0, r5
-; CHECK-NEXT:    mtfprd f2, r7
-; CHECK-NEXT:    ld r5, 0(r3)
-; CHECK-NEXT:    xxswapd v2, vs0
-; CHECK-NEXT:    lxvd2x vs0, 0, r6
+; CHECK-NEXT:    lxvd2x v3, 0, r6
+; CHECK-NEXT:    lxvd2x v5, 0, r7
 ; CHECK-NEXT:    ld r6, 8(r3)
-; CHECK-NEXT:    rotldi r9, r5, 1
-; CHECK-NEXT:    sldi r5, r5, 1
-; CHECK-NEXT:    xxswapd v3, vs1
-; CHECK-NEXT:    std r5, 0(r3)
-; CHECK-NEXT:    rotldi r5, r10, 1
+; CHECK-NEXT:    ld r7, 16(r3)
+; CHECK-NEXT:    rotldi r9, r8, 1
+; CHECK-NEXT:    sldi r8, r8, 1
+; CHECK-NEXT:    std r8, 0(r3)
+; CHECK-NEXT:    rotldi r8, r10, 1
+; CHECK-NEXT:    xxswapd v2, vs0
+; CHECK-NEXT:    mtfprd f0, r5
 ; CHECK-NEXT:    rldimi r9, r6, 1, 0
 ; CHECK-NEXT:    rotldi r6, r6, 1
-; CHECK-NEXT:    xxpermdi v4, v2, vs2, 2
-; CHECK-NEXT:    xxswapd v5, vs0
-; CHECK-NEXT:    rldimi r6, r8, 1, 0
-; CHECK-NEXT:    rotldi r8, r8, 1
+; CHECK-NEXT:    rldimi r6, r7, 1, 0
+; CHECK-NEXT:    rotldi r7, r7, 1
 ; CHECK-NEXT:    std r9, 8(r3)
 ; CHECK-NEXT:    ld r9, 40(r3)
-; CHECK-NEXT:    rldimi r8, r10, 1, 0
-; CHECK-NEXT:    rldimi r5, r11, 1, 0
+; CHECK-NEXT:    rldimi r7, r10, 1, 0
+; CHECK-NEXT:    rldimi r8, r11, 1, 0
 ; CHECK-NEXT:    std r6, 16(r3)
+; CHECK-NEXT:    xxpermdi v4, v2, vs0, 2
+; CHECK-NEXT:    vsld v2, v2, v5
 ; CHECK-NEXT:    rotldi r10, r11, 1
 ; CHECK-NEXT:    ld r11, 48(r3)
-; CHECK-NEXT:    std r5, 32(r3)
-; CHECK-NEXT:    rotldi r6, r12, 1
-; CHECK-NEXT:    vsrd v3, v4, v3
+; CHECK-NEXT:    std r7, 24(r3)
+; CHECK-NEXT:    rotldi r7, r12, 1
 ; CHECK-NEXT:    rldimi r10, r9, 1, 0
 ; CHECK-NEXT:    rotldi r9, r9, 1
-; CHECK-NEXT:    std r8, 24(r3)
-; CHECK-NEXT:    vsld v2, v2, v5
-; CHECK-NEXT:    rotldi r5, r11, 1
+; CHECK-NEXT:    std r8, 32(r3)
+; CHECK-NEXT:    rotldi r6, r11, 1
 ; CHECK-NEXT:    rldimi r9, r11, 1, 0
 ; CHECK-NEXT:    std r10, 40(r3)
-; CHECK-NEXT:    rldimi r5, r12, 1, 0
-; CHECK-NEXT:    rldimi r6, r7, 1, 0
+; CHECK-NEXT:    vsrd v3, v4, v3
+; CHECK-NEXT:    rldimi r6, r12, 1, 0
+; CHECK-NEXT:    rldimi r7, r5, 1, 0
 ; CHECK-NEXT:    std r9, 48(r3)
+; CHECK-NEXT:    std r6, 56(r3)
+; CHECK-NEXT:    std r7, 64(r3)
 ; CHECK-NEXT:    xxlor vs0, v2, v3
-; CHECK-NEXT:    std r5, 56(r3)
-; CHECK-NEXT:    std r6, 64(r3)
 ; CHECK-NEXT:    xxswapd vs0, vs0
 ; CHECK-NEXT:    stxvd2x vs0, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %0 = load i64, ptr %p, align 8
   %shl = shl i64 %0, 1
   store i64 %shl, ptr %p, align 8
   %arrayidx.1 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 1

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 35
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; CHECK-P8-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 1, 0, 3
+; CHECK-P8-NEXT:    lxvd2x 2, 0, 3
 ; CHECK-P8-NEXT:    addi 3, 4, .LCPI12_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x 3, 0, 3
-; CHECK-P8-NEXT:    xxswapd 1, 1
-; CHECK-P8-NEXT:    xvmulsp 2, 35, 0
-; CHECK-P8-NEXT:    xxswapd 35, 3
-; CHECK-P8-NEXT:    xvmaddasp 1, 2, 0
-; CHECK-P8-NEXT:    xvmulsp 0, 0, 35
-; CHECK-P8-NEXT:    xvmulsp 0, 0, 1
+; CHECK-P8-NEXT:    xvmulsp 1, 35, 0
+; CHECK-P8-NEXT:    xvmaddasp 2, 1, 0
+; CHECK-P8-NEXT:    xvmulsp 0, 0, 3
+; CHECK-P8-NEXT:    xvmulsp 0, 0, 2
 ; CHECK-P8-NEXT:    xvmulsp 34, 34, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvrsqrtesp 0, 35
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI12_0@toc@l

 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtsp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB25_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 34
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
 ; CHECK-P8-NEXT:    addis 4, 2, .LCPI25_1@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI25_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 1, 0, 3
+; CHECK-P8-NEXT:    lxvd2x 2, 0, 3
 ; CHECK-P8-NEXT:    addi 3, 4, .LCPI25_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x 3, 0, 3
-; CHECK-P8-NEXT:    xxswapd 1, 1
-; CHECK-P8-NEXT:    xvmulsp 2, 34, 0
-; CHECK-P8-NEXT:    xxswapd 34, 3
-; CHECK-P8-NEXT:    xvmaddasp 1, 2, 0
-; CHECK-P8-NEXT:    xvmulsp 0, 2, 34
-; CHECK-P8-NEXT:    xvmulsp 34, 0, 1
+; CHECK-P8-NEXT:    xvmulsp 1, 34, 0
+; CHECK-P8-NEXT:    xvmaddasp 2, 1, 0
+; CHECK-P8-NEXT:    xvmulsp 0, 1, 3
+; CHECK-P8-NEXT:    xvmulsp 34, 0, 2
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB25_2:
 ; CHECK-P8-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo3_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvtsqrtsp 0, 34

 ; CHECK-P8-LABEL: hoo4_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtdp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB27_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtedp 0, 34
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 1, 0, 3
+; CHECK-P8-NEXT:    lxvd2x 2, 0, 3
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI27_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x 3, 0, 3
-; CHECK-P8-NEXT:    xxswapd 1, 1
-; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
-; CHECK-P8-NEXT:    xxswapd 3, 3
-; CHECK-P8-NEXT:    xxlor 4, 1, 1
-; CHECK-P8-NEXT:    xvmaddadp 4, 2, 0
+; CHECK-P8-NEXT:    xxlor 4, 2, 2
+; CHECK-P8-NEXT:    xvmuldp 1, 34, 0
+; CHECK-P8-NEXT:    xvmaddadp 4, 1, 0
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 3
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 4
-; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
-; CHECK-P8-NEXT:    xvmaddadp 1, 2, 0
-; CHECK-P8-NEXT:    xvmuldp 0, 2, 3
-; CHECK-P8-NEXT:    xvmuldp 34, 0, 1
+; CHECK-P8-NEXT:    xvmuldp 1, 34, 0
+; CHECK-P8-NEXT:    xvmaddadp 2, 1, 0
+; CHECK-P8-NEXT:    xvmuldp 0, 1, 3
+; CHECK-P8-NEXT:    xvmuldp 34, 0, 2
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB27_2:
 ; CHECK-P8-NEXT:    xvsqrtdp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo4_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvtsqrtdp 0, 34

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
 
 ; Check if this causes infinite loop when estimation disabled
 define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
 ; CHECK-LABEL: repeated_fp_divisor_noest:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
 ; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-NEXT:    xxswapd 35, 1
-; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    xxspltw 0, 0, 0
-; CHECK-NEXT:    xvdivsp 0, 35, 0
+; CHECK-NEXT:    xvdivsp 0, 1, 0
+; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    xxswapd 35, 1
 ; CHECK-NEXT:    xvmulsp 1, 34, 35
 ; CHECK-NEXT:    xvmulsp 34, 1, 0
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
   %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 
 define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
 ; CHECK-LABEL: repeated_fp_divisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    lxvd2x 2, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI1_1@toc@l
-; CHECK-NEXT:    xxswapd 1, 1
 ; CHECK-NEXT:    xxspltw 0, 0, 0
-; CHECK-NEXT:    xvresp 2, 0
-; CHECK-NEXT:    xvmaddasp 1, 0, 2
+; CHECK-NEXT:    xvresp 1, 0
+; CHECK-NEXT:    xvmaddasp 2, 0, 1
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    xvnmsubasp 2, 2, 1
+; CHECK-NEXT:    xvnmsubasp 1, 1, 2
 ; CHECK-NEXT:    xvmulsp 0, 34, 35
-; CHECK-NEXT:    xvmulsp 34, 0, 2
+; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
   %mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   ret i64 %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI24_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI24_1@toc@l
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vminub 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vaddubm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI25_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vaddubs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, %a
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI26_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vaddubs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI27_1@toc@l
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vminuh 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduhm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI28_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduhs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, %a
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI29_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduhs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI30_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI30_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI30_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI30_1@toc@l
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vminuw 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduws 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduws 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI33_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI33_1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI33_1@toc@l
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vminud 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vaddudm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
   %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
   %r = add <2 x i64> %s, <i64 42, i64 42>
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
 ; CHECK-NEXT:    xxleqv 0, 0, 0
+; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vaddudm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtud 2, 2, 3
 ; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, %a
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    addi 3, 3, .LCPI35_1@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI35_0@toc@l
-; CHECK-NEXT:    lxvd2x 1, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    xxleqv 0, 0, 0
-; CHECK-NEXT:    xxswapd 36, 1
+; CHECK-NEXT:    lxvd2x 36, 0, 3
 ; CHECK-NEXT:    vcmpgtud 3, 2, 3
 ; CHECK-NEXT:    vaddudm 2, 2, 4
 ; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r

llvm/test/CodeGen/PowerPC/signbit-shift.ll

 
 define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_zext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vsubuwm 2, 3, 2
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = zext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
   ret <4 x i32> %r
 }
 

 
 define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_sext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 35, 35, 35
 ; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = sext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 

 
 define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_lshr_not_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI15_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 

 
 define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: sub_lshr_not_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsrw 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
   %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
   ret <4 x i32> %r
 }
 

 
 define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
 ; CHECK-LABEL: sub_const_op_lshr_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
-; CHECK-NEXT:    xxswapd 35, 0
+; CHECK-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
   ret <4 x i32> %r
 }
 

llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll

 ; PPC-NEXT:    mtlr 0
 ; PPC-NEXT:    blr
 ;
 ; PPC64LE-LABEL: test_srem_vec:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lis 6, 1820
 ; PPC64LE-NEXT:    sldi 3, 3, 31
 ; PPC64LE-NEXT:    ori 6, 6, 29127
-; PPC64LE-NEXT:    sldi 5, 5, 31
-; PPC64LE-NEXT:    rldic 6, 6, 34, 3
 ; PPC64LE-NEXT:    sldi 4, 4, 31
-; PPC64LE-NEXT:    oris 6, 6, 29127
+; PPC64LE-NEXT:    rldic 6, 6, 34, 3
 ; PPC64LE-NEXT:    sradi 3, 3, 31
+; PPC64LE-NEXT:    oris 6, 6, 29127
+; PPC64LE-NEXT:    sradi 4, 4, 31
 ; PPC64LE-NEXT:    ori 7, 6, 7282
-; PPC64LE-NEXT:    sradi 5, 5, 31
+; PPC64LE-NEXT:    sldi 5, 5, 31
 ; PPC64LE-NEXT:    ori 6, 6, 7281
-; PPC64LE-NEXT:    sradi 4, 4, 31
 ; PPC64LE-NEXT:    mulhd 8, 3, 7
 ; PPC64LE-NEXT:    mulhd 7, 4, 7
+; PPC64LE-NEXT:    sradi 5, 5, 31
 ; PPC64LE-NEXT:    mulhd 6, 5, 6
 ; PPC64LE-NEXT:    rldicl 9, 8, 1, 63
 ; PPC64LE-NEXT:    rldicl 10, 7, 1, 63
-; PPC64LE-NEXT:    sub 6, 6, 5
 ; PPC64LE-NEXT:    add 8, 8, 9
-; PPC64LE-NEXT:    rldicl 9, 6, 1, 63
 ; PPC64LE-NEXT:    add 7, 7, 10
-; PPC64LE-NEXT:    sradi 6, 6, 3
 ; PPC64LE-NEXT:    sldi 10, 8, 3
-; PPC64LE-NEXT:    add 6, 6, 9
+; PPC64LE-NEXT:    sub 6, 6, 5
 ; PPC64LE-NEXT:    add 8, 8, 10
-; PPC64LE-NEXT:    addis 9, 2, .LCPI3_0@toc@ha
 ; PPC64LE-NEXT:    sldi 10, 7, 3
-; PPC64LE-NEXT:    sub 3, 3, 8
-; PPC64LE-NEXT:    addi 9, 9, .LCPI3_0@toc@l
+; PPC64LE-NEXT:    rldicl 9, 6, 1, 63
 ; PPC64LE-NEXT:    add 7, 7, 10
-; PPC64LE-NEXT:    sldi 8, 6, 3
-; PPC64LE-NEXT:    lxvd2x 0, 0, 9
-; PPC64LE-NEXT:    mtfprd 1, 3
+; PPC64LE-NEXT:    sub 3, 3, 8
+; PPC64LE-NEXT:    addis 8, 2, .LCPI3_1@toc@ha
+; PPC64LE-NEXT:    sradi 6, 6, 3
 ; PPC64LE-NEXT:    sub 4, 4, 7
-; PPC64LE-NEXT:    add 6, 6, 8
-; PPC64LE-NEXT:    addis 7, 2, .LCPI3_1@toc@ha
-; PPC64LE-NEXT:    mtfprd 2, 4
-; PPC64LE-NEXT:    add 4, 5, 6
-; PPC64LE-NEXT:    addi 3, 7, .LCPI3_1@toc@l
-; PPC64LE-NEXT:    addis 5, 2, .LCPI3_2@toc@ha
-; PPC64LE-NEXT:    mtfprd 4, 4
+; PPC64LE-NEXT:    mtfprd 0, 3
+; PPC64LE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; PPC64LE-NEXT:    addi 7, 8, .LCPI3_1@toc@l
+; PPC64LE-NEXT:    add 6, 6, 9
+; PPC64LE-NEXT:    mtfprd 1, 4
+; PPC64LE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; PPC64LE-NEXT:    lxvd2x 2, 0, 7
+; PPC64LE-NEXT:    sldi 8, 6, 3
 ; PPC64LE-NEXT:    lxvd2x 3, 0, 3
-; PPC64LE-NEXT:    addi 3, 5, .LCPI3_2@toc@l
-; PPC64LE-NEXT:    xxswapd 34, 0
-; PPC64LE-NEXT:    xxmrghd 35, 2, 1
-; PPC64LE-NEXT:    lxvd2x 0, 0, 3
-; PPC64LE-NEXT:    xxswapd 36, 4
-; PPC64LE-NEXT:    xxswapd 37, 3
-; PPC64LE-NEXT:    xxland 35, 35, 34
-; PPC64LE-NEXT:    xxland 34, 36, 34
+; PPC64LE-NEXT:    add 4, 6, 8
+; PPC64LE-NEXT:    addis 6, 2, .LCPI3_2@toc@ha
+; PPC64LE-NEXT:    xxmrghd 34, 1, 0
+; PPC64LE-NEXT:    add 3, 5, 4
+; PPC64LE-NEXT:    addi 4, 6, .LCPI3_2@toc@l
+; PPC64LE-NEXT:    xxswapd 35, 2
+; PPC64LE-NEXT:    mtfprd 0, 3
+; PPC64LE-NEXT:    lxvd2x 1, 0, 4
+; PPC64LE-NEXT:    xxland 34, 34, 3
 ; PPC64LE-NEXT:    xxswapd 36, 0
-; PPC64LE-NEXT:    vcmpequd 3, 3, 5
-; PPC64LE-NEXT:    vcmpequd 2, 2, 4
-; PPC64LE-NEXT:    xxlnor 0, 35, 35
-; PPC64LE-NEXT:    xxlnor 34, 34, 34
+; PPC64LE-NEXT:    vcmpequd 2, 2, 3
+; PPC64LE-NEXT:    xxswapd 35, 1
+; PPC64LE-NEXT:    xxland 36, 36, 3
+; PPC64LE-NEXT:    vcmpequd 3, 4, 3
+; PPC64LE-NEXT:    xxlnor 0, 34, 34
 ; PPC64LE-NEXT:    xxswapd 1, 0
 ; PPC64LE-NEXT:    mffprwz 4, 0
-; PPC64LE-NEXT:    xxswapd 2, 34
+; PPC64LE-NEXT:    xxlnor 34, 35, 35
 ; PPC64LE-NEXT:    mffprwz 3, 1
+; PPC64LE-NEXT:    xxswapd 2, 34
 ; PPC64LE-NEXT:    mffprwz 5, 2
 ; PPC64LE-NEXT:    blr
   %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
   %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
   ret <3 x i1> %cmp
 }

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; CHECK-P8-NEXT:    addi r5, r6, .LCPI3_2@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs3, 0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs2, 0, r5
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_4@toc@ha
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_1@toc@l
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_4@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    lxvd2x vs4, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    xxswapd v4, vs2
 ; CHECK-P8-NEXT:    xxswapd v0, vs4
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v0, vs0
+; CHECK-P8-NEXT:    lxvd2x v0, 0, r4
+; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r6, .LCPI4_2@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r5
 ; CHECK-P8-NEXT:    lxvd2x vs2, 0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_1@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    xxswapd v4, vs2
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v4
-; CHECK-P8-NEXT:    xxswapd v4, vs0
+; CHECK-P8-NEXT:    lxvd2x v4, 0, r4
+; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
-; CHECK-P8-NEXT:    xxswapd v3, vs0
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r4
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest2:

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v3, r3
 ; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P8-NEXT:    xxswapd v3, vs0
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r3
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3

 ; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-P8-NEXT:    addi r5, r6, .LCPI5_2@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
-; CHECK-P8-NEXT:    xxswapd v4, vs0
+; CHECK-P8-NEXT:    lxvd2x v4, 0, r4
+; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1

 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_4@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs2, 0, r4
 ; CHECK-P8-NEXT:    lxvd2x vs3, 0, r5
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
 ; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_1@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xxswapd v0, vs3
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v0, vs0
+; CHECK-P8-NEXT:    lxvd2x v0, 0, r4
+; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0

 ; CHECK-P8-NEXT:    li r6, 96
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    lxvd2x vs0, r4, r5
 ; CHECK-P8-NEXT:    xxswapd v4, vs2
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_1@toc@l
 ; CHECK-P8-NEXT:    xxswapd v5, vs3
 ; CHECK-P8-NEXT:    xxswapd v0, vs4
+; CHECK-P8-NEXT:    lxvd2x v9, 0, r4
+; CHECK-P8-NEXT:    li r4, 112
 ; CHECK-P8-NEXT:    xxswapd v6, vs0
 ; CHECK-P8-NEXT:    vperm v1, v2, v2, v3
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 112
 ; CHECK-P8-NEXT:    vperm v7, v2, v2, v4
 ; CHECK-P8-NEXT:    vperm v8, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v9, vs0
 ; CHECK-P8-NEXT:    vperm v5, v6, v6, v5
 ; CHECK-P8-NEXT:    vperm v0, v6, v6, v0
 ; CHECK-P8-NEXT:    vperm v3, v6, v6, v3
 ; CHECK-P8-NEXT:    vperm v4, v6, v6, v4
 ; CHECK-P8-NEXT:    vsld v1, v1, v9
 ; CHECK-P8-NEXT:    vsld v6, v7, v9
 ; CHECK-P8-NEXT:    vsld v5, v5, v9
 ; CHECK-P8-NEXT:    vsld v0, v0, v9

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
 ; CHECK-P8-NEXT:    mtvsrd v3, r3
 ; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P8-NEXT:    xxswapd v3, vs0
+; CHECK-P8-NEXT:    lxvd2x v3, 0, r3
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r3

 ; CHECK-P8-NEXT:    mtvsrwz v3, r4
 ; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-P8-NEXT:    addi r5, r6, .LCPI5_2@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
-; CHECK-P8-NEXT:    xxswapd v4, vs0
+; CHECK-P8-NEXT:    lxvd2x v4, 0, r4
+; CHECK-P8-NEXT:    li r4, 16
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1

 }
 
 define void @test8elt_signed(ptr noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
 ; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_2@toc@ha
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
+; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
 ; CHECK-P8-NEXT:    addi r6, r6, .LCPI6_2@toc@l
+; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_3@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r6
 ; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_4@toc@ha
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_3@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs2, 0, r5
 ; CHECK-P8-NEXT:    addi r5, r6, .LCPI6_4@toc@l
 ; CHECK-P8-NEXT:    lxvd2x vs3, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
 ; CHECK-P8-NEXT:    xxswapd v4, vs1
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r5, .LCPI6_1@toc@l
 ; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    xxswapd v0, vs3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v4, v3, v3, v4
 ; CHECK-P8-NEXT:    vperm v5, v3, v3, v5
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v0
-; CHECK-P8-NEXT:    xxswapd v0, vs0
+; CHECK-P8-NEXT:    lxvd2x v0, 0, r4
+; CHECK-P8-NEXT:    li r4, 48
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0

 ; CHECK-P8-NEXT:    lxvd2x vs1, 0, r5
 ; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_8@toc@ha
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_7@toc@l
 ; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_8@toc@l
 ; CHECK-P8-NEXT:    xxswapd v5, vs2
 ; CHECK-P8-NEXT:    xxswapd v0, vs3
 ; CHECK-P8-NEXT:    lxvd2x vs2, 0, r4
 ; CHECK-P8-NEXT:    lxvd2x vs3, 0, r5
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
+; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
 ; CHECK-P8-NEXT:    li r5, 96
 ; CHECK-P8-NEXT:    xxswapd v1, vs0
 ; CHECK-P8-NEXT:    xxswapd v6, vs1
 ; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_1@toc@l
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    lxvd2x v9, 0, r4
 ; CHECK-P8-NEXT:    li r4, 112
 ; CHECK-P8-NEXT:    xxswapd v7, vs2
 ; CHECK-P8-NEXT:    xxswapd v8, vs3
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v0, v2, v2, v0
-; CHECK-P8-NEXT:    xxswapd v9, vs0
 ; CHECK-P8-NEXT:    vperm v1, v2, v2, v1
 ; CHECK-P8-NEXT:    vperm v6, v2, v2, v6
 ; CHECK-P8-NEXT:    vperm v7, v2, v2, v7
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v8
 ; CHECK-P8-NEXT:    vsld v3, v3, v9
 ; CHECK-P8-NEXT:    vsld v0, v0, v9
 ; CHECK-P8-NEXT:    vsld v1, v1, v9
 ; CHECK-P8-NEXT:    vsld v6, v6, v9

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI155_0@toc@l
 ; PC64LE-NEXT:    lxvd2x 0, 0, 3
 ; PC64LE-NEXT:    addis 3, 2, .LCPI155_1@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI155_1@toc@l
 ; PC64LE-NEXT:    xxswapd 35, 0
-; PC64LE-NEXT:    lxvd2x 0, 0, 3
 ; PC64LE-NEXT:    vperm 2, 2, 2, 3
-; PC64LE-NEXT:    xxswapd 35, 0
+; PC64LE-NEXT:    lxvd2x 35, 0, 3
 ; PC64LE-NEXT:    vsld 2, 2, 3
 ; PC64LE-NEXT:    vsrad 2, 2, 3
 ; PC64LE-NEXT:    xvcvsxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI155_0@toc@ha

llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

 ; CHECK-P9-NOALTIVEC-NEXT:    extsb 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsb 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsb2d:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
-; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 56, i64 56>
   %shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>
   ret <2 x i64> %shr
 }

 ; CHECK-P9-NOALTIVEC-NEXT:    extsh 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsh 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsh2d:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
-; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 48, i64 48>
   %shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>
   ret <2 x i64> %shr
 }

 ; CHECK-P9-NOALTIVEC-NEXT:    extsw 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsw 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsw2d:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI4_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
-; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 32, i64 32>
   %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
   ret <2 x i64> %shr
 }

 ; CHECK-P9-NOALTIVEC-NEXT:    sradi 3, 3, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    sradi 4, 4, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_none:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI5_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
-; CHECK-P8-NEXT:    xxswapd 35, 0
+; CHECK-P8-NEXT:    lxvd2x 35, 0, 3
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 16, i64 16>
   %shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>
   ret <2 x i64> %shr
 }

llvm/test/CodeGen/PowerPC/vsx.ll

 ; CHECK-LE-LABEL: test69:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_0@toc@l
 ; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_1@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_1@toc@l
 ; CHECK-LE-NEXT:    xxswapd v3, vs0
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-LE-NEXT:    xxswapd v3, vs0
+; CHECK-LE-NEXT:    lxvd2x v3, 0, r3
 ; CHECK-LE-NEXT:    vsld v2, v2, v3
 ; CHECK-LE-NEXT:    vsrad v2, v2, v3
 ; CHECK-LE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i16> %a to <2 x double>
   ret <2 x double> %w
 
 

 ; CHECK-LE-LABEL: test70:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_0@toc@l
 ; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_1@toc@ha
 ; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_1@toc@l
 ; CHECK-LE-NEXT:    xxswapd v3, vs0
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-LE-NEXT:    xxswapd v3, vs0
+; CHECK-LE-NEXT:    lxvd2x v3, 0, r3
 ; CHECK-LE-NEXT:    vsld v2, v2, v3
 ; CHECK-LE-NEXT:    vsrad v2, v2, v3
 ; CHECK-LE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i8> %a to <2 x double>
   ret <2 x double> %w