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Differential D138768

[AArch64][SME]: Add streaming-compatible testing files(limit-duplane.ll, optimize-ptrue.ll, ptest.ll)
ClosedPublic

Authored by hassnaa-arm on Nov 27 2022, 1:20 PM.

Details

Reviewers
david-arm
sdesmalen
Commits
rG43eef9683369: [AArch64][SME]: Add streaming-compatible testing files.
Summary

Testing files:

  • limit-duplane.ll
  • optimize-ptrue.ll
  • ptest.ll

Diff Detail

Event Timeline

hassnaa-arm created this revision.Nov 27 2022, 1:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 27 2022, 1:20 PM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
hassnaa-arm requested review of this revision.Nov 27 2022, 1:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 27 2022, 1:20 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B199664: Diff 478115.Nov 27 2022, 3:07 PM
hassnaa-arm updated this revision to Diff 478186.Nov 28 2022, 3:56 AM

Remove ld2-alloca testing file, because it has invalid NEON instructions.

Harbormaster completed remote builds in B199719: Diff 478186.Nov 28 2022, 4:43 AM
hassnaa-arm edited the summary of this revision. (Show Details)Nov 28 2022, 4:46 AM
hassnaa-arm added a parent revision: D138682: [AArch64][SME]: Generate streaming-compatible code for bit counting/select.Nov 28 2022, 4:57 AM
hassnaa-arm retitled this revision from [AArch64][SME]: Add streaming-compatible testing files. to [AArch64][SME]: Add streaming-compatible testing files(limit-duplane.ll, optimize-ptrue.ll, ptest.ll).Nov 30 2022, 1:22 AM
david-arm added inline comments.Nov 30 2022, 5:45 AM
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
7

The first 3 tests in this file are identical. Can you delete these tests?

@ptest_v16i1_512bit_min_sve
@ptest_v16i1_512bit_sve

512

This looks identical the test above - can you delete it please?

hassnaa-arm marked 2 inline comments as done.Nov 30 2022, 6:23 AM
hassnaa-arm updated this revision to Diff 478931.Nov 30 2022, 6:24 AM

Remove redundant test cases

david-arm accepted this revision.Nov 30 2022, 6:26 AM

LGTM!

This revision is now accepted and ready to land.Nov 30 2022, 6:26 AM
sdesmalen added inline comments.Nov 30 2022, 6:28 AM
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
7

Can you use opaque pointers in these tests please?

hassnaa-arm marked an inline comment as done.Nov 30 2022, 6:56 AM
hassnaa-arm updated this revision to Diff 478937.Nov 30 2022, 6:56 AM

Use opaque PTRs.

sdesmalen accepted this revision.Nov 30 2022, 7:00 AM
Harbormaster completed remote builds in B200265: Diff 478937.Nov 30 2022, 8:03 AM
Closed by commit rG43eef9683369: [AArch64][SME]: Add streaming-compatible testing files. (authored by Hassnaa Hamdi <hassnaa.hamdi@arm.com>). · Explain WhyNov 30 2022, 5:15 PM
This revision was automatically updated to reflect the committed changes.
Hassnaa Hamdi <hassnaa.hamdi@arm.com> added a commit: rG43eef9683369: [AArch64][SME]: Add streaming-compatible testing files..

Revision Contents

Diff 478937

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
define <4 x i32> @test(ptr %arg1, ptr %arg2) {
; CHECK-LABEL: test:
sdesmalenUnsubmitted
Done
ReplyInline Actions

Can you use opaque pointers in these tests please?

sdesmalen: Can you use opaque pointers in these tests please?
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldp q2, q1, [x0, #32]
; CHECK-NEXT: add z2.s, z2.s, z2.s
; CHECK-NEXT: ldp q3, q4, [x0]
; CHECK-NEXT: mov z0.s, z1.s[2]
; CHECK-NEXT: add z1.s, z1.s, z1.s
; CHECK-NEXT: stp q2, q1, [x0, #32]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: add z2.s, z3.s, z3.s
; CHECK-NEXT: add z1.s, z4.s, z4.s
; CHECK-NEXT: stp q2, q1, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <16 x i32>, ptr %arg1, align 256
%1 = load <16 x i32>, ptr %arg2, align 256
%shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> <i32 14, i32 14, i32 14, i32 14>
%2 = add <16 x i32> %0, %0
store <16 x i32> %2, ptr %arg1, align 256
ret <4 x i32> %shvec
}
define <2 x i32> @test2(ptr %arg1, ptr %arg2) {
; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldp q2, q0, [x0, #32]
; CHECK-NEXT: ldp q4, q5, [x0]
; CHECK-NEXT: mov z1.d, z0.d
; CHECK-NEXT: add z3.s, z0.s, z0.s
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT: mov z0.s, s1
; CHECK-NEXT: add z1.s, z2.s, z2.s
; CHECK-NEXT: stp q1, q3, [x0, #32]
; CHECK-NEXT: add z1.s, z4.s, z4.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: add z2.s, z5.s, z5.s
; CHECK-NEXT: stp q1, q2, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <16 x i32>, ptr %arg1, align 256
%1 = load <16 x i32>, ptr %arg2, align 256
%shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14>
%2 = add <16 x i32> %0, %0
store <16 x i32> %2, ptr %arg1, align 256
ret <2 x i32> %shvec
}

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
define void @add_v4i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: add_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ldr s1, [x1]
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z1.h, z1.b
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: st1b { z0.h }, p0, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x i8>, ptr %a
%op2 = load <4 x i8>, ptr %b
%res = add <4 x i8> %op1, %op2
store <4 x i8> %res, ptr %a
ret void
}
define void @add_v8i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: add_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: add z0.b, z0.b, z1.b
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i8>, ptr %a
%op2 = load <8 x i8>, ptr %b
%res = add <8 x i8> %op1, %op2
store <8 x i8> %res, ptr %a
ret void
}
define void @add_v16i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: add_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: add z0.b, z0.b, z1.b
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i8>, ptr %a
%op2 = load <16 x i8>, ptr %b
%res = add <16 x i8> %op1, %op2
store <16 x i8> %res, ptr %a
ret void
}
define void @add_v32i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: add_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q2, q3, [x1]
; CHECK-NEXT: add z0.b, z0.b, z2.b
; CHECK-NEXT: add z1.b, z1.b, z3.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%op2 = load <32 x i8>, ptr %b
%res = add <32 x i8> %op1, %op2
store <32 x i8> %res, ptr %a
ret void
}
define void @add_v2i16(ptr %a, ptr %b, ptr %c) #0 {
; CHECK-LABEL: add_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ldrh w8, [x0, #2]
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: str w8, [sp, #4]
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: str w8, [sp]
; CHECK-NEXT: ldrh w8, [x1, #2]
; CHECK-NEXT: str w8, [sp, #12]
; CHECK-NEXT: ldrh w8, [x1]
; CHECK-NEXT: str w8, [sp, #8]
; CHECK-NEXT: ldp d0, d1, [sp]
; CHECK-NEXT: add z0.s, z0.s, z1.s
; CHECK-NEXT: st1h { z0.s }, p0, [x0]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
%op1 = load <2 x i16>, ptr %a
%op2 = load <2 x i16>, ptr %b
%res = add <2 x i16> %op1, %op2
store <2 x i16> %res, ptr %a
ret void
}
define void @add_v4i16(ptr %a, ptr %b, ptr %c) #0 {
; CHECK-LABEL: add_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x i16>, ptr %a
%op2 = load <4 x i16>, ptr %b
%res = add <4 x i16> %op1, %op2
store <4 x i16> %res, ptr %a
ret void
}
define void @add_v8i16(ptr %a, ptr %b, ptr %c) #0 {
; CHECK-LABEL: add_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i16>, ptr %a
%op2 = load <8 x i16>, ptr %b
%res = add <8 x i16> %op1, %op2
store <8 x i16> %res, ptr %a
ret void
}
define void @add_v16i16(ptr %a, ptr %b, ptr %c) #0 {
; CHECK-LABEL: add_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q2, q3, [x1]
; CHECK-NEXT: add z0.h, z0.h, z2.h
; CHECK-NEXT: add z1.h, z1.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%op2 = load <16 x i16>, ptr %b
%res = add <16 x i16> %op1, %op2
store <16 x i16> %res, ptr %a
ret void
}
define void @abs_v2i32(ptr %a) #0 {
; CHECK-LABEL: abs_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%op1 = load <2 x i32>, ptr %a
%res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false)
store <2 x i32> %res, ptr %a
ret void
}
define void @abs_v4i32(ptr %a) #0 {
; CHECK-LABEL: abs_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x i32>, ptr %a
%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false)
store <4 x i32> %res, ptr %a
ret void
}
define void @abs_v8i32(ptr %a) #0 {
; CHECK-LABEL: abs_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: abs z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false)
store <8 x i32> %res, ptr %a
ret void
}
define void @abs_v2i64(ptr %a) #0 {
; CHECK-LABEL: abs_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: abs z0.d, p0/m, z0.d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false)
store <2 x i64> %res, ptr %a
ret void
}
define void @abs_v4i64(ptr %a) #0 {
; CHECK-LABEL: abs_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: abs z0.d, p0/m, z0.d
; CHECK-NEXT: abs z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x i64>, ptr %a
%res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false)
store <4 x i64> %res, ptr %a
ret void
}
define void @fadd_v2f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ldr s1, [x1]
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret
%op1 = load <2 x half>, ptr %a
%op2 = load <2 x half>, ptr %b
%res = fadd <2 x half> %op1, %op2
store <2 x half> %res, ptr %a
ret void
}
define void @fadd_v4f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x half>, ptr %a
%op2 = load <4 x half>, ptr %b
%res = fadd <4 x half> %op1, %op2
store <4 x half> %res, ptr %a
ret void
}
define void @fadd_v8f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x half>, ptr %a
%op2 = load <8 x half>, ptr %b
%res = fadd <8 x half> %op1, %op2
store <8 x half> %res, ptr %a
ret void
}
define void @fadd_v16f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: ldp q2, q3, [x1]
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z2.h
; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x half>, ptr %a
%op2 = load <16 x half>, ptr %b
%res = fadd <16 x half> %op1, %op2
store <16 x half> %res, ptr %a
ret void
}
define void @fadd_v2f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%op1 = load <2 x float>, ptr %a
%op2 = load <2 x float>, ptr %b
%res = fadd <2 x float> %op1, %op2
store <2 x float> %res, ptr %a
ret void
}
define void @fadd_v4f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x float>, ptr %a
%op2 = load <4 x float>, ptr %b
%res = fadd <4 x float> %op1, %op2
store <4 x float> %res, ptr %a
ret void
}
define void @fadd_v8f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldp q2, q3, [x1]
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z2.s
; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x float>, ptr %a
%op2 = load <8 x float>, ptr %b
%res = fadd <8 x float> %op1, %op2
store <8 x float> %res, ptr %a
ret void
}
define void @fadd_v2f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%op1 = load <2 x double>, ptr %a
%op2 = load <2 x double>, ptr %b
%res = fadd <2 x double> %op1, %op2
store <2 x double> %res, ptr %a
ret void
}
define void @fadd_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fadd_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldp q2, q3, [x1]
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x double>, ptr %a
%op2 = load <4 x double>, ptr %b
%res = fadd <4 x double> %op1, %op2
store <4 x double> %res, ptr %a
ret void
}
declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
define i1 @ptest_v16i1(ptr %a, ptr %b) #0 {
; CHECK-LABEL: ptest_v16i1:
david-armUnsubmitted
Done
ReplyInline Actions

The first 3 tests in this file are identical. Can you delete these tests?

@ptest_v16i1_512bit_min_sve
@ptest_v16i1_512bit_sve

david-arm: The first 3 tests in this file are identical. Can you delete these tests?
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldp q2, q0, [x0, #32]
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: ldp q4, q3, [x0]
; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, z1.s
; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z1.s
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z5.s, z0.s[3]
; CHECK-NEXT: mov z6.s, z0.s[2]
; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z1.s
; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, z1.s
; CHECK-NEXT: mov z3.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z7.s, z0.s[1]
; CHECK-NEXT: mov z0.s, z2.s[3]
; CHECK-NEXT: mov z16.s, z2.s[2]
; CHECK-NEXT: mov z17.s, z2.s[1]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: strb w8, [sp, #12]
; CHECK-NEXT: mov z1.s, z3.s[3]
; CHECK-NEXT: mov z2.s, z3.s[2]
; CHECK-NEXT: mov z4.s, z3.s[1]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: strb w9, [sp, #8]
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: mov z18.s, z3.s[3]
; CHECK-NEXT: strb w8, [sp, #4]
; CHECK-NEXT: fmov w8, s6
; CHECK-NEXT: strb w10, [sp]
; CHECK-NEXT: fmov w10, s7
; CHECK-NEXT: strb w9, [sp, #15]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [sp, #14]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strb w10, [sp, #13]
; CHECK-NEXT: fmov w10, s17
; CHECK-NEXT: strb w9, [sp, #11]
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: strb w8, [sp, #10]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: strb w10, [sp, #9]
; CHECK-NEXT: fmov w10, s4
; CHECK-NEXT: mov z19.s, z3.s[2]
; CHECK-NEXT: mov z20.s, z3.s[1]
; CHECK-NEXT: strb w9, [sp, #7]
; CHECK-NEXT: fmov w9, s18
; CHECK-NEXT: strb w8, [sp, #6]
; CHECK-NEXT: fmov w8, s19
; CHECK-NEXT: strb w10, [sp, #5]
; CHECK-NEXT: fmov w10, s20
; CHECK-NEXT: strb w9, [sp, #3]
; CHECK-NEXT: strb w8, [sp, #2]
; CHECK-NEXT: strb w10, [sp, #1]
; CHECK-NEXT: ldr q0, [sp], #16
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: orv b0, p0, z0.b
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%v0 = bitcast ptr %a to <16 x float>*
%v1 = load <16 x float>, <16 x float>* %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
%v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
ret i1 %v3
}
define i1 @ptest_or_v16i1(ptr %a, ptr %b) #0 {
; CHECK-LABEL: ptest_or_v16i1:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldp q2, q1, [x0, #32]
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: ldp q4, q3, [x0]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z0.s
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z5.s, z1.s[2]
; CHECK-NEXT: mov z6.s, z1.s[1]
; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z0.s
; CHECK-NEXT: mov z3.s, z1.s[3]
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z4.s, z0.s
; CHECK-NEXT: mov z7.s, z2.s[3]
; CHECK-NEXT: mov z16.s, z2.s[2]
; CHECK-NEXT: mov z17.s, z2.s[1]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: strb w8, [sp, #12]
; CHECK-NEXT: mov z2.s, z1.s[3]
; CHECK-NEXT: mov z4.s, z1.s[2]
; CHECK-NEXT: mov z18.s, z1.s[1]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: strb w9, [sp, #8]
; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: mov z19.s, z1.s[3]
; CHECK-NEXT: strb w8, [sp, #4]
; CHECK-NEXT: fmov w8, s5
; CHECK-NEXT: strb w10, [sp]
; CHECK-NEXT: fmov w10, s6
; CHECK-NEXT: strb w9, [sp, #15]
; CHECK-NEXT: fmov w9, s7
; CHECK-NEXT: strb w8, [sp, #14]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strb w10, [sp, #13]
; CHECK-NEXT: fmov w10, s17
; CHECK-NEXT: strb w9, [sp, #11]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: strb w8, [sp, #10]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strb w10, [sp, #9]
; CHECK-NEXT: fmov w10, s18
; CHECK-NEXT: mov z20.s, z1.s[2]
; CHECK-NEXT: mov z21.s, z1.s[1]
; CHECK-NEXT: strb w9, [sp, #7]
; CHECK-NEXT: fmov w9, s19
; CHECK-NEXT: strb w8, [sp, #6]
; CHECK-NEXT: fmov w8, s20
; CHECK-NEXT: strb w10, [sp, #5]
; CHECK-NEXT: fmov w10, s21
; CHECK-NEXT: strb w9, [sp, #3]
; CHECK-NEXT: strb w8, [sp, #2]
; CHECK-NEXT: strb w10, [sp, #1]
; CHECK-NEXT: ldr q1, [x1, #48]
; CHECK-NEXT: ldr q5, [x1]
; CHECK-NEXT: ldr q7, [sp]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: ldp q6, q1, [x1, #16]
; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov z3.s, z2.s[3]
; CHECK-NEXT: mov z4.s, z2.s[2]
; CHECK-NEXT: mov z2.s, z2.s[1]
; CHECK-NEXT: strb w8, [sp, #28]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z6.s, z0.s
; CHECK-NEXT: mov z6.s, z1.s[3]
; CHECK-NEXT: mov z16.s, z1.s[2]
; CHECK-NEXT: mov z17.s, z1.s[1]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p0.s, p0/z, z5.s, z0.s
; CHECK-NEXT: mov z0.s, z1.s[3]
; CHECK-NEXT: mov z5.s, z1.s[2]
; CHECK-NEXT: mov z18.s, z1.s[1]
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: strb w8, [sp, #24]
; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strb w9, [sp, #20]
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: mov z19.s, z1.s[3]
; CHECK-NEXT: mov z20.s, z1.s[2]
; CHECK-NEXT: strb w10, [sp, #16]
; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: strb w8, [sp, #31]
; CHECK-NEXT: fmov w8, s6
; CHECK-NEXT: strb w9, [sp, #30]
; CHECK-NEXT: fmov w9, s16
; CHECK-NEXT: strb w10, [sp, #29]
; CHECK-NEXT: fmov w10, s17
; CHECK-NEXT: strb w8, [sp, #27]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w9, [sp, #26]
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: strb w10, [sp, #25]
; CHECK-NEXT: fmov w10, s18
; CHECK-NEXT: mov z21.s, z1.s[1]
; CHECK-NEXT: strb w8, [sp, #23]
; CHECK-NEXT: fmov w8, s19
; CHECK-NEXT: strb w9, [sp, #22]
; CHECK-NEXT: fmov w9, s20
; CHECK-NEXT: strb w10, [sp, #21]
; CHECK-NEXT: fmov w10, s21
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: strb w8, [sp, #19]
; CHECK-NEXT: strb w9, [sp, #18]
; CHECK-NEXT: strb w10, [sp, #17]
; CHECK-NEXT: ldr q0, [sp, #16]
; CHECK-NEXT: orr z0.d, z7.d, z0.d
; CHECK-NEXT: orv b0, p0, z0.b
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
%v0 = bitcast ptr %a to <16 x float>*
%v1 = load <16 x float>, <16 x float>* %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
%v3 = bitcast float* %b to <16 x float>*
%v4 = load <16 x float>, <16 x float>* %v3, align 4
%v5 = fcmp une <16 x float> %v4, zeroinitializer
%v6 = or <16 x i1> %v2, %v5
%v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6)
ret i1 %v7
}
declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)
;
; AND reduction.
;
define i1 @ptest_and_v16i1(ptr %a, ptr %b) #0 {
; CHECK-LABEL: ptest_and_v16i1:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: adrp x8, .LCPI2_0
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldp q2, q1, [x0, #32]
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]
; CHECK-NEXT: ldp q4, q3, [x0]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z2.s, z0.s
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z5.s, z1.s[2]
; CHECK-NEXT: mov z6.s, z1.s[1]
; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, z0.s
; CHECK-NEXT: mov z3.s, z1.s[3]
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z4.s, z0.s
; CHECK-NEXT: mov z7.s, z2.s[3]
; CHECK-NEXT: mov z16.s, z2.s[2]
; CHECK-NEXT: mov z17.s, z2.s[1]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: strb w8, [sp, #12]
; CHECK-NEXT: mov z2.s, z1.s[3]
; CHECK-NEXT: mov z4.s, z1.s[2]
; CHECK-NEXT: mov z18.s, z1.s[1]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: strb w9, [sp, #8]
; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: mov z19.s, z1.s[3]
; CHECK-NEXT: strb w8, [sp, #4]
; CHECK-NEXT: fmov w8, s5
; CHECK-NEXT: strb w10, [sp]
; CHECK-NEXT: fmov w10, s6
; CHECK-NEXT: strb w9, [sp, #15]
; CHECK-NEXT: fmov w9, s7
; CHECK-NEXT: strb w8, [sp, #14]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strb w10, [sp, #13]
; CHECK-NEXT: fmov w10, s17
; CHECK-NEXT: strb w9, [sp, #11]
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: strb w8, [sp, #10]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strb w10, [sp, #9]
; CHECK-NEXT: fmov w10, s18
; CHECK-NEXT: mov z20.s, z1.s[2]
; CHECK-NEXT: mov z21.s, z1.s[1]
; CHECK-NEXT: strb w9, [sp, #7]
; CHECK-NEXT: fmov w9, s19
; CHECK-NEXT: strb w8, [sp, #6]
; CHECK-NEXT: fmov w8, s20
; CHECK-NEXT: strb w10, [sp, #5]
; CHECK-NEXT: fmov w10, s21
; CHECK-NEXT: strb w9, [sp, #3]
; CHECK-NEXT: strb w8, [sp, #2]
; CHECK-NEXT: strb w10, [sp, #1]
; CHECK-NEXT: ldr q1, [x1, #48]
; CHECK-NEXT: ldr q5, [x1]
; CHECK-NEXT: ldr q7, [sp]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: ldp q6, q1, [x1, #16]
; CHECK-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov z3.s, z2.s[3]
; CHECK-NEXT: mov z4.s, z2.s[2]
; CHECK-NEXT: mov z2.s, z2.s[1]
; CHECK-NEXT: strb w8, [sp, #28]
; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, z0.s
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p1.s, p0/z, z6.s, z0.s
; CHECK-NEXT: mov z6.s, z1.s[3]
; CHECK-NEXT: mov z16.s, z1.s[2]
; CHECK-NEXT: mov z17.s, z1.s[1]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: fcmne p0.s, p0/z, z5.s, z0.s
; CHECK-NEXT: mov z0.s, z1.s[3]
; CHECK-NEXT: mov z5.s, z1.s[2]
; CHECK-NEXT: mov z18.s, z1.s[1]
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: strb w8, [sp, #24]
; CHECK-NEXT: fmov w10, s1
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strb w9, [sp, #20]
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: mov z19.s, z1.s[3]
; CHECK-NEXT: mov z20.s, z1.s[2]
; CHECK-NEXT: strb w10, [sp, #16]
; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: strb w8, [sp, #31]
; CHECK-NEXT: fmov w8, s6
; CHECK-NEXT: strb w9, [sp, #30]
; CHECK-NEXT: fmov w9, s16
; CHECK-NEXT: strb w10, [sp, #29]
; CHECK-NEXT: fmov w10, s17
; CHECK-NEXT: strb w8, [sp, #27]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w9, [sp, #26]
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: strb w10, [sp, #25]
; CHECK-NEXT: fmov w10, s18
; CHECK-NEXT: mov z21.s, z1.s[1]
; CHECK-NEXT: strb w8, [sp, #23]
; CHECK-NEXT: fmov w8, s19
; CHECK-NEXT: strb w9, [sp, #22]
; CHECK-NEXT: fmov w9, s20
; CHECK-NEXT: strb w10, [sp, #21]
; CHECK-NEXT: fmov w10, s21
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: strb w8, [sp, #19]
; CHECK-NEXT: strb w9, [sp, #18]
; CHECK-NEXT: strb w10, [sp, #17]
; CHECK-NEXT: ldr q0, [sp, #16]
; CHECK-NEXT: and z0.d, z7.d, z0.d
; CHECK-NEXT: andv b0, p0, z0.b
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
%v0 = bitcast ptr %a to <16 x float>*
%v1 = load <16 x float>, <16 x float>* %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
%v3 = bitcast float* %b to <16 x float>*
%v4 = load <16 x float>, <16 x float>* %v3, align 4
%v5 = fcmp une <16 x float> %v4, zeroinitializer
%v6 = and <16 x i1> %v2, %v5
%v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)
ret i1 %v7
}
attributes #0 = { "target-features"="+sve" }
declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)
david-armUnsubmitted
Done
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This looks identical the test above - can you delete it please?

david-arm: This looks identical the test above - can you delete it please?