[mlir][spirv] Add group ops

[Hardcode84]

Summary

Also, gen_spirv_dialect script was broken was broken due to SPV->SPIRV renamings.

[Hardcode84]

test roundtrip

[antiagainst]

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

22

Can you update the summary and description to match the extension spec wording?

It's a bit annoying that the main SPIR-V spec only says "TBD" and no explanation so this is inheriting that. We'd prefer to have clear semantics here though. Diverging here is fine; the automatic importing tool is only meant for simplifying the process of defining new ops; some manual modification before/after is fine.

53

This and the result should be changed to SPIRV_ScalarOrVectorOf<SPIRV_Float>?

Similarly for the following places where we also use SPIRV_Scalar?

[Hardcode84]

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

53

For non-KHR ops spec says

Result Type must be a 16-bit, 32-bit, or 64-bit floating-point type scalar.
The type of X must be the same as Result Type.

Not vector, so I'll change them to just SPIRV_Float/SPIRV_Integer

[Hardcode84]

update types and description

[Hardcode84]

Not vector, so I'll change them to just SPIRV_Float/SPIRV_Integer

Nevermind, looked in wrong place

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

 def SPIRV_OC_OpSelectionMerge             : I32EnumAttrCase<"OpSelectionMerge", 247>;
 def SPIRV_OC_OpLabel                      : I32EnumAttrCase<"OpLabel", 248>;
 def SPIRV_OC_OpBranch                     : I32EnumAttrCase<"OpBranch", 249>;
 def SPIRV_OC_OpBranchConditional          : I32EnumAttrCase<"OpBranchConditional", 250>;
 def SPIRV_OC_OpReturn                     : I32EnumAttrCase<"OpReturn", 253>;
 def SPIRV_OC_OpReturnValue                : I32EnumAttrCase<"OpReturnValue", 254>;
 def SPIRV_OC_OpUnreachable                : I32EnumAttrCase<"OpUnreachable", 255>;
 def SPIRV_OC_OpGroupBroadcast             : I32EnumAttrCase<"OpGroupBroadcast", 263>;
+def SPIRV_OC_OpGroupIAdd                  : I32EnumAttrCase<"OpGroupIAdd", 264>;
+def SPIRV_OC_OpGroupFAdd                  : I32EnumAttrCase<"OpGroupFAdd", 265>;
+def SPIRV_OC_OpGroupFMin                  : I32EnumAttrCase<"OpGroupFMin", 266>;
+def SPIRV_OC_OpGroupUMin                  : I32EnumAttrCase<"OpGroupUMin", 267>;
+def SPIRV_OC_OpGroupSMin                  : I32EnumAttrCase<"OpGroupSMin", 268>;
+def SPIRV_OC_OpGroupFMax                  : I32EnumAttrCase<"OpGroupFMax", 269>;
+def SPIRV_OC_OpGroupUMax                  : I32EnumAttrCase<"OpGroupUMax", 270>;
+def SPIRV_OC_OpGroupSMax                  : I32EnumAttrCase<"OpGroupSMax", 271>;
 def SPIRV_OC_OpNoLine                     : I32EnumAttrCase<"OpNoLine", 317>;
 def SPIRV_OC_OpModuleProcessed            : I32EnumAttrCase<"OpModuleProcessed", 330>;
 def SPIRV_OC_OpGroupNonUniformElect       : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
 def SPIRV_OC_OpGroupNonUniformBroadcast   : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>;
 def SPIRV_OC_OpGroupNonUniformBallot      : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
 def SPIRV_OC_OpGroupNonUniformShuffle     : I32EnumAttrCase<"OpGroupNonUniformShuffle", 345>;
 def SPIRV_OC_OpGroupNonUniformShuffleXor  : I32EnumAttrCase<"OpGroupNonUniformShuffleXor", 346>;
 def SPIRV_OC_OpGroupNonUniformShuffleUp   : I32EnumAttrCase<"OpGroupNonUniformShuffleUp", 347>;

 def SPIRV_OC_OpCooperativeMatrixLoadNV    : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>;
 def SPIRV_OC_OpCooperativeMatrixStoreNV   : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>;
 def SPIRV_OC_OpCooperativeMatrixMulAddNV  : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
 def SPIRV_OC_OpCooperativeMatrixLengthNV  : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
 def SPIRV_OC_OpSubgroupBlockReadINTEL     : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
 def SPIRV_OC_OpSubgroupBlockWriteINTEL    : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
 def SPIRV_OC_OpAssumeTrueKHR              : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
 def SPIRV_OC_OpAtomicFAddEXT              : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
+def SPIRV_OC_OpGroupIMulKHR               : I32EnumAttrCase<"OpGroupIMulKHR", 6401>;
+def SPIRV_OC_OpGroupFMulKHR               : I32EnumAttrCase<"OpGroupFMulKHR", 6402>;
 
 def SPIRV_OC_OpTypeJointMatrixINTEL       : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
 def SPIRV_OC_OpJointMatrixLoadINTEL       : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
 def SPIRV_OC_OpJointMatrixStoreINTEL      : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
 def SPIRV_OC_OpJointMatrixMadINTEL        : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
 def SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL : I32EnumAttrCase<"OpJointMatrixWorkItemLengthINTEL", 6410>;
 
 def SPIRV_OpcodeAttr :
     SPIRV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
-      SPIRV_OC_OpNop, SPIRV_OC_OpUndef, SPIRV_OC_OpSourceContinued, SPIRV_OC_OpSource,
-      SPIRV_OC_OpSourceExtension, SPIRV_OC_OpName, SPIRV_OC_OpMemberName, SPIRV_OC_OpString,
-      SPIRV_OC_OpLine, SPIRV_OC_OpExtension, SPIRV_OC_OpExtInstImport, SPIRV_OC_OpExtInst,
+      SPIRV_OC_OpNop, SPIRV_OC_OpUndef, SPIRV_OC_OpSourceContinued,
+      SPIRV_OC_OpSource, SPIRV_OC_OpSourceExtension, SPIRV_OC_OpName,
+      SPIRV_OC_OpMemberName, SPIRV_OC_OpString, SPIRV_OC_OpLine,
+      SPIRV_OC_OpExtension, SPIRV_OC_OpExtInstImport, SPIRV_OC_OpExtInst,
       SPIRV_OC_OpMemoryModel, SPIRV_OC_OpEntryPoint, SPIRV_OC_OpExecutionMode,
-      SPIRV_OC_OpCapability, SPIRV_OC_OpTypeVoid, SPIRV_OC_OpTypeBool, SPIRV_OC_OpTypeInt,
-      SPIRV_OC_OpTypeFloat, SPIRV_OC_OpTypeVector, SPIRV_OC_OpTypeMatrix,
-      SPIRV_OC_OpTypeImage, SPIRV_OC_OpTypeSampledImage, SPIRV_OC_OpTypeArray,
-      SPIRV_OC_OpTypeRuntimeArray, SPIRV_OC_OpTypeStruct, SPIRV_OC_OpTypePointer,
-      SPIRV_OC_OpTypeFunction, SPIRV_OC_OpTypeForwardPointer, SPIRV_OC_OpConstantTrue,
-      SPIRV_OC_OpConstantFalse, SPIRV_OC_OpConstant, SPIRV_OC_OpConstantComposite,
-      SPIRV_OC_OpConstantNull, SPIRV_OC_OpSpecConstantTrue, SPIRV_OC_OpSpecConstantFalse,
-      SPIRV_OC_OpSpecConstant, SPIRV_OC_OpSpecConstantComposite, SPIRV_OC_OpSpecConstantOp,
-      SPIRV_OC_OpFunction, SPIRV_OC_OpFunctionParameter, SPIRV_OC_OpFunctionEnd,
-      SPIRV_OC_OpFunctionCall, SPIRV_OC_OpVariable, SPIRV_OC_OpLoad, SPIRV_OC_OpStore,
-      SPIRV_OC_OpCopyMemory, SPIRV_OC_OpAccessChain, SPIRV_OC_OpPtrAccessChain,
-      SPIRV_OC_OpInBoundsPtrAccessChain, SPIRV_OC_OpDecorate, SPIRV_OC_OpMemberDecorate,
-      SPIRV_OC_OpVectorExtractDynamic, SPIRV_OC_OpVectorInsertDynamic,
-      SPIRV_OC_OpVectorShuffle, SPIRV_OC_OpCompositeConstruct, SPIRV_OC_OpCompositeExtract,
+      SPIRV_OC_OpCapability, SPIRV_OC_OpTypeVoid, SPIRV_OC_OpTypeBool,
+      SPIRV_OC_OpTypeInt, SPIRV_OC_OpTypeFloat, SPIRV_OC_OpTypeVector,
+      SPIRV_OC_OpTypeMatrix, SPIRV_OC_OpTypeImage, SPIRV_OC_OpTypeSampledImage,
+      SPIRV_OC_OpTypeArray, SPIRV_OC_OpTypeRuntimeArray, SPIRV_OC_OpTypeStruct,
+      SPIRV_OC_OpTypePointer, SPIRV_OC_OpTypeFunction, SPIRV_OC_OpTypeForwardPointer,
+      SPIRV_OC_OpConstantTrue, SPIRV_OC_OpConstantFalse, SPIRV_OC_OpConstant,
+      SPIRV_OC_OpConstantComposite, SPIRV_OC_OpConstantNull,
+      SPIRV_OC_OpSpecConstantTrue, SPIRV_OC_OpSpecConstantFalse,
+      SPIRV_OC_OpSpecConstant, SPIRV_OC_OpSpecConstantComposite,
+      SPIRV_OC_OpSpecConstantOp, SPIRV_OC_OpFunction, SPIRV_OC_OpFunctionParameter,
+      SPIRV_OC_OpFunctionEnd, SPIRV_OC_OpFunctionCall, SPIRV_OC_OpVariable,
+      SPIRV_OC_OpLoad, SPIRV_OC_OpStore, SPIRV_OC_OpCopyMemory,
+      SPIRV_OC_OpAccessChain, SPIRV_OC_OpPtrAccessChain,
+      SPIRV_OC_OpInBoundsPtrAccessChain, SPIRV_OC_OpDecorate,
+      SPIRV_OC_OpMemberDecorate, SPIRV_OC_OpVectorExtractDynamic,
+      SPIRV_OC_OpVectorInsertDynamic, SPIRV_OC_OpVectorShuffle,
+      SPIRV_OC_OpCompositeConstruct, SPIRV_OC_OpCompositeExtract,
       SPIRV_OC_OpCompositeInsert, SPIRV_OC_OpTranspose, SPIRV_OC_OpImageDrefGather,
       SPIRV_OC_OpImage, SPIRV_OC_OpImageQuerySize, SPIRV_OC_OpConvertFToU,
       SPIRV_OC_OpConvertFToS, SPIRV_OC_OpConvertSToF, SPIRV_OC_OpConvertUToF,
-      SPIRV_OC_OpUConvert, SPIRV_OC_OpSConvert, SPIRV_OC_OpFConvert, SPIRV_OC_OpPtrCastToGeneric,
-      SPIRV_OC_OpGenericCastToPtr, SPIRV_OC_OpGenericCastToPtrExplicit, SPIRV_OC_OpBitcast,
-      SPIRV_OC_OpSNegate, SPIRV_OC_OpFNegate, SPIRV_OC_OpIAdd, SPIRV_OC_OpFAdd,
-      SPIRV_OC_OpISub, SPIRV_OC_OpFSub, SPIRV_OC_OpIMul, SPIRV_OC_OpFMul, SPIRV_OC_OpUDiv,
-      SPIRV_OC_OpSDiv, SPIRV_OC_OpFDiv, SPIRV_OC_OpUMod, SPIRV_OC_OpSRem, SPIRV_OC_OpSMod,
-      SPIRV_OC_OpFRem, SPIRV_OC_OpFMod, SPIRV_OC_OpVectorTimesScalar,
-      SPIRV_OC_OpMatrixTimesScalar, SPIRV_OC_OpMatrixTimesMatrix, SPIRV_OC_OpIAddCarry,
-      SPIRV_OC_OpISubBorrow, SPIRV_OC_OpUMulExtended, SPIRV_OC_OpSMulExtended, SPIRV_OC_OpIsNan,
-      SPIRV_OC_OpIsInf, SPIRV_OC_OpOrdered, SPIRV_OC_OpUnordered, SPIRV_OC_OpLogicalEqual,
-      SPIRV_OC_OpLogicalNotEqual, SPIRV_OC_OpLogicalOr, SPIRV_OC_OpLogicalAnd, SPIRV_OC_OpLogicalNot,
-      SPIRV_OC_OpSelect, SPIRV_OC_OpIEqual, SPIRV_OC_OpINotEqual, SPIRV_OC_OpUGreaterThan,
-      SPIRV_OC_OpSGreaterThan, SPIRV_OC_OpUGreaterThanEqual, SPIRV_OC_OpSGreaterThanEqual,
-      SPIRV_OC_OpULessThan, SPIRV_OC_OpSLessThan, SPIRV_OC_OpULessThanEqual,
-      SPIRV_OC_OpSLessThanEqual, SPIRV_OC_OpFOrdEqual, SPIRV_OC_OpFUnordEqual,
-      SPIRV_OC_OpFOrdNotEqual, SPIRV_OC_OpFUnordNotEqual, SPIRV_OC_OpFOrdLessThan,
-      SPIRV_OC_OpFUnordLessThan, SPIRV_OC_OpFOrdGreaterThan, SPIRV_OC_OpFUnordGreaterThan,
-      SPIRV_OC_OpFOrdLessThanEqual, SPIRV_OC_OpFUnordLessThanEqual,
-      SPIRV_OC_OpFOrdGreaterThanEqual, SPIRV_OC_OpFUnordGreaterThanEqual,
-      SPIRV_OC_OpShiftRightLogical, SPIRV_OC_OpShiftRightArithmetic,
-      SPIRV_OC_OpShiftLeftLogical, SPIRV_OC_OpBitwiseOr, SPIRV_OC_OpBitwiseXor,
-      SPIRV_OC_OpBitwiseAnd, SPIRV_OC_OpNot, SPIRV_OC_OpBitFieldInsert,
-      SPIRV_OC_OpBitFieldSExtract, SPIRV_OC_OpBitFieldUExtract, SPIRV_OC_OpBitReverse,
-      SPIRV_OC_OpBitCount, SPIRV_OC_OpControlBarrier, SPIRV_OC_OpMemoryBarrier,
-      SPIRV_OC_OpAtomicExchange, SPIRV_OC_OpAtomicCompareExchange,
-      SPIRV_OC_OpAtomicCompareExchangeWeak, SPIRV_OC_OpAtomicIIncrement,
-      SPIRV_OC_OpAtomicIDecrement, SPIRV_OC_OpAtomicIAdd, SPIRV_OC_OpAtomicISub,
-      SPIRV_OC_OpAtomicSMin, SPIRV_OC_OpAtomicUMin, SPIRV_OC_OpAtomicSMax,
-      SPIRV_OC_OpAtomicUMax, SPIRV_OC_OpAtomicAnd, SPIRV_OC_OpAtomicOr, SPIRV_OC_OpAtomicXor,
-      SPIRV_OC_OpPhi, SPIRV_OC_OpLoopMerge, SPIRV_OC_OpSelectionMerge, SPIRV_OC_OpLabel,
-      SPIRV_OC_OpBranch, SPIRV_OC_OpBranchConditional, SPIRV_OC_OpReturn,
-      SPIRV_OC_OpReturnValue, SPIRV_OC_OpUnreachable, SPIRV_OC_OpGroupBroadcast,
+      SPIRV_OC_OpUConvert, SPIRV_OC_OpSConvert, SPIRV_OC_OpFConvert,
+      SPIRV_OC_OpPtrCastToGeneric, SPIRV_OC_OpGenericCastToPtr,
+      SPIRV_OC_OpGenericCastToPtrExplicit, SPIRV_OC_OpBitcast, SPIRV_OC_OpSNegate,
+      SPIRV_OC_OpFNegate, SPIRV_OC_OpIAdd, SPIRV_OC_OpFAdd, SPIRV_OC_OpISub,
+      SPIRV_OC_OpFSub, SPIRV_OC_OpIMul, SPIRV_OC_OpFMul, SPIRV_OC_OpUDiv,
+      SPIRV_OC_OpSDiv, SPIRV_OC_OpFDiv, SPIRV_OC_OpUMod, SPIRV_OC_OpSRem,
+      SPIRV_OC_OpSMod, SPIRV_OC_OpFRem, SPIRV_OC_OpFMod,
+      SPIRV_OC_OpVectorTimesScalar, SPIRV_OC_OpMatrixTimesScalar,
+      SPIRV_OC_OpMatrixTimesMatrix, SPIRV_OC_OpIAddCarry, SPIRV_OC_OpISubBorrow,
+      SPIRV_OC_OpUMulExtended, SPIRV_OC_OpSMulExtended, SPIRV_OC_OpIsNan,
+      SPIRV_OC_OpIsInf, SPIRV_OC_OpOrdered, SPIRV_OC_OpUnordered,
+      SPIRV_OC_OpLogicalEqual, SPIRV_OC_OpLogicalNotEqual, SPIRV_OC_OpLogicalOr,
+      SPIRV_OC_OpLogicalAnd, SPIRV_OC_OpLogicalNot, SPIRV_OC_OpSelect,
+      SPIRV_OC_OpIEqual, SPIRV_OC_OpINotEqual, SPIRV_OC_OpUGreaterThan,
+      SPIRV_OC_OpSGreaterThan, SPIRV_OC_OpUGreaterThanEqual,
+      SPIRV_OC_OpSGreaterThanEqual, SPIRV_OC_OpULessThan, SPIRV_OC_OpSLessThan,
+      SPIRV_OC_OpULessThanEqual, SPIRV_OC_OpSLessThanEqual, SPIRV_OC_OpFOrdEqual,
+      SPIRV_OC_OpFUnordEqual, SPIRV_OC_OpFOrdNotEqual, SPIRV_OC_OpFUnordNotEqual,
+      SPIRV_OC_OpFOrdLessThan, SPIRV_OC_OpFUnordLessThan, SPIRV_OC_OpFOrdGreaterThan,
+      SPIRV_OC_OpFUnordGreaterThan, SPIRV_OC_OpFOrdLessThanEqual,
+      SPIRV_OC_OpFUnordLessThanEqual, SPIRV_OC_OpFOrdGreaterThanEqual,
+      SPIRV_OC_OpFUnordGreaterThanEqual, SPIRV_OC_OpShiftRightLogical,
+      SPIRV_OC_OpShiftRightArithmetic, SPIRV_OC_OpShiftLeftLogical,
+      SPIRV_OC_OpBitwiseOr, SPIRV_OC_OpBitwiseXor, SPIRV_OC_OpBitwiseAnd,
+      SPIRV_OC_OpNot, SPIRV_OC_OpBitFieldInsert, SPIRV_OC_OpBitFieldSExtract,
+      SPIRV_OC_OpBitFieldUExtract, SPIRV_OC_OpBitReverse, SPIRV_OC_OpBitCount,
+      SPIRV_OC_OpControlBarrier, SPIRV_OC_OpMemoryBarrier, SPIRV_OC_OpAtomicExchange,
+      SPIRV_OC_OpAtomicCompareExchange, SPIRV_OC_OpAtomicCompareExchangeWeak,
+      SPIRV_OC_OpAtomicIIncrement, SPIRV_OC_OpAtomicIDecrement,
+      SPIRV_OC_OpAtomicIAdd, SPIRV_OC_OpAtomicISub, SPIRV_OC_OpAtomicSMin,
+      SPIRV_OC_OpAtomicUMin, SPIRV_OC_OpAtomicSMax, SPIRV_OC_OpAtomicUMax,
+      SPIRV_OC_OpAtomicAnd, SPIRV_OC_OpAtomicOr, SPIRV_OC_OpAtomicXor,
+      SPIRV_OC_OpPhi, SPIRV_OC_OpLoopMerge, SPIRV_OC_OpSelectionMerge,
+      SPIRV_OC_OpLabel, SPIRV_OC_OpBranch, SPIRV_OC_OpBranchConditional,
+      SPIRV_OC_OpReturn, SPIRV_OC_OpReturnValue, SPIRV_OC_OpUnreachable,
+      SPIRV_OC_OpGroupBroadcast, SPIRV_OC_OpGroupIAdd, SPIRV_OC_OpGroupFAdd,
+      SPIRV_OC_OpGroupFMin, SPIRV_OC_OpGroupUMin, SPIRV_OC_OpGroupSMin,
+      SPIRV_OC_OpGroupFMax, SPIRV_OC_OpGroupUMax, SPIRV_OC_OpGroupSMax,
       SPIRV_OC_OpNoLine, SPIRV_OC_OpModuleProcessed, SPIRV_OC_OpGroupNonUniformElect,
       SPIRV_OC_OpGroupNonUniformBroadcast, SPIRV_OC_OpGroupNonUniformBallot,
       SPIRV_OC_OpGroupNonUniformShuffle, SPIRV_OC_OpGroupNonUniformShuffleXor,
       SPIRV_OC_OpGroupNonUniformShuffleUp, SPIRV_OC_OpGroupNonUniformShuffleDown,
       SPIRV_OC_OpGroupNonUniformIAdd, SPIRV_OC_OpGroupNonUniformFAdd,
       SPIRV_OC_OpGroupNonUniformIMul, SPIRV_OC_OpGroupNonUniformFMul,
       SPIRV_OC_OpGroupNonUniformSMin, SPIRV_OC_OpGroupNonUniformUMin,
       SPIRV_OC_OpGroupNonUniformFMin, SPIRV_OC_OpGroupNonUniformSMax,
       SPIRV_OC_OpGroupNonUniformUMax, SPIRV_OC_OpGroupNonUniformFMax,
       SPIRV_OC_OpSubgroupBallotKHR, SPIRV_OC_OpTypeCooperativeMatrixNV,
       SPIRV_OC_OpCooperativeMatrixLoadNV, SPIRV_OC_OpCooperativeMatrixStoreNV,
       SPIRV_OC_OpCooperativeMatrixMulAddNV, SPIRV_OC_OpCooperativeMatrixLengthNV,
       SPIRV_OC_OpSubgroupBlockReadINTEL, SPIRV_OC_OpSubgroupBlockWriteINTEL,
-      SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT,
+      SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT, SPIRV_OC_OpGroupIMulKHR,
+      SPIRV_OC_OpGroupFMulKHR,
 
       SPIRV_OC_OpTypeJointMatrixINTEL, SPIRV_OC_OpJointMatrixLoadINTEL,
       SPIRV_OC_OpJointMatrixStoreINTEL, SPIRV_OC_OpJointMatrixMadINTEL,
       SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_GROUP_OPS
 #define MLIR_DIALECT_SPIRV_IR_GROUP_OPS
 
 // -----
 
+def SPIRV_GroupFMulKHROp : SPIRV_KhrVendorOp<"GroupFMul", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = "TBD";
+
+  let description = [{
+
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.KHR.GroupFMul` scope operation ssa-use
+                            `:` float-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.KHR.GroupFMul <Workgroup> <Reduce> %value : f32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_GroupUniformArithmeticKHR]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
 def SPIRV_GroupBroadcastOp : SPIRV_Op<"GroupBroadcast",
                               [Pure,
                                AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Broadcast the Value of the invocation identified by the local id LocalId
     to the result of all invocations in the group.
   }];
 
def SPIRV_GroupBroadcastOp : SPIRV_Op<"GroupBroadcast",
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($localid)
   }];
 }
 
 // -----
 
-def SPIRV_KHRSubgroupBallotOp : SPIRV_KhrVendorOp<"SubgroupBallot", []> {
-  let summary = "See extension SPV_KHR_shader_ballot";
+def SPIRV_GroupFAddOp : SPIRV_Op<"GroupFAdd", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    A floating-point add group operation specified for all values of X
+    specified by invocations in the group.
+  }];
 
   let description = [{
-    Computes a bitfield value combining the Predicate value from all invocations
-    in the current Subgroup that execute the same dynamic instance of this
-    instruction. The bit is set to one if the corresponding invocation is active
-    and the predicate is evaluated to true; otherwise, it is set to zero.
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
 
-    Predicate must be a Boolean type.
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
 
-    Result Type must be a 4 component vector of 32 bit integer types.
+    Result Type  must be a scalar or vector of floating-point type.
 
-    Result is a set of bitfields where the first invocation is represented in bit
-    0 of the first vector component and the last (up to SubgroupSize) is the
-    higher bit number of the last bitmask needed to represent all bits of the
-    subgroup invocations.
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is 0.
+
+     The type of X must be the same as Result Type.
 
     <!-- End of AutoGen section -->
 
     ```
-    subgroup-ballot-op ::= ssa-id `=` `spirv.KHR.SubgroupBallot`
-                                ssa-use `:` `vector` `<` 4 `x` `i32` `>`
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupFAdd` scope operation ssa-use
+                            `:` float-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupFAdd <Workgroup> <Reduce> %value : f32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupFMaxOp : SPIRV_Op<"GroupFMax", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    A floating-point maximum group operation specified for all values of X
+    specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of floating-point type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is -INF.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupFMax` scope operation ssa-use
+                            `:` float-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupFMax <Workgroup> <Reduce> %value : f32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupFMinOp : SPIRV_Op<"GroupFMin", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    A floating-point minimum group operation specified for all values of X
+    specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of floating-point type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is +INF.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
     ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupFMin` scope operation ssa-use
+                            `:` float-type
+    ```mlir
 
     #### Example:
 
+    ```
+    %0 = spirv.GroupFMin <Workgroup> <Reduce> %value : f32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupIAddOp : SPIRV_Op<"GroupIAdd", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    An integer add group operation specified for all values of X specified
+    by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of integer type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is 0.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupIAdd` scope operation ssa-use
+                            `:` integer-type
     ```mlir
-    %0 = spirv.KHR.SubgroupBallot %predicate : vector<4xi32>
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupIAdd <Workgroup> <Reduce> %value : i32
     ```
   }];
 
   let availability = [
     MinVersion<SPIRV_V_1_0>,
     MaxVersion<SPIRV_V_1_6>,
-    Extension<[SPV_KHR_shader_ballot]>,
-    Capability<[SPIRV_C_SubgroupBallotKHR]>
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
   ];
 
   let arguments = (ins
-    SPIRV_Bool:$predicate
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
   );
 
   let results = (outs
-    SPIRV_Int32Vec4:$result
+    SPIRV_Scalar:$result
   );
 
-  let hasVerifier = 0;
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
 
-  let assemblyFormat = "$predicate attr-dict `:` type($result)";
+// -----
+
+def SPIRV_GroupIMulKHROp : SPIRV_KhrVendorOp<"GroupIMul", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = "TBD";
+
+  let description = [{
+
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.KHR.GroupIMul` scope operation ssa-use
+                            `:` integer-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.KHR.GroupIMul <Workgroup> <Reduce> %value : i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_GroupUniformArithmeticKHR]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupSMaxOp : SPIRV_Op<"GroupSMax", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    A signed integer maximum group operation specified for all values of X
+    specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of integer type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is INT_MIN when X is 32 bits wide and
+    LONG_MIN when X is 64 bits wide.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupSMax` scope operation ssa-use
+                            `:` integer-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupSMax <Workgroup> <Reduce> %value : i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupSMinOp : SPIRV_Op<"GroupSMin", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    A signed integer minimum group operation specified for all values of X
+    specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of integer type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is INT_MAX when X is 32 bits wide and
+    LONG_MAX when X is 64 bits wide.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupSMin` scope operation ssa-use
+                            `:` integer-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupSMin <Workgroup> <Reduce> %value : i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupUMaxOp : SPIRV_Op<"GroupUMax", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    An unsigned integer maximum group operation specified for all values of
+    X specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of integer type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is 0.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupUMax` scope operation ssa-use
+                            `:` integer-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupUMax <Workgroup> <Reduce> %value : i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
+}
+
+// -----
+
+def SPIRV_GroupUMinOp : SPIRV_Op<"GroupUMin", [Pure,
+                               AllTypesMatch<["x", "result"]>]> {
+  let summary = [{
+    An unsigned integer minimum group operation specified for all values of
+    X specified by invocations in the group.
+  }];
+
+  let description = [{
+    Behavior is undefined if not all invocations of this module within
+    Execution reach this point of execution.
+
+    Behavior is undefined unless all invocations within Execution execute
+    the same dynamic instance of this instruction.
+
+    Result Type  must be a scalar or vector of integer type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+    The identity I for Operation is UINT_MAX when X is 32 bits wide and
+    ULONG_MAX when X is 64 bits wide.
+
+     The type of X must be the same as Result Type.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    scope ::= `"Workgroup"` | `"Subgroup"`
+    operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"`
+    op ::= ssa-id `=` `spirv.GroupUMin` scope operation ssa-use
+                            `:` integer-type
+    ```mlir
+
+    #### Example:
+
+    ```
+    %0 = spirv.GroupUMin <Workgroup> <Reduce> %value : i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPIRV_C_Groups]>
+  ];
+
+  let arguments = (ins
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_Scalar:$x
+  );
+
+  let results = (outs
+    SPIRV_Scalar:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope $group_operation operands attr-dict `:` type($x)
+  }];
 }
 
 // -----
 
 def SPIRV_INTELSubgroupBlockReadOp : SPIRV_IntelVendorOp<"SubgroupBlockRead", []> {
   let summary = "See extension SPV_INTEL_subgroups";
 
   let description = [{
let arguments = (ins
     SPIRV_Type:$value
   );
 
   let results = (outs);
 }
 
 // -----
 
+def SPIRV_KHRSubgroupBallotOp : SPIRV_KhrVendorOp<"SubgroupBallot", []> {
+  let summary = "See extension SPV_KHR_shader_ballot";
+
+  let description = [{
+    Computes a bitfield value combining the Predicate value from all invocations
+    in the current Subgroup that execute the same dynamic instance of this
+    instruction. The bit is set to one if the corresponding invocation is active
+    and the predicate is evaluated to true; otherwise, it is set to zero.
+
+    Predicate must be a Boolean type.
+
+    Result Type must be a 4 component vector of 32 bit integer types.
+
+    Result is a set of bitfields where the first invocation is represented in bit
+    0 of the first vector component and the last (up to SubgroupSize) is the
+    higher bit number of the last bitmask needed to represent all bits of the
+    subgroup invocations.
+
+    <!-- End of AutoGen section -->
+
+    ```
+    subgroup-ballot-op ::= ssa-id `=` `spirv.KHR.SubgroupBallot`
+                                ssa-use `:` `vector` `<` 4 `x` `i32` `>`
+    ```
+
+    #### Example:
+
+    ```mlir
+    %0 = spirv.KHR.SubgroupBallot %predicate : vector<4xi32>
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPV_KHR_shader_ballot]>,
+    Capability<[SPIRV_C_SubgroupBallotKHR]>
+  ];
+
+  let arguments = (ins
+    SPIRV_Bool:$predicate
+  );
+
+  let results = (outs
+    SPIRV_Int32Vec4:$result
+  );
+
+  let hasVerifier = 0;
+
+  let assemblyFormat = "$predicate attr-dict `:` type($result)";
+}
+
+// -----
+
 #endif // MLIR_DIALECT_SPIRV_IR_GROUP_OPS

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

LogicalResult spirv::VectorTimesScalarOp::verify() {
   if (getVector().getType() != getType())
     return emitOpError("vector operand and result type mismatch");
   auto scalarType = getType().cast<VectorType>().getElementType();
   if (getScalar().getType() != scalarType)
     return emitOpError("scalar operand and result element type match");
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// Group ops
+//===----------------------------------------------------------------------===//
+
+template <typename Op>
+static LogicalResult verifyGroupOp(Op op) {
+  spirv::Scope scope = op.getExecutionScope();
+  if (scope != spirv::Scope::Workgroup && scope != spirv::Scope::Subgroup)
+    return op.emitOpError("execution scope must be 'Workgroup' or 'Subgroup'");
+
+  return success();
+}
+
+LogicalResult spirv::GroupIAddOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupFAddOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupFMinOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupUMinOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupSMinOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupFMaxOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupUMaxOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupSMaxOp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupIMulKHROp::verify() { return verifyGroupOp(*this); }
+
+LogicalResult spirv::GroupFMulKHROp::verify() { return verifyGroupOp(*this); }
+
 // TableGen'erated operation interfaces for querying versions, extensions, and
 // capabilities.
 #include "mlir/Dialect/SPIRV/IR/SPIRVAvailability.cpp.inc"
 
 // TablenGen'erated operation definitions.
 #define GET_OP_CLASSES
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.cpp.inc"
 
 namespace mlir {
 namespace spirv {
 // TableGen'erated operation availability interface implementations.
 #include "mlir/Dialect/SPIRV/IR/SPIRVOpAvailabilityImpl.inc"
 } // namespace spirv
 } // namespace mlir

mlir/test/Dialect/SPIRV/IR/group-ops.mlir

 
 // -----
 
 func.func @subgroup_block_write_intel_vector(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: vector<3xi32>) -> () {
   // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : vector<3xi32>
   spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : vector<3xi32>
   return
 }
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// Group ops
+//===----------------------------------------------------------------------===//
+
+func.func @group_iadd(%value: i32) -> i32 {
+  // CHECK: spirv.GroupIAdd <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.GroupIAdd <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_fadd(%value: f32) -> f32 {
+  // CHECK: spirv.GroupFAdd <Workgroup> <Reduce> %{{.*}} : f32
+  %0 = spirv.GroupFAdd <Workgroup> <Reduce> %value : f32
+  return %0: f32
+}
+
+// -----
+
+func.func @group_fmin(%value: f32) -> f32 {
+  // CHECK: spirv.GroupFMin <Workgroup> <Reduce> %{{.*}} : f32
+  %0 = spirv.GroupFMin <Workgroup> <Reduce> %value : f32
+  return %0: f32
+}
+
+// -----
+
+func.func @group_umin(%value: i32) -> i32 {
+  // CHECK: spirv.GroupUMin <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.GroupUMin <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_smin(%value: i32) -> i32 {
+  // CHECK: spirv.GroupSMin <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.GroupSMin <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_fmax(%value: f32) -> f32 {
+  // CHECK: spirv.GroupFMax <Workgroup> <Reduce> %{{.*}} : f32
+  %0 = spirv.GroupFMax <Workgroup> <Reduce> %value : f32
+  return %0: f32
+}
+
+// -----
+
+func.func @group_umax(%value: i32) -> i32 {
+  // CHECK: spirv.GroupUMax <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.GroupUMax <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_smax(%value: i32) -> i32 {
+  // CHECK: spirv.GroupSMax <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.GroupSMax <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_imul(%value: i32) -> i32 {
+  // CHECK: spirv.KHR.GroupIMul <Workgroup> <Reduce> %{{.*}} : i32
+  %0 = spirv.KHR.GroupIMul <Workgroup> <Reduce> %value : i32
+  return %0: i32
+}
+
+// -----
+
+func.func @group_fmul(%value: f32) -> f32 {
+  // CHECK: spirv.KHR.GroupFMul <Workgroup> <Reduce> %{{.*}} : f32
+  %0 = spirv.KHR.GroupFMul <Workgroup> <Reduce> %value : f32
+  return %0: f32
+}

mlir/test/Target/SPIRV/group-ops.mlir

spirv.func @subgroup_block_write_intel(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: i32) -> () "None" {
     spirv.Return
   }
   // CHECK-LABEL: @subgroup_block_write_intel_vector
   spirv.func @subgroup_block_write_intel_vector(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: vector<3xi32>) -> () "None" {
     // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : vector<3xi32>
     spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : vector<3xi32>
     spirv.Return
   }
+  // CHECK-LABEL: @group_iadd
+  spirv.func @group_iadd(%value: i32) -> i32 "None" {
+    // CHECK: spirv.GroupIAdd <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.GroupIAdd <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_fadd
+  spirv.func @group_fadd(%value: f32) -> f32 "None" {
+    // CHECK: spirv.GroupFAdd <Workgroup> <Reduce> %{{.*}} : f32
+    %0 = spirv.GroupFAdd <Workgroup> <Reduce> %value : f32
+    spirv.ReturnValue %0: f32
+  }
+  // CHECK-LABEL: @group_fmin
+  spirv.func @group_fmin(%value: f32) -> f32 "None" {
+    // CHECK: spirv.GroupFMin <Workgroup> <Reduce> %{{.*}} : f32
+    %0 = spirv.GroupFMin <Workgroup> <Reduce> %value : f32
+    spirv.ReturnValue %0: f32
+  }
+  // CHECK-LABEL: @group_umin
+  spirv.func @group_umin(%value: i32) -> i32 "None" {
+    // CHECK: spirv.GroupUMin <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.GroupUMin <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_smin
+  spirv.func @group_smin(%value: i32) -> i32 "None" {
+    // CHECK: spirv.GroupSMin <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.GroupSMin <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_fmax
+  spirv.func @group_fmax(%value: f32) -> f32 "None" {
+    // CHECK: spirv.GroupFMax <Workgroup> <Reduce> %{{.*}} : f32
+    %0 = spirv.GroupFMax <Workgroup> <Reduce> %value : f32
+    spirv.ReturnValue %0: f32
+  }
+  // CHECK-LABEL: @group_umax
+  spirv.func @group_umax(%value: i32) -> i32 "None" {
+    // CHECK: spirv.GroupUMax <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.GroupUMax <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_smax
+  spirv.func @group_smax(%value: i32) -> i32 "None" {
+    // CHECK: spirv.GroupSMax <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.GroupSMax <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_imul
+  spirv.func @group_imul(%value: i32) -> i32 "None" {
+    // CHECK: spirv.KHR.GroupIMul <Workgroup> <Reduce> %{{.*}} : i32
+    %0 = spirv.KHR.GroupIMul <Workgroup> <Reduce> %value : i32
+    spirv.ReturnValue %0: i32
+  }
+  // CHECK-LABEL: @group_fmul
+  spirv.func @group_fmul(%value: f32) -> f32 "None" {
+    // CHECK: spirv.KHR.GroupFMul <Workgroup> <Reduce> %{{.*}} : f32
+    %0 = spirv.KHR.GroupFMul <Workgroup> <Reduce> %value : f32
+    spirv.ReturnValue %0: f32
+  }
+
 }

mlir/utils/spirv/gen_spirv_dialect.py

def update_td_opcodes(path, instructions, filter_list):
 
   with open(path, 'r') as f:
     content = f.read()
 
   content = content.split(AUTOGEN_OPCODE_SECTION_MARKER)
   assert len(content) == 3
 
   # Extend opcode list with existing list
-  existing_opcodes = [k[11:] for k in re.findall('def SPIRV_OC_\w+', content[1])]
+  prefix = 'def SPIRV_OC_'
+  existing_opcodes = [k[len(prefix):] for k in re.findall(prefix + '\w+', content[1])]
   filter_list.extend(existing_opcodes)
   filter_list = list(set(filter_list))
 
   # Generate the opcode for all instructions in SPIR-V
   filter_instrs = list(
       filter(lambda inst: (inst['opname'] in filter_list), instructions))
   # Sort instruction based on opcode
   filter_instrs.sort(key=lambda inst: inst['opcode'])