[AMDGPU][MC] Refactor MC Code Emitter to avoid using magic values

[dp]

Summary

Fix this bug.

[Joe_Nash]

I believe the latest guidance is to use std::Optional instead of llvm::Optional (https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716). Also it makes a difference in tests, so is not NFC. Otherwise looks good.

[dp]

Corrected as suggested by Joe.
Joe, thanks for your valuable comments!

[Joe_Nash]

Thanks to Jay as well for pointing out std::optional on another review.
LGTM

[foad]

llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

237

You can return {} if you prefer.

[dp]

llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

237

Thanks, I like it much better than nullopt.

[dp]

Correct as suggested by Jay.

llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Casting.h"
+#include <optional>
 
 using namespace llvm;
 
 namespace {
 
 class SIMCCodeEmitter : public  AMDGPUMCCodeEmitter {
   const MCRegisterInfo &MRI;
 
   /// Encode an fp or int literal
-  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
+  std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
+                                         const MCOperandInfo &OpInfo,
                                          const MCSubtargetInfo &STI) const;
 
 public:
   SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
       : AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {}
   SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
   SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
 
   /// Encode the instruction and write it to the OS.
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
 
   if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
     return 248;
 
   return 255;
 }
 
-uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
-                                         const MCOperandInfo &OpInfo,
-                                         const MCSubtargetInfo &STI) const {
+std::optional<uint32_t>
+SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
   int64_t Imm;
   if (MO.isExpr()) {
     const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
     if (!C)
       return 255;
 
     Imm = C->getValue();
   } else {
 
     assert(!MO.isDFPImm());
 
     if (!MO.isImm())
-      return ~0;
+      return {};
 
     Imm = MO.getImm();
   }
 
   switch (OpInfo.OperandType) {
   case AMDGPU::OPERAND_REG_IMM_INT32:
   case AMDGPU::OPERAND_REG_IMM_FP32:
   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
   for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
 
     // Check if this operand should be encoded as [SV]Src
     if (!AMDGPU::isSISrcOperand(Desc, i))
       continue;
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
+    auto Enc = getLitEncoding(Op, Desc.OpInfo[i], STI);
+    if (!Enc || *Enc != 255)
       continue;
 
     // Yes! Encode it
     int64_t Imm = 0;
 
     if (Op.isImm())
       Imm = Op.getImm();
     else if (Op.isExpr()) {
if (MO.isReg()) {
     RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
       RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
     }
     Op = RegEnc;
     return;
   } else {
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
-    if (Enc != ~0U && Enc != 255) {
-      Op = Enc | SDWA9EncValues::SRC_SGPR_MASK;
+    auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
+    if (Enc && *Enc != 255) {
+      Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
       return;
     }
   }
 
   llvm_unreachable("Unsupported operand kind");
 }
 
 void SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
     uint32_t Offset = Desc.getSize();
     assert(Offset == 4 || Offset == 8);
 
     Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
   }
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
-    if (Enc != ~0U) {
-      Op = Enc;
+    if (auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI)) {
+      Op = *Enc;
       return;
     }
   } else if (MO.isImm()) {
     Op = MO.getImm();
     return;
   }
 
   llvm_unreachable("Encoding of this operand type is not supported yet.");
 }
 
 #include "AMDGPUGenMCCodeEmitter.inc"

llvm/test/MC/AMDGPU/gfx10_asm_vop2.s

 // GFX10: encoding: [0xf7,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
 
 v_fmaak_f32 v5, v1, v255, 0x11213141
 // GFX10: encoding: [0x01,0xff,0x0b,0x5a,0x41,0x31,0x21,0x11]
 
 v_fmaak_f32 v5, v1, v2, 0xa1b1c1d1
 // GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xd1,0xc1,0xb1,0xa1]
 
+v_fmaak_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xff,0xff,0xff,0xff]
+
 v_cvt_pkrtz_f16_f32_e32 v5, v1, v2
 // GFX10: encoding: [0x01,0x05,0x0a,0x5e]
 
 v_cvt_pkrtz_f16_f32_e32 v255, v1, v2
 // GFX10: encoding: [0x01,0x05,0xfe,0x5f]
 
 v_cvt_pkrtz_f16_f32_e32 v5, v255, v2
 // GFX10: encoding: [0xff,0x05,0x0a,0x5e]