[AArch64] Add Missing System Registers

[lenary]

Summary

The following system registers have been missing upstream:

• ID_DFR1_EL1
• AMCG1IDR_EL0 (present when FEAT_AMUv1p1 implemented - optional from v8.6-a)
• HAFGRTR_EL2 (present when FEAT_AMUv1 and FEAT_FGT are implemented)

With regards to HAFGRTR_EL2, this is only present when you have both
extensions. As FEAT_FGT is part of a later architecture, we group it
with those registers. In all honesty, this is a good example of the
kinds of place where just enabling all system registers all the time
would be easiest.

[lenary]

Some additional info on the registers:

• HAFGRTR_EL2 is available at https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/HAFGRTR-EL2--Hypervisor-Activity-Monitors-Fine-Grained-Read-Trap-Register?lang=en
• AMCG1IDR_EL0 is available at https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/AMCG1IDR-EL0--Activity-Monitors-Counter-Group-1-Identification-Register?lang=en
• ID_DFR1_EL1 is available at https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/ID-DFR1-EL1--Debug-Feature-Register-1?lang=en

[pratlucas]

LGTM.

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : ROSysReg<"AIDR_EL1",           0b11, 0b001, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"DCZID_EL0",          0b11, 0b011, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"ID_PFR0_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b000>;
 def : ROSysReg<"ID_PFR1_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b001>;
 def : ROSysReg<"ID_PFR2_EL1",        0b11, 0b000, 0b0000, 0b0011, 0b100> {
     let Requires = [{ {AArch64::FeatureSpecRestrict} }];
 }
 def : ROSysReg<"ID_DFR0_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b010>;
+def : ROSysReg<"ID_DFR1_EL1",        0b11, 0b000, 0b0000, 0b0011, 0b101>;
 def : ROSysReg<"ID_AFR0_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b011>;
 def : ROSysReg<"ID_MMFR0_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b100>;
 def : ROSysReg<"ID_MMFR1_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b101>;
 def : ROSysReg<"ID_MMFR2_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b110>;
 def : ROSysReg<"ID_MMFR3_EL1",       0b11, 0b000, 0b0000, 0b0001, 0b111>;
 def : ROSysReg<"ID_ISAR0_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b000>;
 def : ROSysReg<"ID_ISAR1_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b001>;
 def : ROSysReg<"ID_ISAR2_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b010>;

 def : RWSysReg<"TRBMAR_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b100>;
 def : RWSysReg<"TRBTRG_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b110>;
 def : ROSysReg<"TRBIDR_EL1",    0b11, 0b000, 0b1001, 0b1011, 0b111>;
 } // FeatureTRBE
 
 
 // v8.6a Activity Monitors Virtualization Support
 let Requires = [{ {AArch64::FeatureAMVS} }] in {
+//              Name            Op0   Op1    CRn     CRm     Op2
+def : ROSysReg<"AMCG1IDR_EL0",  0b11, 0b011, 0b1101, 0b0010, 0b110>;
 foreach n = 0-15 in {
   foreach x = 0-1 in {
   def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2",
     0b11, 0b100, 0b1101, 0b1000, 0b000>{
       let Encoding{4} = x;
       let Encoding{3-0} = n;
     }
   }
 }
 }
 
 // v8.6a Fine Grained Virtualization Traps
 //                                 Op0   Op1    CRn     CRm     Op2
 let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
 def : RWSysReg<"HFGRTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b100>;
 def : RWSysReg<"HFGWTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b101>;
 def : RWSysReg<"HFGITR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b110>;
 def : RWSysReg<"HDFGRTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b100>;
 def : RWSysReg<"HDFGWTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b101>;
+def : RWSysReg<"HAFGRTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b110>;
 
 // v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2)
 //                                 Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"HDFGRTR2_EL2",     0b11, 0b100, 0b0011, 0b0001, 0b000>;
 def : RWSysReg<"HDFGWTR2_EL2",     0b11, 0b100, 0b0011, 0b0001, 0b001>;
 def : RWSysReg<"HFGRTR2_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b010>;
 def : RWSysReg<"HFGWTR2_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b011>;
 }

llvm/test/MC/AArch64/arm64-system-encoding.s

 ; CHECK: msr  RMR_EL2, x0             ; encoding: [0x40,0xc0,0x1c,0xd5]
 ; CHECK: msr  RMR_EL1, x0             ; encoding: [0x40,0xc0,0x18,0xd5]
 ; CHECK: msr  OSLAR_EL1, x3           ; encoding: [0x83,0x10,0x10,0xd5]
 ; CHECK: msr  DBGDTRTX_EL0, x3        ; encoding: [0x03,0x05,0x13,0xd5]
         
  mrs x0, ID_PFR0_EL1
  mrs x0, ID_PFR1_EL1
  mrs x0, ID_DFR0_EL1
+ mrs x0, ID_DFR1_EL1
  mrs x0, ID_AFR0_EL1
  mrs x0, ID_ISAR0_EL1
  mrs x0, ID_ISAR1_EL1
  mrs x0, ID_ISAR2_EL1
  mrs x0, ID_ISAR3_EL1
  mrs x0, ID_ISAR4_EL1
  mrs x0, ID_ISAR5_EL1
  mrs x0, AFSR1_EL1
  mrs x0, AFSR0_EL1
  mrs x0, REVIDR_EL1
 ; CHECK: mrs  x0, ID_PFR0_EL1         ; encoding: [0x00,0x01,0x38,0xd5]
 ; CHECK: mrs  x0, ID_PFR1_EL1         ; encoding: [0x20,0x01,0x38,0xd5]
 ; CHECK: mrs  x0, ID_DFR0_EL1         ; encoding: [0x40,0x01,0x38,0xd5]
+; CHECK: mrs  x0, ID_DFR1_EL1         ; encoding: [0xa0,0x03,0x38,0xd5]
 ; CHECK: mrs  x0, ID_AFR0_EL1         ; encoding: [0x60,0x01,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR0_EL1        ; encoding: [0x00,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR1_EL1        ; encoding: [0x20,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR2_EL1        ; encoding: [0x40,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR3_EL1        ; encoding: [0x60,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR4_EL1        ; encoding: [0x80,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, ID_ISAR5_EL1        ; encoding: [0xa0,0x02,0x38,0xd5]
 ; CHECK: mrs  x0, AFSR1_EL1           ; encoding: [0x20,0x51,0x38,0xd5]
 ; CHECK: mrs  x0, AFSR0_EL1           ; encoding: [0x00,0x51,0x38,0xd5]
 ; CHECK: mrs  x0, REVIDR_EL1          ; encoding: [0xc0,0x00,0x38,0xd5]

llvm/test/MC/AArch64/armv8.6a-amvs.s

 // RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+amvs -o - %s  | FileCheck %s
 // RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a -o - %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %p/armv8.6a-amvs.s 2>&1  | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %s 2>&1  | FileCheck %s --check-prefix=CHECK-ERROR
+mrs x0, AMCG1IDR_EL0
 msr AMEVCNTVOFF00_EL2, x0
 msr AMEVCNTVOFF01_EL2, x0
 msr AMEVCNTVOFF02_EL2, x0
 msr AMEVCNTVOFF03_EL2, x0
 msr AMEVCNTVOFF04_EL2, x0
 msr AMEVCNTVOFF05_EL2, x0
 msr AMEVCNTVOFF06_EL2, x0
 msr AMEVCNTVOFF07_EL2, x0

 mrs x0, AMEVCNTVOFF110_EL2
 mrs x0, AMEVCNTVOFF111_EL2
 mrs x0, AMEVCNTVOFF112_EL2
 mrs x0, AMEVCNTVOFF113_EL2
 mrs x0, AMEVCNTVOFF114_EL2
 mrs x0, AMEVCNTVOFF115_EL2
 
 // CHECK:  .text
+// CHECK-NEXT:  mrs     x0, AMCG1IDR_EL0        // encoding: [0xc0,0xd2,0x3b,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF00_EL2, x0   // encoding: [0x00,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF01_EL2, x0   // encoding: [0x20,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF02_EL2, x0   // encoding: [0x40,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF03_EL2, x0   // encoding: [0x60,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF04_EL2, x0   // encoding: [0x80,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF05_EL2, x0   // encoding: [0xa0,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF06_EL2, x0   // encoding: [0xc0,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF07_EL2, x0   // encoding: [0xe0,0xd8,0x1c,0xd5]

llvm/test/MC/AArch64/armv8.6a-fgt.s

 // RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+fgt   < %s | FileCheck %s
 // RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
 // RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOFGT
 
 msr HFGRTR_EL2, x0
 msr HFGWTR_EL2, x5
 msr HFGITR_EL2, x10
 msr HDFGRTR_EL2, x15
 msr HDFGWTR_EL2, x20
+msr HAFGRTR_EL2, x25
 // CHECK: msr     HFGRTR_EL2, x0          // encoding: [0x80,0x11,0x1c,0xd5]
 // CHECK: msr     HFGWTR_EL2, x5          // encoding: [0xa5,0x11,0x1c,0xd5]
 // CHECK: msr     HFGITR_EL2, x10         // encoding: [0xca,0x11,0x1c,0xd5]
 // CHECK: msr     HDFGRTR_EL2, x15        // encoding: [0x8f,0x31,0x1c,0xd5]
 // CHECK: msr     HDFGWTR_EL2, x20        // encoding: [0xb4,0x31,0x1c,0xd5]
+// CHECK: msr     HAFGRTR_EL2, x25        // encoding: [0xd9,0x31,0x1c,0xd5]
+// NOFGT: error: expected writable system register or pstate
 // NOFGT: error: expected writable system register or pstate
 // NOFGT: error: expected writable system register or pstate
 // NOFGT: error: expected writable system register or pstate
 // NOFGT: error: expected writable system register or pstate
 // NOFGT: error: expected writable system register or pstate
 
 mrs x30,  HFGRTR_EL2
 mrs x25,  HFGWTR_EL2
 mrs x20,  HFGITR_EL2
 mrs x15,  HDFGRTR_EL2
 mrs x10,  HDFGWTR_EL2
+mrs x5,   HAFGRTR_EL2
 // CHECK: mrs     x30, HFGRTR_EL2         // encoding: [0x9e,0x11,0x3c,0xd5]
 // CHECK: mrs     x25, HFGWTR_EL2         // encoding: [0xb9,0x11,0x3c,0xd5]
 // CHECK: mrs     x20, HFGITR_EL2         // encoding: [0xd4,0x11,0x3c,0xd5]
 // CHECK: mrs     x15, HDFGRTR_EL2        // encoding: [0x8f,0x31,0x3c,0xd5]
 // CHECK: mrs     x10, HDFGWTR_EL2        // encoding: [0xaa,0x31,0x3c,0xd5]
+// CHECK: mrs     x5, HAFGRTR_EL2         // encoding: [0xc5,0x31,0x3c,0xd5]
+// NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 // NOFGT: error: expected readable system register
 
 
 mrs x3, HDFGRTR2_EL2

llvm/test/MC/AArch64/basic-a64-diagnostics.s

// write-only registers actually are.
         msr CTR_EL0, x12
         msr MPIDR_EL1, x12
         msr REVIDR_EL1, x12
         msr AIDR_EL1, x12
         msr DCZID_EL0, x12
         msr ID_PFR0_EL1, x12
         msr ID_PFR1_EL1, x12
         msr ID_DFR0_EL1, x12
+        msr ID_DFR1_EL1, x12
         msr ID_AFR0_EL1, x12
         msr ID_MMFR0_EL1, x12
         msr ID_MMFR1_EL1, x12
         msr ID_MMFR2_EL1, x12
         msr ID_MMFR3_EL1, x12
         msr ID_MMFR4_EL1, x12
         msr ID_MMFR5_EL1, x12
         msr ID_ISAR0_EL1, x12

 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_PFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_DFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_DFR1_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_MMFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_MMFR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^

llvm/test/MC/AArch64/basic-a64-instructions.s

// CHECK: msr      {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
   mrs x9, MPIDR_EL1
   mrs x9, VMPIDR_EL2
   mrs x9, REVIDR_EL1
   mrs x9, AIDR_EL1
   mrs x9, DCZID_EL0
   mrs x9, ID_PFR0_EL1
   mrs x9, ID_PFR1_EL1
   mrs x9, ID_DFR0_EL1
+  mrs x9, ID_DFR1_EL1
   mrs x9, ID_AFR0_EL1
   mrs x9, ID_MMFR0_EL1
   mrs x9, ID_MMFR1_EL1
   mrs x9, ID_MMFR2_EL1
   mrs x9, ID_MMFR3_EL1
   mrs x9, ID_MMFR4_EL1
   mrs x9, ID_MMFR5_EL1
   mrs x9, ID_ISAR0_EL1

 // CHECK: mrs      x9, {{mpidr_el1|MPIDR_EL1}}              // encoding: [0xa9,0x00,0x38,0xd5]
 // CHECK: mrs      x9, {{vmpidr_el2|VMPIDR_EL2}}             // encoding: [0xa9,0x00,0x3c,0xd5]
 // CHECK: mrs      x9, {{revidr_el1|REVIDR_EL1}}             // encoding: [0xc9,0x00,0x38,0xd5]
 // CHECK: mrs      x9, {{aidr_el1|AIDR_EL1}}               // encoding: [0xe9,0x00,0x39,0xd5]
 // CHECK: mrs      x9, {{dczid_el0|DCZID_EL0}}              // encoding: [0xe9,0x00,0x3b,0xd5]
 // CHECK: mrs      x9, {{id_pfr0_el1|ID_PFR0_EL1}}            // encoding: [0x09,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_pfr1_el1|ID_PFR1_EL1}}            // encoding: [0x29,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_dfr0_el1|ID_DFR0_EL1}}            // encoding: [0x49,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_dfr1_el1|ID_DFR1_EL1}}            // encoding: [0xa9,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{id_afr0_el1|ID_AFR0_EL1}}            // encoding: [0x69,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}           // encoding: [0x89,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}           // encoding: [0xa9,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}           // encoding: [0xc9,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}           // encoding: [0xe9,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}           // encoding: [0xc9,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr5_el1|ID_MMFR5_EL1}}           // encoding: [0xc9,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar0_el1|ID_ISAR0_EL1}}           // encoding: [0x09,0x02,0x38,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s

 // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+amvs %s  | FileCheck %s
 // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+v8.6a -o - %s | FileCheck %s
 // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -o - %s | FileCheck --check-prefix=NOAMVS %s
+[0xc0,0xd2,0x1b,0xd5]
+[0xc0,0xd2,0x3b,0xd5]
 [0x00,0xd8,0x1c,0xd5]
 [0x20,0xd8,0x1c,0xd5]
 [0x40,0xd8,0x1c,0xd5]
 [0x60,0xd8,0x1c,0xd5]
 [0x80,0xd8,0x1c,0xd5]
 [0xa0,0xd8,0x1c,0xd5]
 [0xc0,0xd8,0x1c,0xd5]
 [0xe0,0xd8,0x1c,0xd5]

 [0x20,0xdb,0x3c,0xd5]
 [0x40,0xdb,0x3c,0xd5]
 [0x60,0xdb,0x3c,0xd5]
 [0x80,0xdb,0x3c,0xd5]
 [0xa0,0xdb,0x3c,0xd5]
 [0xc0,0xdb,0x3c,0xd5]
 [0xe0,0xdb,0x3c,0xd5]
 // CHECK:  .text
+// CHECK-NEXT:  msr     S3_3_C13_C2_6, x0       // encoding: [0xc0,0xd2,0x1b,0xd5]
+// CHECK-NEXT:  mrs     x0, AMCG1IDR_EL0        // encoding: [0xc0,0xd2,0x3b,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF00_EL2, x0   // encoding: [0x00,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF01_EL2, x0   // encoding: [0x20,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF02_EL2, x0   // encoding: [0x40,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF03_EL2, x0   // encoding: [0x60,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF04_EL2, x0   // encoding: [0x80,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF05_EL2, x0   // encoding: [0xa0,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF06_EL2, x0   // encoding: [0xc0,0xd8,0x1c,0xd5]
 // CHECK-NEXT:  msr     AMEVCNTVOFF07_EL2, x0   // encoding: [0xe0,0xd8,0x1c,0xd5]

 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF19_EL2   // encoding: [0x20,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF110_EL2  // encoding: [0x40,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF111_EL2  // encoding: [0x60,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF112_EL2  // encoding: [0x80,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF113_EL2  // encoding: [0xa0,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF114_EL2  // encoding: [0xc0,0xdb,0x3c,0xd5]
 // CHECK-NEXT:  mrs     x0, AMEVCNTVOFF115_EL2  // encoding: [0xe0,0xdb,0x3c,0xd5]
 // NOAMVS:  .text
+// NOAMVS-NEXT:  msr     S3_3_C13_C2_6, x0       // encoding: [0xc0,0xd2,0x1b,0xd5]
+// NOAMVS-NEXT:  mrs     x0, S3_3_C13_C2_6       // encoding: [0xc0,0xd2,0x3b,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_0, x0       // encoding: [0x00,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_1, x0       // encoding: [0x20,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_2, x0       // encoding: [0x40,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_3, x0       // encoding: [0x60,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_4, x0       // encoding: [0x80,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_5, x0       // encoding: [0xa0,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_6, x0       // encoding: [0xc0,0xd8,0x1c,0xd5]
 // NOAMVS-NEXT:  msr     S3_4_C13_C8_7, x0       // encoding: [0xe0,0xd8,0x1c,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt

 # RUN: llvm-mc -triple=aarch64  -mattr=+fgt -disassemble < %s      | FileCheck %s
 # RUN: llvm-mc -triple=aarch64              -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
 
 [0x80,0x11,0x1c,0xd5]
 [0xa0,0x11,0x1c,0xd5]
 [0xc0,0x11,0x1c,0xd5]
 [0x80,0x31,0x1c,0xd5]
 [0xa0,0x31,0x1c,0xd5]
+[0xc0,0x31,0x1c,0xd5]
 
 # CHECK: msr HFGRTR_EL2, x0
 # CHECK: msr HFGWTR_EL2, x0
 # CHECK: msr HFGITR_EL2, x0
 # CHECK: msr HDFGRTR_EL2, x0
 # CHECK: msr HDFGWTR_EL2, x0
+# CHECK: msr HAFGRTR_EL2, x0
 # NOFGT: msr S3_4_C1_C1_4, x0
 # NOFGT: msr S3_4_C1_C1_5, x0
 # NOFGT: msr S3_4_C1_C1_6, x0
 # NOFGT: msr S3_4_C3_C1_4, x0
 # NOFGT: msr S3_4_C3_C1_5, x0
+# NOFGT: msr S3_4_C3_C1_6, x0
 
 [0x80,0x11,0x3c,0xd5]
 [0xa0,0x11,0x3c,0xd5]
 [0xc0,0x11,0x3c,0xd5]
 [0x80,0x31,0x3c,0xd5]
 [0xa0,0x31,0x3c,0xd5]
+[0xc0,0x31,0x3c,0xd5]
 
 # CHECK: mrs x0, HFGRTR_EL2
 # CHECK: mrs x0, HFGWTR_EL2
 # CHECK: mrs x0, HFGITR_EL2
 # CHECK: mrs x0, HDFGRTR_EL2
 # CHECK: mrs x0, HDFGWTR_EL2
+# CHECK: mrs x0, HAFGRTR_EL2
 # NOFGT: mrs x0, S3_4_C1_C1_4
 # NOFGT: mrs x0, S3_4_C1_C1_5
 # NOFGT: mrs x0, S3_4_C1_C1_6
 # NOFGT: mrs x0, S3_4_C3_C1_4
 # NOFGT: mrs x0, S3_4_C3_C1_5
+# NOFGT: mrs x0, S3_4_C3_C1_6
 
 [0x03,0x31,0x3c,0xd5]
 [0x23,0x31,0x3c,0xd5]
 [0x43,0x31,0x3c,0xd5]
 [0x63,0x31,0x3c,0xd5]
 # CHECK: mrs x3, HDFGRTR2_EL2
 # CHECK: mrs x3, HDFGWTR2_EL2
 # CHECK: mrs x3, HFGRTR2_EL2

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: mrs      x9, {{mpidr_el1|MPIDR_EL1}}
 # CHECK: mrs      x9, {{vmpidr_el2|VMPIDR_EL2}}
 # CHECK: mrs      x9, {{revidr_el1|REVIDR_EL1}}
 # CHECK: mrs      x9, {{aidr_el1|AIDR_EL1}}
 # CHECK: mrs      x9, {{dczid_el0|DCZID_EL0}}
 # CHECK: mrs      x9, {{id_pfr0_el1|ID_PFR0_EL1}}
 # CHECK: mrs      x9, {{id_pfr1_el1|ID_PFR1_EL1}}
 # CHECK: mrs      x9, {{id_dfr0_el1|ID_DFR0_EL1}}
+# CHECK: mrs      x9, {{id_dfr1_el1|ID_DFR1_EL1}}
 # CHECK: mrs      x9, {{id_afr0_el1|ID_AFR0_EL1}}
 # CHECK: mrs      x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
 # CHECK: mrs      x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
 # CHECK: mrs      x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
 # CHECK: mrs      x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
 # CHECK: mrs      x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
 # CHECK: mrs      x9, {{id_mmfr5_el1|ID_MMFR5_EL1}}
 # CHECK: mrs      x9, {{id_isar0_el1|ID_ISAR0_EL1}}

 0xa9 0x0 0x38 0xd5
 0xa9 0x0 0x3c 0xd5
 0xc9 0x0 0x38 0xd5
 0xe9 0x0 0x39 0xd5
 0xe9 0x0 0x3b 0xd5
 0x9 0x1 0x38 0xd5
 0x29 0x1 0x38 0xd5
 0x49 0x1 0x38 0xd5
+0xa9 0x3 0x38 0xd5
 0x69 0x1 0x38 0xd5
 0x89 0x1 0x38 0xd5
 0xa9 0x1 0x38 0xd5
 0xc9 0x1 0x38 0xd5
 0xe9 0x1 0x38 0xd5
 0xc9 0x2 0x38 0xd5
 0xc9 0x3 0x38 0xd5
 0x9 0x2 0x38 0xd5