[PowerPC] Fix load-conversion pattern recognition in strictfp cases

[qiucf]

Summary

Direct-move instructions are usually more efficient than load then store for conversion. But direct moves are not needed when the source register was just loaded from some address.

The pattern has already been recognized, but the source value of strict nodes are not the first (that's the chain), but the second. This patch fixes it and makes the peephole available to strict conversion operations.

[shchenz]

LGTM. Thanks for fixing.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
   DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
   DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
 }
 
 /// Analyze profitability of direct move
 /// prefer float load to int load plus direct move
 /// when there is no integer use of int load
 bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
-  SDNode *Origin = Op.getOperand(0).getNode();
+  SDNode *Origin = Op.getOperand(Op->isStrictFPOpcode() ? 1 : 0).getNode();
   if (Origin->getOpcode() != ISD::LOAD)
     return true;
 
   // If there is no LXSIBZX/LXSIHZX, like Power8,
   // prefer direct move if the memory size is 1 or 2 bytes.
   MachineMemOperand *MMO = cast<LoadSDNode>(Origin)->getMemOperand();
   if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2)
     return true;

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

entry:
   %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.strict") #0
   store i32 %conv, ptr %addr, align 4
   ret void
 }
 
 define double @load_i32_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_i32_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwa f0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_i32_to_d:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    fcfid f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i32, ptr %addr, align 4
   %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @load_i64_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_i64_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_i64_to_d:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfd f0, 0(r3)
 ; NOVSX-NEXT:    fcfid f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i64, ptr %addr, align 8
   %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @load_u32_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_u32_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
+; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_u32_to_d:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfiwzx f0, 0, r3
 ; NOVSX-NEXT:    fcfidu f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i32, ptr %addr, align 4
   %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define double @load_u64_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_u64_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_u64_to_d:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfd f0, 0(r3)
 ; NOVSX-NEXT:    fcfidu f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i64, ptr %addr, align 8
   %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %conv
 }
 
 define float @load_i32_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_i32_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwa f0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_i32_to_f:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    fcfids f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i32, ptr %addr, align 4
   %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %conv
 }
 
 define float @load_i64_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_i64_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_i64_to_f:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfd f0, 0(r3)
 ; NOVSX-NEXT:    fcfids f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i64, ptr %addr, align 8
   %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %conv
 }
 
 define float @load_u32_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_u32_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
+; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_u32_to_f:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfiwzx f0, 0, r3
 ; NOVSX-NEXT:    fcfidus f1, f0
 ; NOVSX-NEXT:    blr
 entry:
   %m = load i32, ptr %addr, align 4
   %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %conv
 }
 
 define float @load_u64_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_u64_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: load_u64_to_f:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    lfd f0, 0(r3)
 ; NOVSX-NEXT:    fcfidus f1, f0
 ; NOVSX-NEXT:    blr