[NFC][AArch64]Call encoding functions for left-shift immediate (which is no-op in terms of value but better code style)

[mingmingl]

Summary

Call encoding functions for left-shfit immidate for consistency (and easier tracking if the encoding ever changes in the future).

[dmgreen]

Sounds good. Thanks for the cleanup.

[mingmingl]

thanks! Going to submit (the x86 failure window looks irrelevant from error message, and ninja check-llvm passed).

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
                    CurDAG->getTargetConstant(ImmS, DL, VT)};
   unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
   return true;
 }
 
 static bool isWorthFoldingIntoOrrWithShift(SDValue Dst, SelectionDAG *CurDAG,
                                            SDValue &ShiftedOperand,
-                                           uint64_t &ShiftAmount) {
+                                           uint64_t &EncodedShiftImm) {
   // Avoid folding Dst into ORR-with-shift if Dst has other uses than ORR.
   if (!Dst.hasOneUse())
     return false;
 
   EVT VT = Dst.getValueType();
   assert((VT == MVT::i32 || VT == MVT::i64) &&
          "Caller should guarantee that VT is one of i32 or i64");
   const unsigned SizeInBits = VT.getSizeInBits();
if (isOpcWithIntImmediate(DstOp0.getNode(), ISD::SRL, SrlImm)) {
             (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
         SDNode *UBFMNode = CurDAG->getMachineNode(
             UBFMOpc, DL, VT, DstOp0.getOperand(0),
             CurDAG->getTargetConstant(SrlImm + NumTrailingZeroInShiftedMask, DL,
                                       VT),
             CurDAG->getTargetConstant(
                 SrlImm + NumTrailingZeroInShiftedMask + MaskWidth - 1, DL, VT));
         ShiftedOperand = SDValue(UBFMNode, 0);
-        ShiftAmount = NumTrailingZeroInShiftedMask;
+        EncodedShiftImm = AArch64_AM::getShifterImm(
+            AArch64_AM::LSL, NumTrailingZeroInShiftedMask);
         return true;
       }
     }
     return false;
   }
 
   if (isOpcWithIntImmediate(Dst.getNode(), ISD::SHL, ShlImm)) {
     ShiftedOperand = Dst.getOperand(0);
-    ShiftAmount = ShlImm;
+    EncodedShiftImm = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShlImm);
     return true;
   }
 
   uint64_t SrlImm;
   if (isOpcWithIntImmediate(Dst.getNode(), ISD::SRL, SrlImm)) {
     ShiftedOperand = Dst.getOperand(0);
-    ShiftAmount = AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm);
+    EncodedShiftImm = AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm);
     return true;
   }
   return false;
 }
 
 static bool tryOrrWithShift(SDNode *N, SDValue OrOpd0, SDValue OrOpd1,
                             SDValue Src, SDValue Dst, SelectionDAG *CurDAG,
                             const bool BiggerPattern) {
if (isOpcWithIntImmediate(OrOpd0.getNode(), ISD::AND, SrcAndImm) &&
         isMask_64(SrcAndImm) && OrOpd0.getOperand(0) == Src) {
       // OrOpd0 = AND Src, #Mask
       // So BFM simplifies away one AND node from Src and doesn't simplify away
       // nodes from Dst. If ORR with left-shifted operand also simplifies away
       // one node (from Rd), ORR is better since it has higher throughput and
       // smaller latency than BFM on many AArch64 processors (and for the rest
       // ORR is at least as good as BFM).
       SDValue ShiftedOperand;
-      uint64_t ShiftAmount;
+      uint64_t EncodedShiftImm;
       if (isWorthFoldingIntoOrrWithShift(Dst, CurDAG, ShiftedOperand,
-                                         ShiftAmount)) {
+                                         EncodedShiftImm)) {
         unsigned OrrOpc = (VT == MVT::i32) ? AArch64::ORRWrs : AArch64::ORRXrs;
         SDValue Ops[] = {OrOpd0, ShiftedOperand,
-                         CurDAG->getTargetConstant(ShiftAmount, DL, VT)};
+                         CurDAG->getTargetConstant(EncodedShiftImm, DL, VT)};
         CurDAG->SelectNodeTo(N, OrrOpc, VT, Ops);
         return true;
       }
     }
     return false;
   }
 
   assert((!BiggerPattern) && "BiggerPattern should be handled above");
 
   uint64_t ShlImm;
   if (isOpcWithIntImmediate(OrOpd0.getNode(), ISD::SHL, ShlImm) &&
       OrOpd0.getOperand(0) == Src && OrOpd0.hasOneUse()) {
     unsigned OrrOpc = (VT == MVT::i32) ? AArch64::ORRWrs : AArch64::ORRXrs;
-    SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ShlImm, DL, VT)};
+    SDValue Ops[] = {
+        Dst, Src,
+        CurDAG->getTargetConstant(
+            AArch64_AM::getShifterImm(AArch64_AM::LSL, ShlImm), DL, VT)};
     CurDAG->SelectNodeTo(N, OrrOpc, VT, Ops);
     return true;
   }
 
   return false;
 }
 
 static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,