This is an archive of the discontinued LLVM Phabricator instance.

Differential D137656

[PowerPC] Switch to by-name matching for instructions.
AbandonedPublic

Authored by jyknight on Nov 8 2022, 9:53 AM.

Details

Reviewers
None
Summary

This patch fixes all of the "easy" cases, and is _nearly_ all the way
to being able to disable useDeprecatedPositionallyEncodedOperands.
There are a small number of trickier cases, which I've split off into
the next (smaller) patch, for ease of review.

While this changes a large number of lines of source code, it produces
no significant changes in the code generated by tablegen, save for
MTVRSAVEv, which was previously encoding the wrong operand.

Also DQForm

X-Form instructions.

XXForm

DSS/DCB Form (actually misnamed X-forms...)

XLForm

XFXForm -- one codegen change, MTVRSAVEv was previously encoding the wrong operand.

XFLForm, XSForm, XOForm

AForm MForm MDForm MDSForm

VAForm Z22Form Z23Form

fixup: VAForm/VNForm

VXForm

PPC10 prefix formats

EVXForm

Diff Detail

Unit TestsFailed

TimeTest
40 msx64 debian > Clang.CodeGen/assignment-tracking::assignment-tracking.cpp
50 msx64 debian > Clang.CodeGen/assignment-tracking::flag.cpp
50 msx64 debian > Clang.CodeGen/assignment-tracking::memcpy-fragment.cpp
40 msx64 debian > Clang.CodeGen/assignment-tracking::nested-scope.cpp
60,060 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test

Event Timeline

jyknight created this revision.Nov 8 2022, 9:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 8 2022, 9:53 AM
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai. · View Herald Transcript
jyknight requested review of this revision.Nov 8 2022, 9:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 8 2022, 9:53 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B196739: Diff 474037.Nov 8 2022, 10:56 AM
jyknight abandoned this revision.Nov 8 2022, 11:47 AM

(Accidental duplicate of https://reviews.llvm.org/D137661)

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
1110 lines
936 lines
341 lines
28 lines
1568 lines
6 lines
990 lines
75 lines
402 lines
4 lines

Diff 474037

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lineslet isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(retflag)]>, Requires<[In64BitMode]>; [(retflag)]>, Requires<[In64BitMode]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
"bcctr 12, $bi, 0", IIC_BrB, []>, "bcctr 12, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
"bcctr 4, $bi, 0", IIC_BrB, []>, "bcctr 4, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
} }
let Defs = [LR8] in let Defs = [LR8] in
def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
PPC970_Unit_BRU; PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
let Defs = [CTR8], Uses = [CTR8] in { let Defs = [CTR8], Uses = [CTR8] in {
def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
"bdz $dst">; "bdz $BD">;
def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
"bdnz $dst">; "bdnz $BD">;
} }
let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
"bdzlr", IIC_BrB, []>; "bdzlr", IIC_BrB, []>;
def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
"bdnzlr", IIC_BrB, []>; "bdnzlr", IIC_BrB, []>;
} }
} }
let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
// Convenient aliases for call instructions // Convenient aliases for call instructions
let Uses = [RM] in { let Uses = [RM] in {
def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; // See Pat patterns below. "bl $LI", IIC_BrB, []>; // See Pat patterns below.
def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
"bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>;
} }
let Uses = [RM], isCodeGenOnly = 1 in { let Uses = [RM], isCodeGenOnly = 1 in {
def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins calltarget:$func), (outs), (ins calltarget:$LI),
"bl $func\n\tnop", IIC_BrB, []>; "bl $LI\n\tnop", IIC_BrB, []>;
def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins tlscall:$func), (outs), (ins tlscall:$LI),
"bl $func\n\tnop", IIC_BrB, []>; "bl $LI\n\tnop", IIC_BrB, []>;
def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
(outs), (ins abscalltarget:$func), (outs), (ins abscalltarget:$LI),
"bla $func\n\tnop", IIC_BrB, "bla $LI\n\tnop", IIC_BrB,
[(PPCcall_nop (i64 imm:$func))]>; [(PPCcall_nop (i64 imm:$LI))]>;
let Predicates = [PCRelativeMemops] in { let Predicates = [PCRelativeMemops] in {
// BL8_NOTOC means that the caller does not use the TOC pointer and if // BL8_NOTOC means that the caller does not use the TOC pointer and if
// it does use R2 then it is just a caller saved register. Therefore it is // it does use R2 then it is just a caller saved register. Therefore it is
// safe to emit only the bl and not the nop for this instruction. The // safe to emit only the bl and not the nop for this instruction. The
// linker will not try to restore R2 after the call. // linker will not try to restore R2 after the call.
def BL8_NOTOC : IForm<18, 0, 1, (outs), def BL8_NOTOC : IForm<18, 0, 1, (outs),
(ins calltarget:$func), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs),
(ins tlscall:$func), (ins tlscall:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
} }
} }
let Uses = [CTR8, RM] in { let Uses = [CTR8, RM] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl)]>, "bctrl", IIC_BrB, [(PPCbctrl)]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
"bcctrl 12, $bi, 0", IIC_BrB, []>, "bcctrl 12, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
"bcctrl 4, $bi, 0", IIC_BrB, []>, "bcctrl 4, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
} }
} }
let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
isCodeGenOnly = 1, Uses = [RM] in { isCodeGenOnly = 1, Uses = [RM] in {
// Convenient aliases for call instructions // Convenient aliases for call instructions
def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; // See Pat patterns below. "bl $LI", IIC_BrB, []>; // See Pat patterns below.
def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
"bla $func", IIC_BrB, [(PPCcall_rm (i64 imm:$func))]>; "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>;
def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins calltarget:$func), (outs), (ins calltarget:$LI),
"bl $func\n\tnop", IIC_BrB, []>; "bl $LI\n\tnop", IIC_BrB, []>;
def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24,
(outs), (ins abscalltarget:$func), (outs), (ins abscalltarget:$LI),
"bla $func\n\tnop", IIC_BrB, "bla $LI\n\tnop", IIC_BrB,
[(PPCcall_nop_rm (i64 imm:$func))]>; [(PPCcall_nop_rm (i64 imm:$LI))]>;
let Predicates = [PCRelativeMemops] in { let Predicates = [PCRelativeMemops] in {
// BL8_NOTOC means that the caller does not use the TOC pointer and if // BL8_NOTOC means that the caller does not use the TOC pointer and if
// it does use R2 then it is just a caller saved register. Therefore it is // it does use R2 then it is just a caller saved register. Therefore it is
// safe to emit only the bl and not the nop for this instruction. The // safe to emit only the bl and not the nop for this instruction. The
// linker will not try to restore R2 after the call. // linker will not try to restore R2 after the call.
def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), def BL8_NOTOC_RM : IForm<18, 0, 1, (outs),
(ins calltarget:$func), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
} }
let Uses = [CTR8, RM] in { let Uses = [CTR8, RM] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>, "bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
} }
Show All 20 Lines
} // Interpretation64Bit } // Interpretation64Bit
// FIXME: Duplicating this for the asm parser should be unnecessary, but the // FIXME: Duplicating this for the asm parser should be unnecessary, but the
// previous definition must be marked as CodeGen only to prevent decoding // previous definition must be marked as CodeGen only to prevent decoding
// conflicts. // conflicts.
let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in
let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
// Calls // Calls
def : Pat<(PPCcall (i64 tglobaladdr:$dst)), def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
(BL8 tglobaladdr:$dst)>; (BL8 tglobaladdr:$dst)>;
def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
(BL8_NOP tglobaladdr:$dst)>; (BL8_NOP tglobaladdr:$dst)>;
def : Pat<(PPCcall (i64 texternalsym:$dst)), def : Pat<(PPCcall (i64 texternalsym:$dst)),
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lineslet Defs = [CR0] in {
def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo<
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
[(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>;
} }
// Instructions to support atomic operations // Instructions to support atomic operations
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"ldarx $rD, $ptr", IIC_LdStLDARX, []>; "ldarx $RST, $addr", IIC_LdStLDARX, []>;
// TODO: Add scheduling info. // TODO: Add scheduling info.
let hasNoSchedulingInfo = 1 in let hasNoSchedulingInfo = 1 in
def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
"lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64;
// Instruction to support lock versions of atomics // Instruction to support lock versions of atomics
// (EH=1 - see Power ISA 2.07 Book II 4.4.2) // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm;
// TODO: Add scheduling info. // TODO: Add scheduling info.
let hasNoSchedulingInfo = 1 in let hasNoSchedulingInfo = 1 in
// FIXME: We have to seek a way to remove isRecordForm since // FIXME: We have to seek a way to remove isRecordForm since
// LQARXL is not really altering CR0. // LQARXL is not really altering CR0.
def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
"lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>,
isPPC64, isRecordForm; isPPC64, isRecordForm;
let hasExtraDefRegAllocReq = 1 in let hasExtraDefRegAllocReq = 1 in
def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB),
"ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
} }
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm;
// TODO: Add scheduling info. // TODO: Add scheduling info.
let hasNoSchedulingInfo = 1 in let hasNoSchedulingInfo = 1 in
def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr),
"stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, "stqcx. $RST, $addr", IIC_LdStSTQCX, []>,
isPPC64, isRecordForm; isPPC64, isRecordForm;
} }
def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi),
(ins g8prc:$src), (ins g8prc:$src),
"#SPLIT_QUADWORD", []>; "#SPLIT_QUADWORD", []>;
class AtomicRMW128<string asmstr> class AtomicRMW128<string asmstr>
: PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch),
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesdef : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr,
(SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128
memrr:$ptr, memrr:$ptr,
g8rc:$cmp_lo, g8rc:$cmp_lo,
g8rc:$cmp_hi, g8rc:$cmp_hi,
g8rc:$new_lo, g8rc:$new_lo,
g8rc:$new_hi))>; g8rc:$new_hi))>;
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB),
"stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNdi8 :PPCEmitTimePseudo< (outs), def TCRETURNdi8 :PPCEmitTimePseudo< (outs),
(ins calltarget:$dst, i32imm:$offset), (ins calltarget:$dst, i32imm:$offset),
"#TC_RETURNd8 $dst $offset", "#TC_RETURNd8 $dst $offset",
[]>; []>;
Show All 12 Lines
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$LI),
"b $dst", IIC_BrB, "b $LI", IIC_BrB,
[]>; []>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI),
"ba $dst", IIC_BrB, "ba $LI", IIC_BrB,
[]>; []>;
} }
} // Interpretation64Bit } // Interpretation64Bit
def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
(TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
(TCRETURNdi8 texternalsym:$dst, imm:$imm)>; (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
(TCRETURNri8 CTRRC8:$dst, imm:$imm)>; (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
// 64-bit CR instructions // 64-bit CR instructions
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
// mtocrf's input needs to be prepared by shifting by an amount dependent // mtocrf's input needs to be prepared by shifting by an amount dependent
// on the cr register selected. Thus, post-ra anti-dep breaking must not // on the cr register selected. Thus, post-ra anti-dep breaking must not
// later change that register assignment. // later change that register assignment.
let hasExtraDefRegAllocReq = 1 in { let hasExtraDefRegAllocReq = 1 in {
def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST),
"mtocrf $FXM, $ST", IIC_BrMCRX>, "mtocrf $FXM, $RST", IIC_BrMCRX>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
// is dependent on the cr fields being set. // is dependent on the cr fields being set.
def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST),
"mtcrf $FXM, $rS", IIC_BrMCRX>, "mtcrf $FXM, $RST", IIC_BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraDefRegAllocReq = 1 } // hasExtraDefRegAllocReq = 1
// mfocrf's input needs to be prepared by shifting by an amount dependent // mfocrf's input needs to be prepared by shifting by an amount dependent
// on the cr register selected. Thus, post-ra anti-dep breaking must not // on the cr register selected. Thus, post-ra anti-dep breaking must not
// later change that register assignment. // later change that register assignment.
let hasExtraSrcRegAllocReq = 1 in { let hasExtraSrcRegAllocReq = 1 in {
def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM),
"mfocrf $rT, $FXM", IIC_SprMFCRF>, "mfocrf $RST, $FXM", IIC_SprMFCRF>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
// is dependent on the cr fields being copied. // is dependent on the cr fields being copied.
def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins),
"mfcr $rT", IIC_SprMFCR>, "mfcr $RT", IIC_SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraSrcRegAllocReq = 1 } // hasExtraSrcRegAllocReq = 1
} // hasSideEffects = 0 } // hasSideEffects = 0
// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp // While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
// is not. // is not.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
let Defs = [CTR8] in let Defs = [CTR8] in
def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP64", "#EH_SJLJ_SETJMP64",
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
let hasSideEffects = 1, isBarrier = 1 in { let hasSideEffects = 1, isBarrier = 1 in {
let isTerminator = 1 in let isTerminator = 1 in
def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
"#EH_SJLJ_LONGJMP64", "#EH_SJLJ_LONGJMP64",
[(PPCeh_sjlj_longjmp addr:$buf)]>, [(PPCeh_sjlj_longjmp addr:$buf)]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
"mfspr $RT, $SPR", IIC_SprMFSPR>; "mfspr $RST, $SPR", IIC_SprMFSPR>;
def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST),
"mtspr $SPR, $RT", IIC_SprMTSPR>; "mtspr $SPR, $RST", IIC_SprMTSPR>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 64-bit SPR manipulation instrs. // 64-bit SPR manipulation instrs.
let Uses = [CTR8] in { let Uses = [CTR8] in {
def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins),
"mfctr $rT", IIC_SprMFSPR>, "mfctr $RST", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in {
def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),
"mtctr $rS", IIC_SprMTSPR>, "mtctr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
// MTCTR[8|]loop must be inside a loop-preheader, duplicating // MTCTR[8|]loop must be inside a loop-preheader, duplicating
// the loop-preheader block will break this assumption. // the loop-preheader block will break this assumption.
let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in { let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in {
let Pattern = [(int_set_loop_iterations i64:$rS)] in let Pattern = [(int_set_loop_iterations i64:$RST)] in
def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),
"mtctr $rS", IIC_SprMTSPR>, "mtctr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in
def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride),
"#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>;
let Pattern = [(set i64:$rT, readcyclecounter)] in let Pattern = [(set i64:$RST, readcyclecounter)] in
def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins),
"mfspr $rT, 268", IIC_SprMFTB>, "mfspr $RST, 268", IIC_SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
// Note that encoding mftb using mfspr is now the preferred form, // Note that encoding mftb using mfspr is now the preferred form,
// and has been since at least ISA v2.03. The mftb instruction has // and has been since at least ISA v2.03. The mftb instruction has
// now been phased out. Using mfspr, however, is known not to work on // now been phased out. Using mfspr, however, is known not to work on
// the POWER3. // the POWER3.
let Defs = [X1], Uses = [X1] in let Defs = [X1], Uses = [X1] in
def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
Show All 17 Linesdef PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs
RegConstraint<"$actual_negsize = $negsize">; RegConstraint<"$actual_negsize = $negsize">;
def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp),
(ins i64imm:$stacksize), (ins i64imm:$stacksize),
"#PROBED_STACKALLOC_64", []>; "#PROBED_STACKALLOC_64", []>;
} }
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let Defs = [LR8] in { let Defs = [LR8] in {
def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), def MTLR8 : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST),
"mtlr $rS", IIC_SprMTSPR>, "mtlr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Uses = [LR8] in { let Uses = [LR8] in {
def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins),
"mflr $rT", IIC_SprMFSPR>, "mflr $RST", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
} // Interpretation64Bit } // Interpretation64Bit
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Fixed point instructions. // Fixed point instructions.
// //
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), def LI8 : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D),
"li $rD, $imm", IIC_IntSimple, "li $RST, $D", IIC_IntSimple,
[(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64; [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64;
def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D),
"lis $rD, $imm", IIC_IntSimple, "lis $RST, $D", IIC_IntSimple,
[(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64; [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64;
} }
// Logical ops. // Logical ops.
let isCommutable = 1 in { let isCommutable = 1 in {
defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"nand", "$rA, $rS, $rB", IIC_IntSimple, "nand", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>;
defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm AND8 : XForm_6r<31, 28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"and", "$rA, $rS, $rB", IIC_IntSimple, "and", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (and i64:$rS, i64:$rB))]>; [(set i64:$RA, (and i64:$RST, i64:$RB))]>;
} // isCommutable } // isCommutable
defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm ANDC8: XForm_6r<31, 60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"andc", "$rA, $rS, $rB", IIC_IntSimple, "andc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm OR8 : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"or", "$rA, $rS, $rB", IIC_IntSimple, "or", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (or i64:$rS, i64:$rB))]>; [(set i64:$RA, (or i64:$RST, i64:$RB))]>;
defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"nor", "$rA, $rS, $rB", IIC_IntSimple, "nor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>;
} // isCommutable } // isCommutable
defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"orc", "$rA, $rS, $rB", IIC_IntSimple, "orc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"eqv", "$rA, $rS, $rB", IIC_IntSimple, "eqv", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>;
defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"xor", "$rA, $rS, $rB", IIC_IntSimple, "xor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$rA, (xor i64:$rS, i64:$rB))]>; [(set i64:$RA, (xor i64:$RST, i64:$RB))]>;
} // let isCommutable = 1 } // let isCommutable = 1
// Logical ops with immediate. // Logical ops with immediate.
let Defs = [CR0] in { let Defs = [CR0] in {
def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def ANDI8_rec : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"andi. $dst, $src1, $src2", IIC_IntGeneral, "andi. $RA, $RST, $D", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>,
isRecordForm, SExt32To64, ZExt32To64; isRecordForm, SExt32To64, ZExt32To64;
def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"andis. $dst, $src1, $src2", IIC_IntGeneral, "andis. $RA, $RST, $D", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>,
isRecordForm, ZExt32To64; isRecordForm, ZExt32To64;
} }
def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def ORI8 : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"ori $dst, $src1, $src2", IIC_IntSimple, "ori $RA, $RST, $D", IIC_IntSimple,
[(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>;
def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def ORIS8 : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"oris $dst, $src1, $src2", IIC_IntSimple, "oris $RA, $RST, $D", IIC_IntSimple,
[(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>;
def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def XORI8 : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"xori $dst, $src1, $src2", IIC_IntSimple, "xori $RA, $RST, $D", IIC_IntSimple,
[(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>;
def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), def XORIS8 : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
"xoris $dst, $src1, $src2", IIC_IntSimple, "xoris $RA, $RST, $D", IIC_IntSimple,
[(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>;
let isCommutable = 1 in let isCommutable = 1 in
defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"add", "$rT, $rA, $rB", IIC_IntSimple, "add", "$RT, $RA, $RB", IIC_IntSimple,
[(set i64:$rT, (add i64:$rA, i64:$rB))]>; [(set i64:$RT, (add i64:$RA, i64:$RB))]>;
// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
// initial-exec thread-local storage model. We need to forbid r0 here - // initial-exec thread-local storage model. We need to forbid r0 here -
// while it works for add just fine, the linker can relax this to local-exec // while it works for add just fine, the linker can relax this to local-exec
// addi, which won't work for r0. // addi, which won't work for r0.
def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB),
"add $rT, $rA, $rB", IIC_IntSimple, "add $RT, $RA, $RB", IIC_IntSimple,
[(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>;
let mayLoad = 1 in { let mayLoad = 1 in {
def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
} }
let mayStore = 1 in { let mayStore = 1 in {
def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stbx $rS, $rA, $rB", IIC_LdStStore, []>, "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"sthx $rS, $rA, $rB", IIC_LdStStore, []>, "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stwx $rS, $rA, $rB", IIC_LdStStore, []>, "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stbx $rS, $rA, $rB", IIC_LdStStore, []>, "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"sthx $rS, $rA, $rB", IIC_LdStStore, []>, "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stwx $rS, $rA, $rB", IIC_LdStStore, []>, "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
let isCommutable = 1 in let isCommutable = 1 in
defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"addc", "$rT, $rA, $rB", IIC_IntGeneral, "addc", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i64:$rT, (addc i64:$rA, i64:$rB))]>, [(set i64:$RT, (addc i64:$RA, i64:$RB))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Defs = [CARRY] in let Defs = [CARRY] in
def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
"addic $rD, $rA, $imm", IIC_IntGeneral, "addic $RST, $RA, $D", IIC_IntGeneral,
[(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; [(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>;
def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
"addi $rD, $rA, $imm", IIC_IntSimple, "addi $RST, $RA, $D", IIC_IntSimple,
[(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>;
def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D),
"addis $rD, $rA, $imm", IIC_IntSimple, "addis $RST, $RA, $D", IIC_IntSimple,
[(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>;
def LA8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym), def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
"la $rD, $sym($rA)", IIC_IntGeneral, "la $RST, $D($RA)", IIC_IntGeneral,
[(set i64:$rD, (add i64:$rA, [(set i64:$RST, (add i64:$RA,
(PPClo tglobaladdr:$sym, 0)))]>; (PPClo tglobaladdr:$D, 0)))]>;
let Defs = [CARRY] in { let Defs = [CARRY] in {
def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
"subfic $rD, $rA, $imm", IIC_IntGeneral, "subfic $RST, $RA, $D", IIC_IntGeneral,
[(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; [(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>;
} }
defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"subfc", "$rT, $rA, $rB", IIC_IntGeneral, "subfc", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i64:$rT, (subc i64:$rB, i64:$rA))]>, [(set i64:$RT, (subc i64:$RB, i64:$RA))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"subf", "$rT, $rA, $rB", IIC_IntGeneral, "subf", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i64:$rT, (sub i64:$rB, i64:$rA))]>; [(set i64:$RT, (sub i64:$RB, i64:$RA))]>;
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"neg", "$rT, $rA", IIC_IntSimple, "neg", "$RT, $RA", IIC_IntSimple,
[(set i64:$rT, (ineg i64:$rA))]>; [(set i64:$RT, (ineg i64:$RA))]>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
let isCommutable = 1 in let isCommutable = 1 in
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"adde", "$rT, $rA, $rB", IIC_IntGeneral, "adde", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, i64:$rB))]>; [(set i64:$RT, (adde i64:$RA, i64:$RB))]>;
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"addme", "$rT, $rA", IIC_IntGeneral, "addme", "$RT, $RA", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, -1))]>; [(set i64:$RT, (adde i64:$RA, -1))]>;
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"addze", "$rT, $rA", IIC_IntGeneral, "addze", "$RT, $RA", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, 0))]>; [(set i64:$RT, (adde i64:$RA, 0))]>;
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"subfe", "$rT, $rA, $rB", IIC_IntGeneral, "subfe", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i64:$rT, (sube i64:$rB, i64:$rA))]>; [(set i64:$RT, (sube i64:$RB, i64:$RA))]>;
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"subfme", "$rT, $rA", IIC_IntGeneral, "subfme", "$RT, $RA", IIC_IntGeneral,
[(set i64:$rT, (sube -1, i64:$rA))]>; [(set i64:$RT, (sube -1, i64:$RA))]>;
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),
"subfze", "$rT, $rA", IIC_IntGeneral, "subfze", "$RT, $RA", IIC_IntGeneral,
[(set i64:$rT, (sube 0, i64:$rA))]>; [(set i64:$RT, (sube 0, i64:$RA))]>;
} }
} // isCodeGenOnly } // isCodeGenOnly
// FIXME: Duplicating this for the asm parser should be unnecessary, but the // FIXME: Duplicating this for the asm parser should be unnecessary, but the
// previous definition must be marked as CodeGen only to prevent decoding // previous definition must be marked as CodeGen only to prevent decoding
// conflicts. // conflicts.
let isAsmParserOnly = 1 in { let isAsmParserOnly = 1 in {
def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB),
"add $rT, $rA, $rB", IIC_IntSimple, []>; "add $RT, $RA, $RB", IIC_IntSimple, []>;
let mayLoad = 1 in { let mayLoad = 1 in {
def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
"ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
} }
let mayStore = 1 in { let mayStore = 1 in {
def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stbx $rS, $rA, $rB", IIC_LdStStore, []>, "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"sthx $rS, $rA, $rB", IIC_LdStStore, []>, "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stwx $rS, $rA, $rB", IIC_LdStStore, []>, "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
"stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
} }
let isCommutable = 1 in { let isCommutable = 1 in {
defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"mulhd", "$rT, $rA, $rB", IIC_IntMulHW, "mulhd", "$RT, $RA, $RB", IIC_IntMulHW,
[(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>;
defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU,
[(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>;
} // isCommutable } // isCommutable
} }
} // Interpretation64Bit } // Interpretation64Bit
let isCompare = 1, hasSideEffects = 0 in { let isCompare = 1, hasSideEffects = 0 in {
def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), def CMPD : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),
"cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64;
def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), def CMPLD : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),
"cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64;
def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), def CMPDI : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D),
"cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64;
def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D),
"cmpldi $dst, $src1, $src2", "cmpldi $BF, $RA, $D",
IIC_IntCompare>, isPPC64; IIC_IntCompare>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF),
(ins u1imm:$L, g8rc:$rA, g8rc:$rB), (ins u1imm:$L, g8rc:$RA, g8rc:$RB),
"cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF),
(ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB",
IIC_IntCompare, []>, Requires<[IsISA3_0]>; IIC_IntCompare, []>, Requires<[IsISA3_0]>;
} }
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SLD : XForm_6r<31, 27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
"sld", "$rA, $rS, $rB", IIC_IntRotateD, "sld", "$RA, $RST, $RB", IIC_IntRotateD,
[(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64;
defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SRD : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
"srd", "$rA, $rS, $rB", IIC_IntRotateD, "srd", "$RA, $RST, $RB", IIC_IntRotateD,
[(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64;
defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
"srad", "$rA, $rS, $rB", IIC_IntRotateD, "srad", "$RA, $RST, $RB", IIC_IntRotateD,
[(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$RA), (ins g8rc:$RST),
"cntlzw", "$rA, $rS", IIC_IntGeneral, []>, "cntlzw", "$RA, $RST", IIC_IntGeneral, []>,
ZExt32To64, SExt32To64; ZExt32To64, SExt32To64;
defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST),
"cnttzw", "$rA, $rS", IIC_IntGeneral, []>, "cnttzw", "$RA, $RST", IIC_IntGeneral, []>,
Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST),
"extsb", "$rA, $rS", IIC_IntSimple, "extsb", "$RA, $RST", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64; [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64;
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST),
"extsh", "$rA, $rS", IIC_IntSimple, "extsh", "$RA, $RST", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64; [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64;
defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm SLW8 : XForm_6r<31, 24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm SRW8 : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
} // Interpretation64Bit } // Interpretation64Bit
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST),
"extsb $rA, $rS", IIC_IntSimple, []>, isPPC64, "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64,
SExt32To64; SExt32To64;
def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST),
"extsh $rA, $rS", IIC_IntSimple, []>, isPPC64, "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64,
SExt32To64; SExt32To64;
} // isCodeGenOnly for fast-isel } // isCodeGenOnly for fast-isel
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSW : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST),
"extsw", "$rA, $rS", IIC_IntSimple, "extsw", "$RA, $RST", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64, [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64,
SExt32To64; SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST),
"extsw", "$rA, $rS", IIC_IntSimple, "extsw", "$RA, $RST", IIC_IntSimple,
[(set i64:$rA, (sext i32:$rS))]>, isPPC64, [(set i64:$RA, (sext i32:$RST))]>, isPPC64,
SExt32To64; SExt32To64;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST),
"extsw $rA, $rS", IIC_IntSimple, "extsw $RA, $RST", IIC_IntSimple,
[]>, isPPC64; []>, isPPC64;
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),
"sradi", "$rA, $rS, $SH", IIC_IntRotateDI, "sradi", "$RA, $RS, $SH", IIC_IntRotateDI,
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA),
(ins gprc:$rS, u6imm:$SH), (ins gprc:$RS, u6imm:$SH),
"extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,
[(set i64:$rA, [(set i64:$RA,
(PPCextswsli i32:$rS, (i32 imm:$SH)))]>, (PPCextswsli i32:$RS, (i32 imm:$SH)))]>,
isPPC64, Requires<[IsISA3_0]>; isPPC64, Requires<[IsISA3_0]>;
defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),
"extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,
[]>, isPPC64, Requires<[IsISA3_0]>; []>, isPPC64, Requires<[IsISA3_0]>;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1, Defs = [CARRY] in let isCodeGenOnly = 1, Defs = [CARRY] in
def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH),
"sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64;
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$RA), (ins g8rc:$RST),
"cntlzd", "$rA, $rS", IIC_IntGeneral, "cntlzd", "$RA, $RST", IIC_IntGeneral,
[(set i64:$rA, (ctlz i64:$rS))]>, [(set i64:$RA, (ctlz i64:$RST))]>,
ZExt32To64, SExt32To64; ZExt32To64, SExt32To64;
defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST),
"cnttzd", "$rA, $rS", IIC_IntGeneral, "cnttzd", "$RA, $RST", IIC_IntGeneral,
[(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>, [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>,
ZExt32To64, SExt32To64; ZExt32To64, SExt32To64;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST),
"popcntd $rA, $rS", IIC_IntGeneral, "popcntd $RA, $RST", IIC_IntGeneral,
[(set i64:$rA, (ctpop i64:$rS))]>, [(set i64:$RA, (ctpop i64:$RST))]>,
ZExt32To64, SExt32To64; ZExt32To64, SExt32To64;
def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"bpermd $rA, $rS, $rB", IIC_IntGeneral, "bpermd $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>,
isPPC64, Requires<[HasBPERMD]>; isPPC64, Requires<[HasBPERMD]>;
let isCodeGenOnly = 1, isCommutable = 1 in let isCodeGenOnly = 1, isCommutable = 1 in
def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"cmpb $rA, $rS, $rB", IIC_IntGeneral, "cmpb $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>;
// popcntw also does a population count on the high 32 bits (storing the // popcntw also does a population count on the high 32 bits (storing the
// results in the high 32-bits of the output). We'll ignore that here (which is // results in the high 32-bits of the output). We'll ignore that here (which is
// safe because we never separately use the high part of the 64-bit registers). // safe because we never separately use the high part of the 64-bit registers).
def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST),
"popcntw $rA, $rS", IIC_IntGeneral, "popcntw $RA, $RST", IIC_IntGeneral,
[(set i32:$rA, (ctpop i32:$rS))]>; [(set i32:$RA, (ctpop i32:$RST))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),
"popcntb $rA, $rS", IIC_IntGeneral, "popcntb $RA, $RST", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;
defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"divd", "$rT, $rA, $rB", IIC_IntDivD, "divd", "$RT, $RA, $RB", IIC_IntDivD,
[(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64;
defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"divdu", "$rT, $rA, $rB", IIC_IntDivD, "divdu", "$RT, $RA, $RB", IIC_IntDivD,
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64;
defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"divde", "$rT, $rA, $rB", IIC_IntDivD, "divde", "$RT, $RA, $RB", IIC_IntDivD,
[(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>,
isPPC64, Requires<[HasExtDiv]>; isPPC64, Requires<[HasExtDiv]>;
let Predicates = [IsISA3_0] in { let Predicates = [IsISA3_0] in {
def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
"maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
def MADDHDU : VAForm_1a<49, def MADDHDU : VAForm_1a<49,
(outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
"maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
"maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
[(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>,
isPPC64; isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def MADDLD8 : VAForm_1a<51, def MADDLD8 : VAForm_1a<51,
(outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
"maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
[(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
isPPC64; isPPC64;
def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
"setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64; "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;
} }
def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
"addpcis $RT, $D", IIC_BrB, []>, isPPC64; "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),
"modsd $rT, $rA, $rB", IIC_IntDivW, "modsd $RST, $RA, $RB", IIC_IntDivW,
[(set i64:$rT, (srem i64:$rA, i64:$rB))]>; [(set i64:$RST, (srem i64:$RA, i64:$RB))]>;
def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),
"modud $rT, $rA, $rB", IIC_IntDivW, "modud $RST, $RA, $RB", IIC_IntDivW,
[(set i64:$rT, (urem i64:$rA, i64:$rB))]>; [(set i64:$RST, (urem i64:$RA, i64:$RB))]>;
} }
defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"divdeu", "$rT, $rA, $rB", IIC_IntDivD, "divdeu", "$RT, $RA, $RB", IIC_IntDivD,
[(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>,
isPPC64, Requires<[HasExtDiv]>; isPPC64, Requires<[HasExtDiv]>;
let isCommutable = 1 in let isCommutable = 1 in
defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"mulld", "$rT, $rA, $rB", IIC_IntMulHD, "mulld", "$RT, $RA, $RB", IIC_IntMulHD,
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
"mulli $rD, $rA, $imm", IIC_IntMulLI, "mulli $RST, $RA, $D", IIC_IntMulLI,
[(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>;
} }
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
"darn $RT, $L", IIC_LdStLD>, isPPC64; "darn $RT, $L", IIC_LdStLD>, isPPC64;
} }
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA),
(ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE),
"rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64, RegConstraint<"$rSi = $rA">, []>, isPPC64, RegConstraint<"$RAi = $RA">,
NoEncode<"$rSi">; NoEncode<"$RAi">;
// Rotate instructions. // Rotate instructions.
defm RLDCL : MDSForm_1r<30, 8, defm RLDCL : MDSForm_1r<30, 8,
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),
"rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,
[]>, isPPC64; []>, isPPC64;
defm RLDCR : MDSForm_1r<30, 9, defm RLDCR : MDSForm_1r<30, 9,
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),
"rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,
[]>, isPPC64; []>, isPPC64;
defm RLDICL : MDForm_1r<30, 0, defm RLDICL : MDForm_1r<30, 0,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
"rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def RLDICL_32_64 : MDForm_1<30, 0, def RLDICL_32_64 : MDForm_1<30, 0,
(outs g8rc:$rA), (outs g8rc:$RA),
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
"rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// End fast-isel. // End fast-isel.
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm RLDICL_32 : MDForm_1r<30, 0, defm RLDICL_32 : MDForm_1r<30, 0,
(outs gprc:$rA), (outs gprc:$RA),
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
"rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
defm RLDICR : MDForm_1r<30, 1, defm RLDICR : MDForm_1r<30, 1,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
"rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def RLDICR_32 : MDForm_1<30, 1, def RLDICR_32 : MDForm_1<30, 1,
(outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
"rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
defm RLDIC : MDForm_1r<30, 2, defm RLDIC : MDForm_1r<30, 2,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
"rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA),
(ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,
[]>; []>;
defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA),
(ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME),
"rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral,
[]>; []>;
// RLWIMI can be commuted if the rotate amount is zero. // RLWIMI can be commuted if the rotate amount is zero.
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA),
(ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB,
u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
IIC_IntRotate, []>, PPC970_DGroup_Cracked, IIC_IntRotate, []>, PPC970_DGroup_Cracked,
RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
let isSelect = 1 in let isSelect = 1 in
def ISEL8 : AForm_4<31, 15, def ISEL8 : AForm_4<31, 15,
(outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND),
"isel $rT, $rA, $rB, $cond", IIC_IntISEL, "isel $RT, $RA, $RB, $COND", IIC_IntISEL,
[]>; []>;
} // Interpretation64Bit } // Interpretation64Bit
} // hasSideEffects = 0 } // hasSideEffects = 0
} // End FXU Operations. } // End FXU Operations.
def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load/Store instructions. // Load/Store instructions.
// //
// Sign extending loads. // Sign extending loads.
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), def LHA8: DForm_1<42, (outs g8rc:$RST), (ins memri:$addr),
"lha $rD, $src", IIC_LdStLHA, "lha $RST, $addr", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 DForm:$src))]>, [(set i64:$RST, (sextloadi16 DForm:$addr))]>,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), def LWA : DSForm_1<58, 2, (outs g8rc:$RST), (ins memrix:$addr),
"lwa $rD, $src", IIC_LdStLWA, "lwa $RST, $addr", IIC_LdStLWA,
[(set i64:$rD, [(set i64:$RST,
(sextloadi32 DSForm:$src))]>, isPPC64, (sextloadi32 DSForm:$addr))]>, isPPC64,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lhax $rD, $src", IIC_LdStLHA, "lhax $RST, $addr", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 XForm:$src))]>, [(set i64:$RST, (sextloadi16 XForm:$addr))]>,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lwax $rD, $src", IIC_LdStLHA, "lwax $RST, $addr", IIC_LdStLHA,
[(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), def LWA_32 : DSForm_1<58, 2, (outs gprc:$RST), (ins memrix:$addr),
"lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
} // end fast-isel isCodeGenOnly } // end fast-isel isCodeGenOnly
// Update forms. // Update forms.
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memri:$addr), (ins memri:$addr),
"lhau $rD, $addr", IIC_LdStLHAU, "lhau $RST, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
// NO LWAU! // NO LWAU!
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lhaux $rD, $addr", IIC_LdStLHAUX, "lhaux $RST, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lwaux $rD, $addr", IIC_LdStLHAUX, "lwaux $RST, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64; NoEncode<"$ea_result">, isPPC64;
} }
} }
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
// Zero extending loads. // Zero extending loads.
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins memri:$addr),
"lbz $rD, $src", IIC_LdStLoad, "lbz $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64, [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins memri:$addr),
"lhz $rD, $src", IIC_LdStLoad, "lhz $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64, [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins memri:$addr),
"lwz $rD, $src", IIC_LdStLoad, "lwz $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64, [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64,
ZExt32To64; ZExt32To64;
def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lbzx $rD, $src", IIC_LdStLoad, "lbzx $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64, [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lhzx $rD, $src", IIC_LdStLoad, "lhzx $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi16 XForm:$src))]>, [(set i64:$RST, (zextloadi16 XForm:$addr))]>,
ZExt32To64, SExt32To64; ZExt32To64, SExt32To64;
def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lwzx $rD, $src", IIC_LdStLoad, "lwzx $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (zextloadi32 XForm:$src))]>, [(set i64:$RST, (zextloadi32 XForm:$addr))]>,
ZExt32To64; ZExt32To64;
// Update forms. // Update forms.
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memri:$addr), (ins memri:$addr),
"lbzu $rD, $addr", IIC_LdStLoadUpd, "lbzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memri:$addr), (ins memri:$addr),
"lhzu $rD, $addr", IIC_LdStLoadUpd, "lhzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memri:$addr), (ins memri:$addr),
"lwzu $rD, $addr", IIC_LdStLoadUpd, "lwzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lbzux $rD, $addr", IIC_LdStLoadUpdX, "lbzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lhzux $rD, $addr", IIC_LdStLoadUpdX, "lhzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lwzux $rD, $addr", IIC_LdStLoadUpdX, "lwzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
} }
} }
} // Interpretation64Bit } // Interpretation64Bit
// Full 8-byte loads. // Full 8-byte loads.
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), def LD : DSForm_1<58, 0, (outs g8rc:$RST), (ins memrix:$addr),
"ld $rD, $src", IIC_LdStLD, "ld $RST, $addr", IIC_LdStLD,
[(set i64:$rD, (load DSForm:$src))]>, isPPC64; [(set i64:$RST, (load DSForm:$addr))]>, isPPC64;
// The following four definitions are selected for small code model only. // The following four definitions are selected for small code model only.
// Otherwise, we need to create two instructions to form a 32-bit offset, // Otherwise, we need to create two instructions to form a 32-bit offset,
// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtoc", "#LDtoc",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocJTI", "#LDtocJTI",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocCPT", "#LDtocCPT",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocCPT", "#LDtocCPT",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), def LDX : XForm_1_memOp<31, 21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"ldx $rD, $src", IIC_LdStLD, "ldx $RST, $addr", IIC_LdStLD,
[(set i64:$rD, (load XForm:$src))]>, isPPC64; [(set i64:$RST, (load XForm:$addr))]>, isPPC64;
let Predicates = [IsISA2_06] in { let Predicates = [IsISA2_06] in {
def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"ldbrx $rD, $src", IIC_LdStLoad, "ldbrx $RST, $addr", IIC_LdStLoad,
[(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64;
} }
let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
} }
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrix:$addr), (ins memrix:$addr),
"ldu $rD, $addr", IIC_LdStLDU, "ldu $RST, $addr", IIC_LdStLDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"ldux $rD, $addr", IIC_LdStLDUX, "ldux $RST, $addr", IIC_LdStLDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64; NoEncode<"$ea_result">, isPPC64;
} }
let mayLoad = 1, hasNoSchedulingInfo = 1 in { let mayLoad = 1, hasNoSchedulingInfo = 1 in {
// Full 16-byte load. // Full 16-byte load.
// Early clobber $RTp to avoid assigned to the same register as RA. // Early clobber $RTp to avoid assigned to the same register as RA.
// TODO: Add scheduling info. // TODO: Add scheduling info.
def LQ : DQForm_RTp5_RA17_MEM<56, 0, def LQ : DQForm_RTp5_RA17_MEM<56, 0,
(outs g8prc:$RTp), (outs g8prc:$RTp),
(ins memrix16:$src), (ins memrix16:$addr),
"lq $RTp, $src", IIC_LdStLQ, "lq $RTp, $addr", IIC_LdStLQ,
[]>, []>,
RegConstraint<"@earlyclobber $RTp">, RegConstraint<"@earlyclobber $RTp">,
isPPC64; isPPC64;
// We don't really have LQX in the ISA, make a pseudo one so that we can // We don't really have LQX in the ISA, make a pseudo one so that we can
// handle x-form during isel. Make it pre-ra may expose // handle x-form during isel. Make it pre-ra may expose
// oppotunities to some opts(CSE, LICM and etc.) for the result of adding // oppotunities to some opts(CSE, LICM and etc.) for the result of adding
// RA and RB. // RA and RB.
def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp),
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Linesdef PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#PADDIdtprel", "#PADDIdtprel",
[(set i64:$rD, [(set i64:$rD,
(PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
// Truncating stores. // Truncating stores.
def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, memri:$addr),
"stb $rS, $src", IIC_LdStStore, "stb $RST, $addr", IIC_LdStStore,
[(truncstorei8 i64:$rS, DForm:$src)]>; [(truncstorei8 i64:$RST, DForm:$addr)]>;
def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, memri:$addr),
"sth $rS, $src", IIC_LdStStore, "sth $RST, $addr", IIC_LdStStore,
[(truncstorei16 i64:$rS, DForm:$src)]>; [(truncstorei16 i64:$RST, DForm:$addr)]>;
def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, memri:$addr),
"stw $rS, $src", IIC_LdStStore, "stw $RST, $addr", IIC_LdStStore,
[(truncstorei32 i64:$rS, DForm:$src)]>; [(truncstorei32 i64:$RST, DForm:$addr)]>;
def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stbx $rS, $dst", IIC_LdStStore, "stbx $RST, $addr", IIC_LdStStore,
[(truncstorei8 i64:$rS, XForm:$dst)]>, [(truncstorei8 i64:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"sthx $rS, $dst", IIC_LdStStore, "sthx $RST, $addr", IIC_LdStStore,
[(truncstorei16 i64:$rS, XForm:$dst)]>, [(truncstorei16 i64:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stwx $rS, $dst", IIC_LdStStore, "stwx $RST, $addr", IIC_LdStStore,
[(truncstorei32 i64:$rS, XForm:$dst)]>, [(truncstorei32 i64:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} // Interpretation64Bit } // Interpretation64Bit
// Normal 8-byte stores. // Normal 8-byte stores.
def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), def STD : DSForm_1<62, 0, (outs), (ins g8rc:$RST, memrix:$addr),
"std $rS, $dst", IIC_LdStSTD, "std $RST, $addr", IIC_LdStSTD,
[(store i64:$rS, DSForm:$dst)]>, isPPC64; [(store i64:$RST, DSForm:$addr)]>, isPPC64;
def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stdx $rS, $dst", IIC_LdStSTD, "stdx $RST, $addr", IIC_LdStSTD,
[(store i64:$rS, XForm:$dst)]>, isPPC64, [(store i64:$RST, XForm:$addr)]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Predicates = [IsISA2_06] in { let Predicates = [IsISA2_06] in {
def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stdbrx $rS, $dst", IIC_LdStStore, "stdbrx $RST, $addr", IIC_LdStStore,
[(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
let mayStore = 1, hasNoSchedulingInfo = 1 in { let mayStore = 1, hasNoSchedulingInfo = 1 in {
// Normal 16-byte stores. // Normal 16-byte stores.
// TODO: Add scheduling info. // TODO: Add scheduling info.
def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, memrix:$addr),
"stq $RSp, $dst", IIC_LdStSTQ, "stq $RST, $addr", IIC_LdStSTQ,
[]>, isPPC64; []>, isPPC64;
def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), def STQX_PSEUDO : PPCCustomInserterPseudo<(outs),
(ins g8prc:$RSp, memrr:$dst), (ins g8prc:$RSp, memrr:$dst),
"#STQX_PSEUDO", []>; "#STQX_PSEUDO", []>;
def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst),
"#SPILL_QUADWORD", []>; "#SPILL_QUADWORD", []>;
Show All 10 Linesdef : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst),
(STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>;
def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst),
(STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>;
// Stores with Update (pre-inc). // Stores with Update (pre-inc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
"stbu $rS, $dst", IIC_LdStSTU, []>, "stbu $RST, $addr", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
"sthu $rS, $dst", IIC_LdStSTU, []>, "sthu $RST, $addr", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr),
"stwu $rS, $dst", IIC_LdStSTU, []>, "stwu $RST, $addr", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stbux $rS, $dst", IIC_LdStSTUX, []>, "stbux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"sthux $rS, $dst", IIC_LdStSTUX, []>, "sthux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stwux $rS, $dst", IIC_LdStSTUX, []>, "stwux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} // Interpretation64Bit } // Interpretation64Bit
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrix:$dst), (ins g8rc:$RST, memrix:$addr),
"stdu $rS, $dst", IIC_LdStSTU, []>, "stdu $RST, $addr", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">,
isPPC64; isPPC64;
def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$rS, memrr:$dst), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stdux $rS, $dst", IIC_LdStSTUX, []>, "stdux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked, isPPC64; PPC970_DGroup_Cracked, isPPC64;
} }
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
Show All 17 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating point instructions. // Floating point instructions.
// //
let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,
Uses = [RM] in { // FPU Operations. Uses = [RM] in { // FPU Operations.
defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),
"fcfid", "$frD, $frB", IIC_FPGeneral, "fcfid", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;
defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),
"fctid", "$frD, $frB", IIC_FPGeneral, "fctid", "$RST, $RB", IIC_FPGeneral,
[]>, isPPC64; []>, isPPC64;
defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),
"fctidu", "$frD, $frB", IIC_FPGeneral, "fctidu", "$RST, $RB", IIC_FPGeneral,
[]>, isPPC64; []>, isPPC64;
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),
"fctidz", "$frD, $frB", IIC_FPGeneral, "fctidz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),
"fcfidu", "$frD, $frB", IIC_FPGeneral, "fcfidu", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),
"fcfids", "$frD, $frB", IIC_FPGeneral, "fcfids", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),
"fcfidus", "$frD, $frB", IIC_FPGeneral, "fcfidus", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiduz", "$frD, $frB", IIC_FPGeneral, "fctiduz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiwuz", "$frD, $frB", IIC_FPGeneral, "fctiwuz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
} }
// These instructions store a hash computed from the value of the link register // These instructions store a hash computed from the value of the link register
// and the value of the stack pointer. // and the value of the stack pointer.
let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs),
(ins g8rc:$RB, memrihash:$D_RA_XD), (ins g8rc:$RB, memrihash:$D_RA_XD),
"hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>;
Show All 12 Linesdef HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs),
(ins g8rc:$RB, memrihash:$D_RA_XD), (ins g8rc:$RB, memrihash:$D_RA_XD),
"hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>;
def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs),
(ins g8rc:$RB, memrihash:$D_RA_XD), (ins g8rc:$RB, memrihash:$D_RA_XD),
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
} }
let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),
(ins g8rc:$rA, g8rc:$rB, u2imm:$CY), (ins g8rc:$RA, g8rc:$RB, u2imm:$CY),
"addex $rT, $rA, $rB, $CY", IIC_IntGeneral, "addex $RT, $RA, $RB, $CY", IIC_IntGeneral,
[(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,
timm:$CY))]>; timm:$CY))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Patterns // Instruction Patterns
// //
// Extensions and truncates to/from 32-bit regs. // Extensions and truncates to/from 32-bit regs.
def : Pat<(i64 (zext i32:$in)), def : Pat<(i64 (zext i32:$in)),
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
// DARN (deliver random number) // DARN (deliver random number)
// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;
def : Pat<(int_ppc_darn), (DARN 1)>; def : Pat<(int_ppc_darn), (DARN 1)>;
def : Pat<(int_ppc_darnraw), (DARN 2)>; def : Pat<(int_ppc_darnraw), (DARN 2)>;
class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),
!strconcat(opc, " $rA, $rB"), itin, pattern>{ !strconcat(opc, " $RA, $RB"), itin, pattern>{
let L = 1; let L = 1;
} }
class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),
!strconcat(opc, " $rA, $rB, $L"), itin, pattern>; !strconcat(opc, " $RA, $RB, $L"), itin, pattern>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
} }
// SLB Invalidate Entry Global // SLB Invalidate Entry Global
def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB),
"slbieg $RS, $RB", IIC_SprSLBIEG, []>; "slbieg $RST, $RB", IIC_SprSLBIEG, []>;
// SLB Synchronize // SLB Synchronize
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
} // IsISA3_0 } // IsISA3_0
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
(STDCX g8rc:$A, ForceXForm:$dst)>; (STDCX g8rc:$A, ForceXForm:$dst)>;
def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8), def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8),
(STDCX g8rc:$A, ForceXForm:$dst)>; (STDCX g8rc:$A, ForceXForm:$dst)>;
def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
(MFSPR8 $SPR)>; (MFSPR8 $SPR)>;
def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
(MTSPR8 $SPR, $RT)>; (MTSPR8 $SPR, $RT)>;

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Lines if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())
return C->isOne(); return C->isOne();
return false; return false;
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Helpers for defining instructions that directly correspond to intrinsics. // Helpers for defining instructions that directly correspond to intrinsics.
// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
// inputs doesn't match the type of the output. // inputs doesn't match the type of the output.
class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
// input types and an output type. // input types and an output type.
class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType In1Ty, ValueType In2Ty> ValueType In1Ty, ValueType In2Ty>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
[(set OutTy:$vD, [(set OutTy:$RT,
(IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;
// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
// inputs doesn't match the type of the output. // inputs doesn't match the type of the output.
class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;
// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
// input types and an output type. // input types and an output type.
class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType In1Ty, ValueType In2Ty> ValueType In1Ty, ValueType In2Ty>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP,
[(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; [(set OutTy:$VD, (IntID In1Ty:$VA, In2Ty:$VB))]>;
// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), : VXForm_2<xo, (outs vrrc:$VD), (ins vrrc:$VB),
!strconcat(opc, " $vD, $vB"), IIC_VecFP, !strconcat(opc, " $VD, $VB"), IIC_VecFP,
[(set v4f32:$vD, (IntID v4f32:$vB))]>; [(set v4f32:$VD, (IntID v4f32:$VB))]>;
// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
// inputs doesn't match the type of the output. // inputs doesn't match the type of the output.
class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), : VXForm_2<xo, (outs vrrc:$VD), (ins vrrc:$VB),
!strconcat(opc, " $vD, $vB"), IIC_VecFP, !strconcat(opc, " $VD, $VB"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vB))]>; [(set OutTy:$VD, (IntID InTy:$VB))]>;
class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), : VXForm_BX<xo, (outs vrrc:$VD), (ins vrrc:$VA),
!strconcat(opc, " $vD, $vA"), IIC_VecFP, !strconcat(opc, " $VD, $VA"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA))]>; [(set Ty:$VD, (IntID Ty:$VA))]>;
class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), : VXForm_CR<xo, (outs vrrc:$VD), (ins vrrc:$VA, u1imm:$ST, u4imm:$SIX),
!strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, !strconcat(opc, " $VD, $VA, $ST, $SIX"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA, timm:$ST, timm:$SIX))]>; [(set Ty:$VD, (IntID Ty:$VA, timm:$ST, timm:$SIX))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Definitions. // Instruction Definitions.
def HasAltivec : Predicate<"Subtarget->hasAltivec()">; def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
let Predicates = [HasAltivec] in { let Predicates = [HasAltivec] in {
def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
"dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
Deprecated<DeprecatedDST> { Deprecated<DeprecatedDST> {
let A = 0; let RA = 0;
let B = 0; let RB = 0;
} }
def DSSALL : DSS_Form<1, 822, (outs), (ins), def DSSALL : DSS_Form<1, 822, (outs), (ins),
"dssall", IIC_LdStLoad /*FIXME*/, []>, "dssall", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST> { Deprecated<DeprecatedDST> {
let STRM = 0; let STRM = 0;
let A = 0; let RA = 0;
let B = 0; let RB = 0;
} }
def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),
"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dst i32:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),
"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dstt i32:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),
"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dstst i32:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB),
"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dststt i32:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
// The very same instructions as above, but formally matching 64bit registers. // The very same instructions as above, but formally matching 64bit registers.
def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),
"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dst i64:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),
"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, [(int_ppc_altivec_dstt i64:$RA, i32:$RB, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),
"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dstst i64:$rA, i32:$rB, [(int_ppc_altivec_dstst i64:$RA, i32:$RB,
imm:$STRM)]>, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB),
"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/,
[(int_ppc_altivec_dststt i64:$rA, i32:$rB, [(int_ppc_altivec_dststt i64:$RA, i32:$RB,
imm:$STRM)]>, imm:$STRM)]>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
} }
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), def MFVSCR : VXForm_4<1540, (outs vrrc:$VD), (ins),
"mfvscr $vD", IIC_LdStStore, "mfvscr $VD", IIC_LdStStore,
[(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; [(set v8i16:$VD, (int_ppc_altivec_mfvscr))]>;
def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$VB),
"mtvscr $vB", IIC_LdStLoad, "mtvscr $VB", IIC_LdStLoad,
[(int_ppc_altivec_mtvscr v4i32:$vB)]>; [(int_ppc_altivec_mtvscr v4i32:$VB)]>;
} }
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.
def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvebx $vD, $src", IIC_LdStLoad, "lvebx $RST, $addr", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvebx ForceXForm:$src))]>; [(set v16i8:$RST, (int_ppc_altivec_lvebx ForceXForm:$addr))]>;
def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvehx $vD, $src", IIC_LdStLoad, "lvehx $RST, $addr", IIC_LdStLoad,
[(set v8i16:$vD, (int_ppc_altivec_lvehx ForceXForm:$src))]>; [(set v8i16:$RST, (int_ppc_altivec_lvehx ForceXForm:$addr))]>;
def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvewx $vD, $src", IIC_LdStLoad, "lvewx $RST, $addr", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvewx ForceXForm:$src))]>; [(set v4i32:$RST, (int_ppc_altivec_lvewx ForceXForm:$addr))]>;
def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), def LVX : XForm_1_memOp<31, 103, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvx $vD, $src", IIC_LdStLoad, "lvx $RST, $addr", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvx ForceXForm:$src))]>; [(set v4i32:$RST, (int_ppc_altivec_lvx ForceXForm:$addr))]>;
def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvxl $vD, $src", IIC_LdStLoad, "lvxl $RST, $addr", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvxl ForceXForm:$src))]>; [(set v4i32:$RST, (int_ppc_altivec_lvxl ForceXForm:$addr))]>;
} }
def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvsl $vD, $src", IIC_LdStLoad, "lvsl $RST, $addr", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvsl ForceXForm:$src))]>, [(set v16i8:$RST, (int_ppc_altivec_lvsl ForceXForm:$addr))]>,
PPC970_Unit_LSU; PPC970_Unit_LSU;
def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr),
"lvsr $vD, $src", IIC_LdStLoad, "lvsr $RST, $addr", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvsr ForceXForm:$src))]>, [(set v16i8:$RST, (int_ppc_altivec_lvsr ForceXForm:$addr))]>,
PPC970_Unit_LSU; PPC970_Unit_LSU;
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.
def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
"stvebx $rS, $dst", IIC_LdStStore, "stvebx $RST, $addr", IIC_LdStStore,
[(int_ppc_altivec_stvebx v16i8:$rS, ForceXForm:$dst)]>; [(int_ppc_altivec_stvebx v16i8:$RST, ForceXForm:$addr)]>;
def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
"stvehx $rS, $dst", IIC_LdStStore, "stvehx $RST, $addr", IIC_LdStStore,
[(int_ppc_altivec_stvehx v8i16:$rS, ForceXForm:$dst)]>; [(int_ppc_altivec_stvehx v8i16:$RST, ForceXForm:$addr)]>;
def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
"stvewx $rS, $dst", IIC_LdStStore, "stvewx $RST, $addr", IIC_LdStStore,
[(int_ppc_altivec_stvewx v4i32:$rS, ForceXForm:$dst)]>; [(int_ppc_altivec_stvewx v4i32:$RST, ForceXForm:$addr)]>;
def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
"stvx $rS, $dst", IIC_LdStStore, "stvx $RST, $addr", IIC_LdStStore,
[(int_ppc_altivec_stvx v4i32:$rS, ForceXForm:$dst)]>; [(int_ppc_altivec_stvx v4i32:$RST, ForceXForm:$addr)]>;
def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr),
"stvxl $rS, $dst", IIC_LdStStore, "stvxl $RST, $addr", IIC_LdStStore,
[(int_ppc_altivec_stvxl v4i32:$rS, ForceXForm:$dst)]>; [(int_ppc_altivec_stvxl v4i32:$RST, ForceXForm:$addr)]>;
} }
let PPC970_Unit = 5 in { // VALU Operations. let PPC970_Unit = 5 in { // VALU Operations.
// VA-Form instructions. 3-input AltiVec ops. // VA-Form instructions. 3-input AltiVec ops.
let isCommutable = 1 in { let isCommutable = 1 in {
def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), def VMADDFP : VAForm_1<46, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB),
"vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, "vmaddfp $RT, $RA, $RC, $RB", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$RT,
(fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; (fma v4f32:$RA, v4f32:$RC, v4f32:$RB))]>;
// FIXME: The fma+fneg pattern won't match because fneg is not legal. // FIXME: The fma+fneg pattern won't match because fneg is not legal.
def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), def VNMSUBFP: VAForm_1<47, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB),
"vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, "vnmsubfp $RT, $RA, $RC, $RB", IIC_VecFP,
[(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, [(set v4f32:$RT, (fneg (fma v4f32:$RA, v4f32:$RC,
(fneg v4f32:$vB))))]>; (fneg v4f32:$RB))))]>;
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
v8i16>; v8i16>;
} }
def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
} // isCommutable } // isCommutable
def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
v4i32, v4i32, v16i8>; v4i32, v4i32, v16i8>;
def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
// Shuffles. // Shuffles.
def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), def VSLDOI : VAForm_2<44, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, u4imm:$SH),
"vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, "vsldoi $RT, $RA, $RB, $SH", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$RT,
(PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; (PPCvecshl v16i8:$RA, v16i8:$RB, imm32SExt16:$SH))]>;
// VX-Form instructions. AltiVec arithmetic ops. // VX-Form instructions. AltiVec arithmetic ops.
let isCommutable = 1 in { let isCommutable = 1 in {
def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDFP : VXForm_1<10, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vaddfp $vD, $vA, $vB", IIC_VecFP, "vaddfp $VD, $VA, $VB", IIC_VecFP,
[(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; [(set v4f32:$VD, (fadd v4f32:$VA, v4f32:$VB))]>;
def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUBM : VXForm_1<0, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vaddubm $vD, $vA, $vB", IIC_VecGeneral, "vaddubm $VD, $VA, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (add v16i8:$VA, v16i8:$VB))]>;
def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUHM : VXForm_1<64, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vadduhm $vD, $vA, $vB", IIC_VecGeneral, "vadduhm $VD, $VA, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; [(set v8i16:$VD, (add v8i16:$VA, v8i16:$VB))]>;
def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUWM : VXForm_1<128, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vadduwm $vD, $vA, $vB", IIC_VecGeneral, "vadduwm $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (add v4i32:$VA, v4i32:$VB))]>;
def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
} // isCommutable } // isCommutable
let isCommutable = 1 in let isCommutable = 1 in
def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VAND : VXForm_1<1028, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vand $vD, $vA, $vB", IIC_VecFP, "vand $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (and v4i32:$VA, v4i32:$VB))]>;
def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VANDC : VXForm_1<1092, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vandc $vD, $vA, $vB", IIC_VecFP, "vandc $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, (and v4i32:$vA, [(set v4i32:$VD, (and v4i32:$VA,
(vnot v4i32:$vB)))]>; (vnot v4i32:$VB)))]>;
def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCFSX : VXForm_1<842, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfsx $vD, $vB, $UIMM", IIC_VecFP, "vcfsx $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$VD,
(int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>; (int_ppc_altivec_vcfsx v4i32:$VB, timm:$VA))]>;
def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCFUX : VXForm_1<778, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfux $vD, $vB, $UIMM", IIC_VecFP, "vcfux $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$VD,
(int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>; (int_ppc_altivec_vcfux v4i32:$VB, timm:$VA))]>;
def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCTSXS : VXForm_1<970, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctsxs $vD, $vB, $UIMM", IIC_VecFP, "vctsxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>; (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>;
def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCTUXS : VXForm_1<906, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctuxs $vD, $vB, $UIMM", IIC_VecFP, "vctuxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>; (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>;
// Defines with the UIM field set to 0 for floating-point // Defines with the UIM field set to 0 for floating-point
// to integer (fp_to_sint/fp_to_uint) conversions and integer // to integer (fp_to_sint/fp_to_uint) conversions and integer
// to floating-point (sint_to_fp/uint_to_fp) conversions. // to floating-point (sint_to_fp/uint_to_fp) conversions.
let isCodeGenOnly = 1, VA = 0 in { let isCodeGenOnly = 1, VA = 0 in {
def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), def VCFSX_0 : VXForm_1<842, (outs vrrc:$VD), (ins vrrc:$VB),
"vcfsx $vD, $vB, 0", IIC_VecFP, "vcfsx $VD, $VB, 0", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$VD,
(int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; (int_ppc_altivec_vcfsx v4i32:$VB, 0))]>;
def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), def VCTUXS_0 : VXForm_1<906, (outs vrrc:$VD), (ins vrrc:$VB),
"vctuxs $vD, $vB, 0", IIC_VecFP, "vctuxs $VD, $VB, 0", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; (int_ppc_altivec_vctuxs v4f32:$VB, 0))]>;
def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), def VCFUX_0 : VXForm_1<778, (outs vrrc:$VD), (ins vrrc:$VB),
"vcfux $vD, $vB, 0", IIC_VecFP, "vcfux $VD, $VB, 0", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$VD,
(int_ppc_altivec_vcfux v4i32:$vB, 0))]>; (int_ppc_altivec_vcfux v4i32:$VB, 0))]>;
def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), def VCTSXS_0 : VXForm_1<970, (outs vrrc:$VD), (ins vrrc:$VB),
"vctsxs $vD, $vB, 0", IIC_VecFP, "vctsxs $VD, $VB, 0", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; (int_ppc_altivec_vctsxs v4f32:$VB, 0))]>;
} }
def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
let isCommutable = 1 in { let isCommutable = 1 in {
def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
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def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
} // isCommutable } // isCommutable
def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHB : VXForm_1< 12, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrghb $vD, $vA, $vB", IIC_VecFP, "vmrghb $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrghb_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHH : VXForm_1< 76, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrghh $vD, $vA, $vB", IIC_VecFP, "vmrghh $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrghh_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHW : VXForm_1<140, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrghw $vD, $vA, $vB", IIC_VecFP, "vmrghw $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrghw_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLB : VXForm_1<268, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrglb $vD, $vA, $vB", IIC_VecFP, "vmrglb $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrglb_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLH : VXForm_1<332, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrglh $vD, $vA, $vB", IIC_VecFP, "vmrglh $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrglh_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLW : VXForm_1<396, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrglw $vD, $vA, $vB", IIC_VecFP, "vmrglw $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (vmrglw_shuffle v16i8:$VA, v16i8:$VB))]>;
def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
v4i32, v16i8, v4i32>; v4i32, v16i8, v4i32>;
def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
v4i32, v8i16, v4i32>; v4i32, v8i16, v4i32>;
def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
v4i32, v16i8, v4i32>; v4i32, v16i8, v4i32>;
def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
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def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBFP : VXForm_1<74, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsubfp $vD, $vA, $vB", IIC_VecGeneral, "vsubfp $VD, $VA, $VB", IIC_VecGeneral,
[(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; [(set v4f32:$VD, (fsub v4f32:$VA, v4f32:$VB))]>;
def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUBM : VXForm_1<1024, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsububm $vD, $vA, $vB", IIC_VecGeneral, "vsububm $VD, $VA, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (sub v16i8:$VA, v16i8:$VB))]>;
def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUHM : VXForm_1<1088, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsubuhm $vD, $vA, $vB", IIC_VecGeneral, "vsubuhm $VD, $VA, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; [(set v8i16:$VD, (sub v8i16:$VA, v8i16:$VB))]>;
def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUWM : VXForm_1<1152, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsubuwm $vD, $vA, $vB", IIC_VecGeneral, "vsubuwm $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (sub v4i32:$VA, v4i32:$VB))]>;
def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
v4i32, v16i8, v4i32>; v4i32, v16i8, v4i32>;
def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
v4i32, v8i16, v4i32>; v4i32, v8i16, v4i32>;
def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
v4i32, v16i8, v4i32>; v4i32, v16i8, v4i32>;
} }
def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VNOR : VXForm_1<1284, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vnor $vD, $vA, $vB", IIC_VecFP, "vnor $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, (vnot (or v4i32:$vA, [(set v4i32:$VD, (vnot (or v4i32:$VA,
v4i32:$vB)))]>; v4i32:$VB)))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VOR : VXForm_1<1156, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vor $vD, $vA, $vB", IIC_VecFP, "vor $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (or v4i32:$VA, v4i32:$VB))]>;
def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VXOR : VXForm_1<1220, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vxor $vD, $vA, $vB", IIC_VecFP, "vxor $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (xor v4i32:$VA, v4i32:$VB))]>;
} // isCommutable } // isCommutable
def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTB : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vspltb $vD, $vB, $UIMM", IIC_VecPerm, "vspltb $VD, $VB, $VA", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$VD,
(vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vspltb_shuffle:$VA v16i8:$VB, (undef)))]>;
def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTH : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vsplth $vD, $vB, $UIMM", IIC_VecPerm, "vsplth $VD, $VB, $VA", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$VD,
(vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vsplth_shuffle:$VA v16i8:$VB, (undef)))]>;
def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTW : VXForm_1<652, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vspltw $vD, $vB, $UIMM", IIC_VecPerm, "vspltw $VD, $VB, $VA", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$VD,
(vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vspltw_shuffle:$VA v16i8:$VB, (undef)))]>;
let isCodeGenOnly = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, hasSideEffects = 0 in {
def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), def VSPLTBs : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB),
"vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; "vspltb $VD, $VB, $VA", IIC_VecPerm, []>;
def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), def VSPLTHs : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB),
"vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; "vsplth $VD, $VB, $VA", IIC_VecPerm, []>;
} }
def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISB : VXForm_3<780, (outs vrrc:$VD), (ins s5imm:$IMM),
"vspltisb $vD, $SIMM", IIC_VecPerm, "vspltisb $VD, $IMM", IIC_VecPerm,
[(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; [(set v16i8:$VD, (v16i8 vecspltisb:$IMM))]>;
def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISH : VXForm_3<844, (outs vrrc:$VD), (ins s5imm:$IMM),
"vspltish $vD, $SIMM", IIC_VecPerm, "vspltish $VD, $IMM", IIC_VecPerm,
[(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; [(set v8i16:$VD, (v8i16 vecspltish:$IMM))]>;
def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISW : VXForm_3<908, (outs vrrc:$VD), (ins s5imm:$IMM),
"vspltisw $vD, $SIMM", IIC_VecPerm, "vspltisw $VD, $IMM", IIC_VecPerm,
[(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; [(set v4i32:$VD, (v4i32 vecspltisw:$IMM))]>;
// Vector Pack. // Vector Pack.
def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
v8i16, v4i32>; v8i16, v4i32>;
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
v16i8, v8i16>; v16i8, v8i16>;
def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
v16i8, v8i16>; v16i8, v8i16>;
def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
v8i16, v4i32>; v8i16, v4i32>;
def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
v8i16, v4i32>; v8i16, v4i32>;
def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
v16i8, v8i16>; v16i8, v8i16>;
def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
v8i16, v4i32>; v8i16, v4i32>;
} }
def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPKUHUM : VXForm_1<14, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vpkuhum $vD, $vA, $vB", IIC_VecFP, "vpkuhum $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$VD,
(vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; (vpkuhum_shuffle v16i8:$VA, v16i8:$VB))]>;
def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPKUWUM : VXForm_1<78, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vpkuwum $vD, $vA, $vB", IIC_VecFP, "vpkuwum $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$VD,
(vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; (vpkuwum_shuffle v16i8:$VA, v16i8:$VB))]>;
// Vector Unpack. // Vector Unpack.
def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
v4i32, v8i16>; v4i32, v8i16>;
def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
v8i16, v16i8>; v8i16, v16i8>;
def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
v4i32, v8i16>; v4i32, v8i16>;
def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
v4i32, v8i16>; v4i32, v8i16>;
def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
v8i16, v16i8>; v8i16, v16i8>;
def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
v4i32, v8i16>; v4i32, v8i16>;
// Altivec Comparisons. // Altivec Comparisons.
class VCMP<bits<10> xo, string asmstr, ValueType Ty> class VCMP<bits<10> xo, string asmstr, ValueType Ty>
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, : VXRForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), asmstr,
IIC_VecFPCompare, IIC_VecFPCompare,
[(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; [(set Ty:$VD, (Ty (PPCvcmp Ty:$VA, Ty:$VB, xo)))]>;
class VCMP_rec<bits<10> xo, string asmstr, ValueType Ty> class VCMP_rec<bits<10> xo, string asmstr, ValueType Ty>
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, : VXRForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), asmstr,
IIC_VecFPCompare, IIC_VecFPCompare,
[(set Ty:$vD, (Ty (PPCvcmp_rec Ty:$vA, Ty:$vB, xo)))]> { [(set Ty:$VD, (Ty (PPCvcmp_rec Ty:$VA, Ty:$VB, xo)))]> {
let Defs = [CR6]; let Defs = [CR6];
let RC = 1; let RC = 1;
} }
// f32 element comparisons.0 // f32 element comparisons.0
def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; def VCMPBFP : VCMP <966, "vcmpbfp $VD, $VA, $VB" , v4f32>;
def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $VD, $VA, $VB" , v4f32>;
def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; def VCMPEQFP : VCMP <198, "vcmpeqfp $VD, $VA, $VB" , v4f32>;
def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $VD, $VA, $VB", v4f32>;
def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; def VCMPGEFP : VCMP <454, "vcmpgefp $VD, $VA, $VB" , v4f32>;
def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $VD, $VA, $VB", v4f32>;
def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; def VCMPGTFP : VCMP <710, "vcmpgtfp $VD, $VA, $VB" , v4f32>;
def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $VD, $VA, $VB", v4f32>;
// i8 element comparisons. // i8 element comparisons.
def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; def VCMPEQUB : VCMP < 6, "vcmpequb $VD, $VA, $VB" , v16i8>;
def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $VD, $VA, $VB", v16i8>;
def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; def VCMPGTSB : VCMP <774, "vcmpgtsb $VD, $VA, $VB" , v16i8>;
def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $VD, $VA, $VB", v16i8>;
def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; def VCMPGTUB : VCMP <518, "vcmpgtub $VD, $VA, $VB" , v16i8>;
def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $VD, $VA, $VB", v16i8>;
// i16 element comparisons. // i16 element comparisons.
def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; def VCMPEQUH : VCMP < 70, "vcmpequh $VD, $VA, $VB" , v8i16>;
def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $VD, $VA, $VB", v8i16>;
def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; def VCMPGTSH : VCMP <838, "vcmpgtsh $VD, $VA, $VB" , v8i16>;
def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $VD, $VA, $VB", v8i16>;
def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; def VCMPGTUH : VCMP <582, "vcmpgtuh $VD, $VA, $VB" , v8i16>;
def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $VD, $VA, $VB", v8i16>;
// i32 element comparisons. // i32 element comparisons.
def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; def VCMPEQUW : VCMP <134, "vcmpequw $VD, $VA, $VB" , v4i32>;
def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $vD, $vA, $vB", v4i32>; def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $VD, $VA, $VB", v4i32>;
def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; def VCMPGTSW : VCMP <902, "vcmpgtsw $VD, $VA, $VB" , v4i32>;
def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $VD, $VA, $VB", v4i32>;
def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; def VCMPGTUW : VCMP <646, "vcmpgtuw $VD, $VA, $VB" , v4i32>;
def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $VD, $VA, $VB", v4i32>;
let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
isReMaterializable = 1 in { isReMaterializable = 1 in {
def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0B : VXForm_setzero<1220, (outs vrrc:$VD), (ins),
"vxor $vD, $vD, $vD", IIC_VecFP, "vxor $VD, $VD, $VD", IIC_VecFP,
[(set v16i8:$vD, (v16i8 immAllZerosV))]>; [(set v16i8:$VD, (v16i8 immAllZerosV))]>;
def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0H : VXForm_setzero<1220, (outs vrrc:$VD), (ins),
"vxor $vD, $vD, $vD", IIC_VecFP, "vxor $VD, $VD, $VD", IIC_VecFP,
[(set v8i16:$vD, (v8i16 immAllZerosV))]>; [(set v8i16:$VD, (v8i16 immAllZerosV))]>;
def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0 : VXForm_setzero<1220, (outs vrrc:$VD), (ins),
"vxor $vD, $vD, $vD", IIC_VecFP, "vxor $VD, $VD, $VD", IIC_VecFP,
[(set v4i32:$vD, (v4i32 immAllZerosV))]>; [(set v4i32:$VD, (v4i32 immAllZerosV))]>;
let IMM=-1 in { let IMM=-1 in {
def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONESB : VXForm_3<908, (outs vrrc:$VD), (ins),
"vspltisw $vD, -1", IIC_VecFP, "vspltisw $VD, -1", IIC_VecFP,
[(set v16i8:$vD, (v16i8 immAllOnesV))]>; [(set v16i8:$VD, (v16i8 immAllOnesV))]>;
def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONESH : VXForm_3<908, (outs vrrc:$VD), (ins),
"vspltisw $vD, -1", IIC_VecFP, "vspltisw $VD, -1", IIC_VecFP,
[(set v8i16:$vD, (v8i16 immAllOnesV))]>; [(set v8i16:$VD, (v8i16 immAllOnesV))]>;
def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONES : VXForm_3<908, (outs vrrc:$VD), (ins),
"vspltisw $vD, -1", IIC_VecFP, "vspltisw $VD, -1", IIC_VecFP,
[(set v4i32:$vD, (v4i32 immAllOnesV))]>; [(set v4i32:$VD, (v4i32 immAllOnesV))]>;
} }
} }
} // VALU Operations. } // VALU Operations.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Additional Altivec Patterns // Additional Altivec Patterns
// //
▲ Show 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),
(v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
} // end HasAltivec } // end HasAltivec
// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
: VX_RD5_RSp5_PS1_XO9<xo, : VX_RD5_RSp5_PS1_XO9<xo,
(outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, u1imm:$PS),
!strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { !strconcat(opc, " $VD, $VA, $VB, $PS"), IIC_VecFP, pattern> {
let Defs = [CR6]; let Defs = [CR6];
} }
// [PO VRT VRA VRB 1 / XO] // [PO VRT VRA VRB 1 / XO]
class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
: VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP, pattern> {
let Defs = [CR6]; let Defs = [CR6];
let PS = 0; let PS = 0;
} }
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
let Predicates = [HasP8Altivec] in { let Predicates = [HasP8Altivec] in {
let isCommutable = 1 in { let isCommutable = 1 in {
def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
v2i64, v4i32>; v2i64, v4i32>;
def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
v2i64, v4i32>; v2i64, v4i32>;
def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
v2i64, v4i32>; v2i64, v4i32>;
def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
v2i64, v4i32>; v2i64, v4i32>;
def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULUWM : VXForm_1<137, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmuluwm $vD, $vA, $vB", IIC_VecGeneral, "vmuluwm $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (mul v4i32:$VA, v4i32:$VB))]>;
def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
} // isCommutable } // isCommutable
// Vector merge // Vector merge
def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGEW : VXForm_1<1932, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrgew $vD, $vA, $vB", IIC_VecFP, "vmrgew $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$VD,
(v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; (v16i8 (vmrgew_shuffle v16i8:$VA, v16i8:$VB)))]>;
def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGOW : VXForm_1<1676, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmrgow $vD, $vA, $vB", IIC_VecFP, "vmrgow $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$VD,
(v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; (v16i8 (vmrgow_shuffle v16i8:$VA, v16i8:$VB)))]>;
// Match vmrgew(x,x) and vmrgow(x,x) // Match vmrgew(x,x) and vmrgow(x,x)
def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),
(VMRGEW $vA, $vA)>; (VMRGEW $vA, $vA)>;
def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),
(VMRGOW $vA, $vA)>; (VMRGOW $vA, $vA)>;
// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments // Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments
// are matched for little-endian, where the inputs must be swapped for correct // are matched for little-endian, where the inputs must be swapped for correct
// semantics.w // semantics.w
def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),
(VMRGEW $vB, $vA)>; (VMRGEW $vB, $vA)>;
def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),
(VMRGOW $vB, $vA)>; (VMRGOW $vB, $vA)>;
// Vector rotates. // Vector rotates.
def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)),
(v2i64 (VRLD v2i64:$vA, v2i64:$vB))>; (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>;
// Vector shifts // Vector shifts
def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSLD : VXForm_1<1476, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsld $vD, $vA, $vB", IIC_VecGeneral, []>; "vsld $VD, $VA, $VB", IIC_VecGeneral, []>;
def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSRD : VXForm_1<1732, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; "vsrd $VD, $VA, $VB", IIC_VecGeneral, []>;
def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSRAD : VXForm_1<964, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; "vsrad $VD, $VA, $VB", IIC_VecGeneral, []>;
def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)),
(v2i64 (VSLD $vA, $vB))>; (v2i64 (VSLD $vA, $vB))>;
def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)),
(v2i64 (VSLD $vA, $vB))>; (v2i64 (VSLD $vA, $vB))>;
def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)),
(v2i64 (VSRD $vA, $vB))>; (v2i64 (VSRD $vA, $vB))>;
def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)),
(v2i64 (VSRD $vA, $vB))>; (v2i64 (VSRD $vA, $vB))>;
def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)),
(v2i64 (VSRAD $vA, $vB))>; (v2i64 (VSRAD $vA, $vB))>;
def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)),
(v2i64 (VSRAD $vA, $vB))>; (v2i64 (VSRAD $vA, $vB))>;
// Vector Integer Arithmetic Instructions // Vector Integer Arithmetic Instructions
let isCommutable = 1 in { let isCommutable = 1 in {
def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUDM : VXForm_1<192, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vaddudm $vD, $vA, $vB", IIC_VecGeneral, "vaddudm $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (add v2i64:$VA, v2i64:$VB))]>;
def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUQM : VXForm_1<256, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vadduqm $vD, $vA, $vB", IIC_VecGeneral, "vadduqm $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (add v1i128:$VA, v1i128:$VB))]>;
} // isCommutable } // isCommutable
// Vector Quadword Add // Vector Quadword Add
def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>;
def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>;
def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>;
// Vector Doubleword Subtract // Vector Doubleword Subtract
def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUDM : VXForm_1<1216, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsubudm $vD, $vA, $vB", IIC_VecGeneral, "vsubudm $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (sub v2i64:$VA, v2i64:$VB))]>;
// Vector Quadword Subtract // Vector Quadword Subtract
def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUQM : VXForm_1<1280, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vsubuqm $vD, $vA, $vB", IIC_VecGeneral, "vsubuqm $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (sub v1i128:$VA, v1i128:$VB))]>;
def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>;
def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>;
def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>;
// Count Leading Zeros // Count Leading Zeros
def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), def VCLZB : VXForm_2<1794, (outs vrrc:$VD), (ins vrrc:$VB),
"vclzb $vD, $vB", IIC_VecGeneral, "vclzb $VD, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (ctlz v16i8:$vB))]>; [(set v16i8:$VD, (ctlz v16i8:$VB))]>;
def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), def VCLZH : VXForm_2<1858, (outs vrrc:$VD), (ins vrrc:$VB),
"vclzh $vD, $vB", IIC_VecGeneral, "vclzh $VD, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (ctlz v8i16:$vB))]>; [(set v8i16:$VD, (ctlz v8i16:$VB))]>;
def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), def VCLZW : VXForm_2<1922, (outs vrrc:$VD), (ins vrrc:$VB),
"vclzw $vD, $vB", IIC_VecGeneral, "vclzw $VD, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (ctlz v4i32:$vB))]>; [(set v4i32:$VD, (ctlz v4i32:$VB))]>;
def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), def VCLZD : VXForm_2<1986, (outs vrrc:$VD), (ins vrrc:$VB),
"vclzd $vD, $vB", IIC_VecGeneral, "vclzd $VD, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (ctlz v2i64:$vB))]>; [(set v2i64:$VD, (ctlz v2i64:$VB))]>;
// Population Count // Population Count
def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), def VPOPCNTB : VXForm_2<1795, (outs vrrc:$VD), (ins vrrc:$VB),
"vpopcntb $vD, $vB", IIC_VecGeneral, "vpopcntb $VD, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (ctpop v16i8:$vB))]>; [(set v16i8:$VD, (ctpop v16i8:$VB))]>;
def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), def VPOPCNTH : VXForm_2<1859, (outs vrrc:$VD), (ins vrrc:$VB),
"vpopcnth $vD, $vB", IIC_VecGeneral, "vpopcnth $VD, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (ctpop v8i16:$vB))]>; [(set v8i16:$VD, (ctpop v8i16:$VB))]>;
def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), def VPOPCNTW : VXForm_2<1923, (outs vrrc:$VD), (ins vrrc:$VB),
"vpopcntw $vD, $vB", IIC_VecGeneral, "vpopcntw $VD, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (ctpop v4i32:$vB))]>; [(set v4i32:$VD, (ctpop v4i32:$VB))]>;
def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), def VPOPCNTD : VXForm_2<1987, (outs vrrc:$VD), (ins vrrc:$VB),
"vpopcntd $vD, $vB", IIC_VecGeneral, "vpopcntd $VD, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (ctpop v2i64:$vB))]>; [(set v2i64:$VD, (ctpop v2i64:$VB))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
// VSX equivalents. We need to fix this up at some point. Two possible // VSX equivalents. We need to fix this up at some point. Two possible
// solutions for this problem: // solutions for this problem:
// 1. Disable Altivec patterns that compete with VSX patterns using the // 1. Disable Altivec patterns that compete with VSX patterns using the
// !HasVSX predicate. This essentially favours VSX over Altivec, in // !HasVSX predicate. This essentially favours VSX over Altivec, in
// hopes of reducing register pressure (larger register set using VSX // hopes of reducing register pressure (larger register set using VSX
// instructions than VMX instructions) // instructions than VMX instructions)
// 2. Employ a more disciplined use of AddedComplexity, which would provide // 2. Employ a more disciplined use of AddedComplexity, which would provide
// more fine-grained control than option 1. This would be beneficial // more fine-grained control than option 1. This would be beneficial
// if we find situations where Altivec is really preferred over VSX. // if we find situations where Altivec is really preferred over VSX.
def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VEQV : VXForm_1<1668, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"veqv $vD, $vA, $vB", IIC_VecGeneral, "veqv $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (vnot (xor v4i32:$vA, v4i32:$vB)))]>; [(set v4i32:$VD, (vnot (xor v4i32:$VA, v4i32:$VB)))]>;
def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VNAND : VXForm_1<1412, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vnand $vD, $vA, $vB", IIC_VecGeneral, "vnand $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (vnot (and v4i32:$vA, v4i32:$vB)))]>; [(set v4i32:$VD, (vnot (and v4i32:$VA, v4i32:$VB)))]>;
} // isCommutable } // isCommutable
def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VORC : VXForm_1<1348, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vorc $vD, $vA, $vB", IIC_VecGeneral, "vorc $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (or v4i32:$vA, [(set v4i32:$VD, (or v4i32:$VA,
(vnot v4i32:$vB)))]>; (vnot v4i32:$VB)))]>;
// i64 element comparisons. // i64 element comparisons.
def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; def VCMPEQUD : VCMP <199, "vcmpequd $VD, $VA, $VB" , v2i64>;
def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $vD, $vA, $vB", v2i64>; def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $VD, $VA, $VB", v2i64>;
def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; def VCMPGTSD : VCMP <967, "vcmpgtsd $VD, $VA, $VB" , v2i64>;
def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $VD, $VA, $VB", v2i64>;
def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; def VCMPGTUD : VCMP <711, "vcmpgtud $VD, $VA, $VB" , v2i64>;
def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $VD, $VA, $VB", v2i64>;
// The cryptography instructions that do not require Category:Vector.Crypto // The cryptography instructions that do not require Category:Vector.Crypto
def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
int_ppc_altivec_crypto_vpmsumb, v16i8>; int_ppc_altivec_crypto_vpmsumb, v16i8>;
def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
int_ppc_altivec_crypto_vpmsumh, v8i16>; int_ppc_altivec_crypto_vpmsumh, v8i16>;
def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
int_ppc_altivec_crypto_vpmsumw, v4i32>; int_ppc_altivec_crypto_vpmsumw, v4i32>;
def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
int_ppc_altivec_crypto_vpmsumd, v2i64>; int_ppc_altivec_crypto_vpmsumd, v2i64>;
def VPERMXOR : VAForm_1<45, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VC), def VPERMXOR : VAForm_1<45, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
"vpermxor $VD, $VA, $VB, $VC", IIC_VecFP, []>; "vpermxor $RT, $RA, $RB, $RC", IIC_VecFP, []>;
// Vector doubleword integer pack and unpack. // Vector doubleword integer pack and unpack.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
v4i32, v2i64>; v4i32, v2i64>;
def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
v4i32, v2i64>; v4i32, v2i64>;
def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,
v4i32, v2i64>; v4i32, v2i64>;
} }
def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPKUDUM : VXForm_1<1102, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vpkudum $vD, $vA, $vB", IIC_VecFP, "vpkudum $VD, $VA, $VB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$VD,
(vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; (vpkudum_shuffle v16i8:$VA, v16i8:$VB))]>;
def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,
v2i64, v4i32>; v2i64, v4i32>;
def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
v2i64, v4i32>; v2i64, v4i32>;
def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>; def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>;
def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>; def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>;
def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)), def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)),
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def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
let Predicates = [HasP9Altivec] in { let Predicates = [HasP9Altivec] in {
// Vector Multiply-Sum // Vector Multiply-Sum
def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
v1i128, v2i64, v1i128>; v1i128, v2i64, v1i128>;
// i8 element comparisons. // i8 element comparisons.
def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; def VCMPNEB : VCMP < 7, "vcmpneb $VD, $VA, $VB" , v16i8>;
def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $VD, $VA, $VB" , v16i8>;
def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; def VCMPNEZB : VCMP <263, "vcmpnezb $VD, $VA, $VB" , v16i8>;
def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $VD, $VA, $VB", v16i8>;
// i16 element comparisons. // i16 element comparisons.
def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; def VCMPNEH : VCMP < 71, "vcmpneh $VD, $VA, $VB" , v8i16>;
def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $VD, $VA, $VB" , v8i16>;
def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; def VCMPNEZH : VCMP <327, "vcmpnezh $VD, $VA, $VB" , v8i16>;
def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $VD, $VA, $VB", v8i16>;
// i32 element comparisons. // i32 element comparisons.
def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; def VCMPNEW : VCMP <135, "vcmpnew $VD, $VA, $VB" , v4i32>;
def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $VD, $VA, $VB" , v4i32>;
def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; def VCMPNEZW : VCMP <391, "vcmpnezw $VD, $VA, $VB" , v4i32>;
def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $VD, $VA, $VB", v4i32>;
// VX-Form: [PO VRT / UIM VRB XO]. // VX-Form: [PO VRT / UIM VRB XO].
// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
// "/ UIM" (1 + 4 bit) // "/ UIM" (1 + 4 bit)
class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins u4imm:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; !strconcat(opc, " $VD, $VB, $VA"), IIC_VecGeneral, pattern>;
class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), : VXForm_1<xo, (outs g8rc:$VD), (ins g8rc:$VA, vrrc:$VB),
!strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>;
// Vector Extract Unsigned // Vector Extract Unsigned
def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64; def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64;
def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64; def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64;
def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64; def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64;
def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64; def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64;
def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64; def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64;
def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64; def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64;
} }
// Vector Insert Element Instructions // Vector Insert Element Instructions
def VINSERTB : VXForm_1<781, (outs vrrc:$vD), def VINSERTB : VXForm_1<781, (outs vrrc:$VD),
(ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB),
"vinsertb $vD, $vB, $UIM", IIC_VecGeneral, "vinsertb $VD, $VB, $VA", IIC_VecGeneral,
[(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, [(set v16i8:$VD, (PPCvecinsert v16i8:$VDi, v16i8:$VB,
imm32SExt16:$UIM))]>, imm32SExt16:$VA))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VINSERTH : VXForm_1<845, (outs vrrc:$vD), def VINSERTH : VXForm_1<845, (outs vrrc:$VD),
(ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB),
"vinserth $vD, $vB, $UIM", IIC_VecGeneral, "vinserth $VD, $VB, $VA", IIC_VecGeneral,
[(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, [(set v8i16:$VD, (PPCvecinsert v8i16:$VDi, v8i16:$VB,
imm32SExt16:$UIM))]>, imm32SExt16:$VA))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
: VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$VD), (ins vrrc:$VB),
!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; !strconcat(opc, " $VD, $VB"), IIC_VecGeneral, pattern>;
class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
: VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$VD), (ins vfrc:$VB),
!strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; !strconcat(opc, " $VD, $VB"), IIC_VecGeneral, pattern>;
// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] // Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[RD]
def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$VD), (ins vrrc:$VB),
"vclzlsbb $rD, $vB", IIC_VecGeneral, "vclzlsbb $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, (int_ppc_altivec_vclzlsbb [(set i32:$VD, (int_ppc_altivec_vclzlsbb
v16i8:$vB))]>; v16i8:$VB))]>;
def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$VD), (ins vrrc:$VB),
"vctzlsbb $rD, $vB", IIC_VecGeneral, "vctzlsbb $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, (int_ppc_altivec_vctzlsbb [(set i32:$VD, (int_ppc_altivec_vctzlsbb
v16i8:$vB))]>; v16i8:$VB))]>;
// Vector Count Trailing Zeros // Vector Count Trailing Zeros
def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
[(set v16i8:$vD, (cttz v16i8:$vB))]>; [(set v16i8:$VD, (cttz v16i8:$VB))]>;
def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
[(set v8i16:$vD, (cttz v8i16:$vB))]>; [(set v8i16:$VD, (cttz v8i16:$VB))]>;
def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
[(set v4i32:$vD, (cttz v4i32:$vB))]>; [(set v4i32:$VD, (cttz v4i32:$VB))]>;
def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
[(set v2i64:$vD, (cttz v2i64:$vB))]>; [(set v2i64:$VD, (cttz v2i64:$VB))]>;
// Vector Extend Sign // Vector Extend Sign
def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w",
[(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>; [(set v4i32:$VD, (int_ppc_altivec_vextsb2w v16i8:$VB))]>;
def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w",
[(set v4i32:$vD, (int_ppc_altivec_vextsh2w v8i16:$vB))]>; [(set v4i32:$VD, (int_ppc_altivec_vextsh2w v8i16:$VB))]>;
def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsb2d v16i8:$vB))]>; [(set v2i64:$VD, (int_ppc_altivec_vextsb2d v16i8:$VB))]>;
def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsh2d v8i16:$vB))]>; [(set v2i64:$VD, (int_ppc_altivec_vextsh2d v8i16:$VB))]>;
def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsw2d v4i32:$vB))]>; [(set v2i64:$VD, (int_ppc_altivec_vextsw2d v4i32:$VB))]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;
def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;
def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;
def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
} }
def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>; def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>;
def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>; def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>;
def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>; def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>;
def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>; def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>;
def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>; def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>;
// Vector Integer Negate // Vector Integer Negate
def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",
[(set v4i32:$vD, [(set v4i32:$VD,
(sub (v4i32 immAllZerosV), v4i32:$vB))]>; (sub (v4i32 immAllZerosV), v4i32:$VB))]>;
def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
[(set v2i64:$vD, [(set v2i64:$VD,
(sub (v2i64 immAllZerosV), v2i64:$vB))]>; (sub (v2i64 immAllZerosV), v2i64:$VB))]>;
// Vector Parity Byte // Vector Parity Byte
def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$VD,
(int_ppc_altivec_vprtybw v4i32:$vB))]>; (int_ppc_altivec_vprtybw v4i32:$VB))]>;
def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$VD,
(int_ppc_altivec_vprtybd v2i64:$vB))]>; (int_ppc_altivec_vprtybd v2i64:$VB))]>;
def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$VD,
(int_ppc_altivec_vprtybq v1i128:$vB))]>; (int_ppc_altivec_vprtybq v1i128:$VB))]>;
// Vector (Bit) Permute (Right-indexed) // Vector (Bit) Permute (Right-indexed)
def VBPERMD : VX1_Int_Ty3<1484, "vbpermd", int_ppc_altivec_vbpermd, def VBPERMD : VX1_Int_Ty3<1484, "vbpermd", int_ppc_altivec_vbpermd,
v2i64, v2i64, v16i8>; v2i64, v2i64, v16i8>;
def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), def VPERMR : VAForm_1a<59, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
"vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; "vpermr $RT, $RA, $RB, $RC", IIC_VecFP, []>;
class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; !strconcat(opc, " $VD, $VA, $VB"), IIC_VecFP, pattern>;
// Vector Rotate Left Mask/Mask-Insert // Vector Rotate Left Mask/Mask-Insert
def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm",
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vrlwnm v4i32:$vA, (int_ppc_altivec_vrlwnm v4i32:$VA,
v4i32:$vB))]>; v4i32:$VB))]>;
def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), def VRLWMI : VXForm_1<133, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
"vrlwmi $vD, $vA, $vB", IIC_VecFP, "vrlwmi $VD, $VA, $VB", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, (int_ppc_altivec_vrlwmi v4i32:$VA, v4i32:$VB,
v4i32:$vDi))]>, v4i32:$VDi))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm",
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vrldnm v2i64:$vA, (int_ppc_altivec_vrldnm v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), def VRLDMI : VXForm_1<197, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
"vrldmi $vD, $vA, $vB", IIC_VecFP, "vrldmi $VD, $VA, $VB", IIC_VecFP,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, (int_ppc_altivec_vrldmi v2i64:$VA, v2i64:$VB,
v2i64:$vDi))]>, v2i64:$VDi))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
// Vector Shift Left/Right // Vector Shift Left/Right
def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
[(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; [(set v16i8 : $VD, (int_ppc_altivec_vslv v16i8 : $VA, v16i8 : $VB))]>;
def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
[(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; [(set v16i8 : $VD, (int_ppc_altivec_vsrv v16i8 : $VA, v16i8 : $VB))]>;
// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), def VMUL10UQ : VXForm_BX<513, (outs vrrc:$VD), (ins vrrc:$VA),
"vmul10uq $vD, $vA", IIC_VecFP, []>; "vmul10uq $VD, $VA", IIC_VecFP, []>;
def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$VD), (ins vrrc:$VA),
"vmul10cuq $vD, $vA", IIC_VecFP, []>; "vmul10cuq $VD, $VA", IIC_VecFP, []>;
// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
// Decimal Integer Format Conversion Instructions // Decimal Integer Format Conversion Instructions
// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
list<dag> pattern> list<dag> pattern>
: VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$VD), (ins vrrc:$VB, u1imm:$PS),
!strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { !strconcat(opc, " $VD, $VB, $PS"), IIC_VecFP, pattern> {
let Defs = [CR6]; let Defs = [CR6];
} }
// [PO VRT EO VRB 1 / XO] // [PO VRT EO VRB 1 / XO]
class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
list<dag> pattern> list<dag> pattern>
: VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$VD), (ins vrrc:$VB),
!strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { !strconcat(opc, " $VD, $VB"), IIC_VecFP, pattern> {
let Defs = [CR6]; let Defs = [CR6];
let PS = 0; let PS = 0;
} }
// Decimal Convert From/to National/Zoned/Signed-QWord // Decimal Convert From/to National/Zoned/Signed-QWord
def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>;
Show All 12 Lines
def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>;
def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
// Decimal (Unsigned) Truncate // Decimal (Unsigned) Truncate
def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;
// Absolute Difference // Absolute Difference
def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VABSDUB : VXForm_1<1027, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vabsdub $vD, $vA, $vB", IIC_VecGeneral, "vabsdub $VD, $VA, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$VD, (int_ppc_altivec_vabsdub v16i8:$VA, v16i8:$VB))]>;
def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VABSDUH : VXForm_1<1091, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vabsduh $vD, $vA, $vB", IIC_VecGeneral, "vabsduh $VD, $VA, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; [(set v8i16:$VD, (int_ppc_altivec_vabsduh v8i16:$VA, v8i16:$VB))]>;
def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VABSDUW : VXForm_1<1155, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vabsduw $vD, $vA, $vB", IIC_VecGeneral, "vabsduw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (int_ppc_altivec_vabsduw v4i32:$VA, v4i32:$VB))]>;
} // end HasP9Altivec } // end HasP9Altivec

llvm/lib/Target/PowerPC/PPCInstrFormats.td

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Linesclass BForm_3_at<bits<6> opcode, bit aa, bit lk,
let Inst{6-8} = BO{4-2}; let Inst{6-8} = BO{4-2};
let Inst{9-10} = at; let Inst{9-10} = at;
let Inst{11-15} = BI; let Inst{11-15} = BI;
let Inst{16-29} = BD; let Inst{16-29} = BD;
let Inst{30} = aa; let Inst{30} = aa;
let Inst{31} = lk; let Inst{31} = lk;
} }
class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, class
BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
dag OOL, dag IOL, string asmstr> dag OOL, dag IOL, string asmstr>
: I<opcode, OOL, IOL, asmstr, IIC_BrB> { : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<5> BI; bits<5> BI;
bits<14> BD; bits<14> BD;
let Inst{6-10} = bo; let Inst{6-10} = bo;
let Inst{11-15} = BI; let Inst{11-15} = BI;
let Inst{16-29} = BD; let Inst{16-29} = BD;
Show All 11 Linesclass SCForm<bits<6> opcode, bits<1> xo,
let Pattern = pattern; let Pattern = pattern;
let Inst{20-26} = LEV; let Inst{20-26} = LEV;
let Inst{30} = xo; let Inst{30} = xo;
} }
// 1.7.4 D-Form // 1.7.4 D-Form
class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RST;
bits<5> B; bits<5> RA;
bits<16> C; bits<16> D;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = A; let Inst{6-10} = RST;
let Inst{11-15} = B; let Inst{11-15} = RA;
let Inst{16-31} = C; let Inst{16-31} = D;
} }
class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RST;
bits<21> Addr; // FIXME: bogus names, to force positional matching for the moment.
bits<21> addr_foo;
let Pattern = pattern;
let Inst{6-10} = A;
let Inst{11-15} = Addr{20-16}; // Base Reg
let Inst{16-31} = Addr{15-0}; // Displacement
}
class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A;
bits<16> C;
bits<5> B;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = A; let Inst{6-10} = RST;
let Inst{11-15} = B; let Inst{11-15} = addr_foo{20-16}; // Base Reg
let Inst{16-31} = C; let Inst{16-31} = addr_foo{15-0}; // Displacement
} }
class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
// Even though ADDIC_rec does not really have an RC bit, provide // Even though ADDIC_rec does not really have an RC bit, provide
// the declaration of one here so that isRecordForm has something to set. // the declaration of one here so that isRecordForm has something to set.
bit RC = 0; bit RC = 0;
} }
class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RST;
bits<16> B; bits<16> D;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = A; let Inst{6-10} = RST;
let Inst{11-15} = 0; let Inst{11-15} = 0;
let Inst{16-31} = B; let Inst{16-31} = D;
} }
class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> B; bits<5> RA;
bits<5> A; bits<5> RST;
bits<16> C; bits<16> D;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = A; let Inst{6-10} = RST;
let Inst{11-15} = B; let Inst{11-15} = RA;
let Inst{16-31} = C; let Inst{16-31} = D;
} }
class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
let A = 0; let RST = 0;
let Addr = 0; let addr_foo = 0;
} }
class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, string asmstr, InstrItinClass itin,
list<dag> pattern> list<dag> pattern>
: DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
let A = R; let RST = R;
let B = R; let RA = R;
let C = 0; let D = 0;
} }
class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
dag OOL, dag IOL, string asmstr, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RST;
bits<21> Addr; bits<21> addr;
let Pattern = pattern; let Pattern = pattern;
bits<24> LI; bits<24> LI;
let Inst{6-29} = LI; let Inst{6-29} = LI;
let Inst{30} = aa; let Inst{30} = aa;
let Inst{31} = lk; let Inst{31} = lk;
let Inst{38-42} = A; let Inst{38-42} = RST;
let Inst{43-47} = Addr{20-16}; // Base Reg let Inst{43-47} = addr{20-16}; // Base Reg
let Inst{48-63} = Addr{15-0}; // Displacement let Inst{48-63} = addr{15-0}; // Displacement
} }
// This is used to emit BL8+NOP. // This is used to emit BL8+NOP.
class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
dag OOL, dag IOL, string asmstr, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: IForm_and_DForm_1<opcode1, aa, lk, opcode2, : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
OOL, IOL, asmstr, itin, pattern> { OOL, IOL, asmstr, itin, pattern> {
let A = 0; let RST = 0;
let Addr = 0; let addr = 0;
} }
class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF; bits<3> BF;
bits<1> L; bits<1> L;
bits<5> RA; bits<5> RA;
bits<16> I; bits<16> D;
let Inst{6-8} = BF; let Inst{6-8} = BF;
let Inst{9} = 0; let Inst{9} = 0;
let Inst{10} = L; let Inst{10} = L;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-31} = I; let Inst{16-31} = D;
} }
class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: DForm_5<opcode, OOL, IOL, asmstr, itin> { : DForm_5<opcode, OOL, IOL, asmstr, itin> {
let L = PPC64; let L = PPC64;
} }
class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: DForm_5<opcode, OOL, IOL, asmstr, itin>; : DForm_5<opcode, OOL, IOL, asmstr, itin>;
class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: DForm_6<opcode, OOL, IOL, asmstr, itin> { : DForm_6<opcode, OOL, IOL, asmstr, itin> {
let L = PPC64; let L = PPC64;
} }
// 1.7.5 DS-Form // 1.7.5 DS-Form
class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RST; bits<5> RST;
bits<19> DS_RA; // FIXME: bogus names, to force positional matching for the moment.rr
bits<19> addr_foo;
bits<14> DS;
bits<5> RA;
let DS = addr_foo{13-0};
let RA = addr_foo{18-14};
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RST; let Inst{6-10} = RST;
let Inst{11-15} = DS_RA{18-14}; // Register # let Inst{11-15} = RA;
let Inst{16-29} = DS_RA{13-0}; // Displacement. let Inst{16-29} = DS;
let Inst{30-31} = xo; let Inst{30-31} = xo;
} }
// ISA V3.0B 1.6.6 DX-Form // ISA V3.0B 1.6.6 DX-Form
class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<16> D; bits<16> D;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-15} = D{5-1}; // d1 let Inst{11-15} = D{5-1}; // d1
let Inst{16-25} = D{15-6}; // d0 let Inst{16-25} = D{15-6}; // d0
let Inst{26-30} = xo; let Inst{26-30} = xo;
let Inst{31} = D{0}; // d2 let Inst{31} = D{0}; // d2
} }
// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<6> XT; bits<6> XT;
bits<17> DS_RA; bits<17> addr;
bits<5> RA;
bits<12> DQ;
let RA = addr{16-12};
let DQ = addr{11-0};
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = XT{4-0}; let Inst{6-10} = XT{4-0};
let Inst{11-15} = DS_RA{16-12}; // Register # let Inst{11-15} = RA;
let Inst{16-27} = DS_RA{11-0}; // Displacement. let Inst{16-27} = DQ;
let Inst{28} = XT{5}; let Inst{28} = XT{5};
let Inst{29-31} = xo; let Inst{29-31} = xo;
} }
class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, string asmstr, InstrItinClass itin,
list<dag> pattern> list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RTp; bits<5> RTp;
bits<17> DQ_RA; bits<17> addr;
bits<5> RA;
bits<12> DQ;
let RA = addr{16-12};
let DQ = addr{11-0};
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RTp{4-0}; let Inst{6-10} = RTp{4-0};
let Inst{11-15} = DQ_RA{16-12}; // Register # let Inst{11-15} = RA;
let Inst{16-27} = DQ_RA{11-0}; // Displacement. let Inst{16-27} = DQ;
let Inst{28-31} = xo; let Inst{28-31} = xo;
} }
// 1.7.6 X-Form // 1.7.6 X-Form
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RST; bits<5> RST;
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
bit RC = 0; // set by isRecordForm bit RC = 0; // set by isRecordForm
let Inst{6-10} = RST; let Inst{6-10} = RST;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = RC; let Inst{31} = RC;
} }
class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, string asmstr, InstrItinClass itin,
list<dag> pattern> list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp;
Show All 10 Lines
} }
// This is the same as XForm_base_r3xo, but the first two operands are swapped // This is the same as XForm_base_r3xo, but the first two operands are swapped
// when code is emitted. // when code is emitted.
class XForm_base_r3xo_swapped class XForm_base_r3xo_swapped
<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RA;
bits<5> RST; bits<5> RST;
bits<5> B; bits<5> RB;
bit RC = 0; // set by isRecordForm bit RC = 0; // set by isRecordForm
let Inst{6-10} = RST; let Inst{6-10} = RST;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = RC; let Inst{31} = RC;
} }
class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let RST = 0; let RST = 0;
} }
class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let A = 0; let RA = 0;
let B = 0; let RB = 0;
} }
class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RST; bits<5> RST;
bits<5> A; bits<5> RA;
bits<1> WS; bits<1> WS;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RST; let Inst{6-10} = RST;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{20} = WS; let Inst{20} = WS;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
Show All 12 Linesclass XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
let Pattern = pattern; let Pattern = pattern;
} }
class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
let B = 0; let RB = 0;
let Pattern = pattern; let Pattern = pattern;
} }
class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF; bits<3> BF;
bits<1> L; bits<1> L;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
let Inst{6-8} = BF; let Inst{6-8} = BF;
let Inst{9} = 0; let Inst{9} = 0;
let Inst{10} = L; let Inst{10} = L;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesclass XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
: XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
let L = PPC64; let L = PPC64;
} }
class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF; bits<3> BF;
bits<5> FRA; bits<5> RA;
bits<5> FRB; bits<5> RB;
let Inst{6-8} = BF; let Inst{6-8} = BF;
let Inst{9-10} = 0; let Inst{9-10} = 0;
let Inst{11-15} = FRA; let Inst{11-15} = RA;
let Inst{16-20} = FRB; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
let FRA = 0; let RA = 0;
let Pattern = pattern; let Pattern = pattern;
} }
class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> FRT; bits<5> FRT;
bits<5> FRA; bits<5> FRA;
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Linesclass XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
} }
// [PO RT /// RB XO RC] // [PO RT /// RB XO RC]
class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let A = 0; let RA = 0;
} }
class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
} }
class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Linesclass X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
let Inst{31} = 0; let Inst{31} = 0;
} }
class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let RST = 0; let RST = 0;
let A = 0; let RA = 0;
let B = 0; let RB = 0;
} }
class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let RST = 0; let RST = 0;
let A = 0; let RA = 0;
} }
class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin> string asmstr, InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bit R; bit R;
bit RC = 1; bit RC = 1;
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linesclass X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let A = xo2; let RA = xo2;
} }
class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<3> BF; bits<3> BF;
bits<7> DCMX; bits<7> DCMX;
bits<5> VB; bits<5> VB;
Show All 27 Lines
class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin> string asmstr, InstrItinClass itin>
: XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> {
} }
class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
let FRA = 0; let RA = 0;
let FRB = 0; let RB = 0;
} }
// [PO /// L RA RB XO /] // [PO /// L RA RB XO /]
class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
let BF = 0; let BF = 0;
let Pattern = pattern; let Pattern = pattern;
bit RC = 0; bit RC = 0;
let Inst{31} = RC; let Inst{31} = RC;
} }
// XX*-Form (VSX) // XX*-Form (VSX)
class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<6> XT; bits<6> XT;
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = XT{4-0}; let Inst{6-10} = XT{4-0};
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = XT{5}; let Inst{31} = XT{5};
} }
class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp;
class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let B = 0; let RB = 0;
} }
class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<6> XT; bits<6> XT;
bits<6> XB; bits<6> XB;
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Linesclass XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
let Inst{30} = XB{5}; let Inst{30} = XB{5};
let Inst{31} = XT{5}; let Inst{31} = XT{5};
} }
// DCB_Form - Form X instruction, used for dcb* instructions. // DCB_Form - Form X instruction, used for dcb* instructions.
class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<31, OOL, IOL, asmstr, itin> { : I<31, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = immfield; let Inst{6-10} = immfield;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<31, OOL, IOL, asmstr, itin> { : I<31, OOL, IOL, asmstr, itin> {
bits<5> TH; bits<5> TH;
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = TH; let Inst{6-10} = TH;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
// DSS_Form - Form X instruction, used for altivec dss* instructions. // DSS_Form - Form X instruction, used for altivec dss* instructions.
class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<31, OOL, IOL, asmstr, itin> { : I<31, OOL, IOL, asmstr, itin> {
bits<2> STRM; bits<2> STRM;
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6} = T; let Inst{6} = T;
let Inst{7-8} = 0; let Inst{7-8} = 0;
let Inst{9-10} = STRM; let Inst{9-10} = STRM;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
// 1.7.7 XL-Form // 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
bits<5> bi, bit lk, bits<6> opcode2, dag OOL, bits<5> bi, bit lk, bits<6> opcode2, dag OOL,
dag IOL, string asmstr, InstrItinClass itin, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern> list<dag> pattern>
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
bits<5> RST; bits<5> RST;
bits<21> D_RA; bits<21> addr;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = bo; let Inst{6-10} = bo;
let Inst{11-15} = bi; let Inst{11-15} = bi;
let Inst{16-18} = 0; let Inst{16-18} = 0;
let Inst{19-20} = 0; // Unused (BH) let Inst{19-20} = 0; // Unused (BH)
let Inst{21-30} = xo1; let Inst{21-30} = xo1;
let Inst{31} = lk; let Inst{31} = lk;
let Inst{38-42} = RST; let Inst{38-42} = RST;
let Inst{43-47} = D_RA{20-16}; // Base Register let Inst{43-47} = addr{20-16}; // Base Register
let Inst{48-63} = D_RA{15-0}; // Displacement let Inst{48-63} = addr{15-0}; // Displacement
} }
// 1.7.8 XFX-Form // 1.7.8 XFX-Form
class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RST;
bits<10> SPR; bits<10> SPR;
let Inst{6-10} = RT; let Inst{6-10} = RST;
let Inst{11} = SPR{4}; let Inst{11} = SPR{4};
let Inst{12} = SPR{3}; let Inst{12} = SPR{3};
let Inst{13} = SPR{2}; let Inst{13} = SPR{2};
let Inst{14} = SPR{1}; let Inst{14} = SPR{1};
let Inst{15} = SPR{0}; let Inst{15} = SPR{0};
let Inst{16} = SPR{9}; let Inst{16} = SPR{9};
let Inst{17} = SPR{8}; let Inst{17} = SPR{8};
let Inst{18} = SPR{7}; let Inst{18} = SPR{7};
Show All 19 Linesclass XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<10> Entry; bits<10> imm;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-20} = Entry; let Inst{11-20} = imm;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RST;
bits<8> FXM; bits<8> FXM;
bits<5> rS;
let Inst{6-10} = rS; let Inst{6-10} = RST;
let Inst{11} = 0; let Inst{11} = 0;
let Inst{12-19} = FXM; let Inst{12-19} = FXM;
let Inst{20} = 0; let Inst{20} = 0;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin> InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> ST; bits<5> RST;
bits<8> FXM; bits<8> FXM;
let Inst{6-10} = ST; let Inst{6-10} = RST;
let Inst{11} = 1; let Inst{11} = 1;
let Inst{12-19} = FXM; let Inst{12-19} = FXM;
let Inst{20} = 0; let Inst{20} = 0;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
dag OOL, dag IOL, string asmstr, InstrItinClass itin>
: XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
let SPR = spr;
}
// XFL-Form - MTFSF // XFL-Form - MTFSF
// This is probably 1.7.9, but I don't have the reference that uses this // This is probably 1.7.9, but I don't have the reference that uses this
// numbering scheme... // numbering scheme...
class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag>pattern> InstrItinClass itin, list<dag>pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<8> FM; bits<8> FM;
bits<5> rT; bits<5> RT;
bit RC = 0; // set by isRecordForm bit RC = 0; // set by isRecordForm
let Pattern = pattern; let Pattern = pattern;
let Inst{6} = 0; let Inst{6} = 0;
let Inst{7-14} = FM; let Inst{7-14} = FM;
let Inst{15} = 0; let Inst{15} = 0;
let Inst{16-20} = rT; let Inst{16-20} = RT;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = RC; let Inst{31} = RC;
} }
class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag>pattern> InstrItinClass itin, list<dag>pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bit L; bit L;
Show All 11 Linesclass XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = RC; let Inst{31} = RC;
} }
// 1.7.10 XS-Form - SRADI. // 1.7.10 XS-Form - SRADI.
class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> A; bits<5> RA;
bits<5> RS; bits<5> RS;
bits<6> SH; bits<6> SH;
bit RC = 0; // set by isRecordForm bit RC = 0; // set by isRecordForm
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RS; let Inst{6-10} = RS;
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = SH{4,3,2,1,0}; let Inst{16-20} = SH{4,3,2,1,0};
let Inst{21-29} = xo; let Inst{21-29} = xo;
let Inst{30} = SH{5}; let Inst{30} = SH{5};
let Inst{31} = RC; let Inst{31} = RC;
} }
// 1.7.11 XO-Form // 1.7.11 XO-Form
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Linesclass MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-25} = MB; let Inst{21-25} = MB;
let Inst{26-30} = ME; let Inst{26-30} = ME;
let Inst{31} = RC; let Inst{31} = RC;
} }
class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RA;
bits<5> RS;
bits<5> SH;
bits<5> MB;
bits<5> ME;
let Pattern = pattern;
bit RC = 0; // set by isRecordForm
let Inst{6-10} = RS;
let Inst{11-15} = RA;
let Inst{16-20} = SH;
let Inst{21-25} = MB;
let Inst{26-30} = ME;
let Inst{31} = RC;
} }
// 1.7.14 MD-Form // 1.7.14 MD-Form
class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RA; bits<5> RA;
bits<5> RS; bits<5> RS;
Show All 35 Lines
// E-1 VA-Form // E-1 VA-Form
// VAForm_1 - DACB ordering. // VAForm_1 - DACB ordering.
class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<5> VD; bits<5> RT;
bits<5> VA; bits<5> RA;
bits<5> VC; bits<5> RC;
bits<5> VB; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = VD; let Inst{6-10} = RT;
let Inst{11-15} = VA; let Inst{11-15} = RA;
let Inst{16-20} = VB; let Inst{16-20} = RB;
let Inst{21-25} = VC; let Inst{21-25} = RC;
let Inst{26-31} = xo; let Inst{26-31} = xo;
} }
// VAForm_1a - DABC ordering. // VAForm_1a - DABC ordering.
class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<5> VD; bits<5> RT;
bits<5> VA; bits<5> RA;
bits<5> VB; bits<5> RB;
bits<5> VC; bits<5> RC;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = VD; let Inst{6-10} = RT;
let Inst{11-15} = VA; let Inst{11-15} = RA;
let Inst{16-20} = VB; let Inst{16-20} = RB;
let Inst{21-25} = VC; let Inst{21-25} = RC;
let Inst{26-31} = xo; let Inst{26-31} = xo;
} }
class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<5> VD; bits<5> RT;
bits<5> VA; bits<5> RA;
bits<5> VB; bits<5> RB;
bits<4> SH; bits<4> SH;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = VD; let Inst{6-10} = RT;
let Inst{11-15} = VA; let Inst{11-15} = RA;
let Inst{16-20} = VB; let Inst{16-20} = RB;
let Inst{21} = 0; let Inst{21} = 0;
let Inst{22-25} = SH; let Inst{22-25} = SH;
let Inst{26-31} = xo; let Inst{26-31} = xo;
} }
// E-2 VX-Form // E-2 VX-Form
class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesclass VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Inst{16-20} = VB; let Inst{16-20} = VB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
// e.g. [PO VRT EO VRB XO] // e.g. [PO VRT EO VRB XO]
class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<5> RD; bits<5> VD;
bits<5> VB; bits<5> VB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RD; let Inst{6-10} = VD;
let Inst{11-15} = eo; let Inst{11-15} = eo;
let Inst{16-20} = VB; let Inst{16-20} = VB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrHTM.td

Show All 29 Lines
let Defs = [CR0] in { let Defs = [CR0] in {
def TBEGIN : XForm_htm0 <31, 654, def TBEGIN : XForm_htm0 <31, 654,
(outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>; (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>;
def TEND : XForm_htm1 <31, 686, def TEND : XForm_htm1 <31, 686,
(outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>; (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>;
def TABORT : XForm_base_r3xo <31, 910, def TABORT : XForm_base_r3xo <31, 910,
(outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR, (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,
[]>, isRecordForm { []>, isRecordForm {
let RST = 0; let RST = 0;
let B = 0; let RB = 0;
} }
def TABORTWC : XForm_base_r3xo <31, 782, def TABORTWC : XForm_base_r3xo <31, 782,
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
"tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>, "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm; isRecordForm;
def TABORTWCI : XForm_base_r3xo <31, 846, def TABORTWCI : XForm_base_r3xo <31, 846,
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
"tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>, "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm; isRecordForm;
def TABORTDC : XForm_base_r3xo <31, 814, def TABORTDC : XForm_base_r3xo <31, 814,
(outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
"tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>, "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm; isRecordForm;
def TABORTDCI : XForm_base_r3xo <31, 878, def TABORTDCI : XForm_base_r3xo <31, 878,
(outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
"tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>, "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
isRecordForm; isRecordForm;
def TSR : XForm_htm2 <31, 750, def TSR : XForm_htm2 <31, 750,
(outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>, (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>,
isRecordForm; isRecordForm;
def TRECLAIM : XForm_base_r3xo <31, 942, def TRECLAIM : XForm_base_r3xo <31, 942,
(outs), (ins gprc:$A), "treclaim. $A", (outs), (ins gprc:$RA), "treclaim. $RA",
IIC_SprMTSPR, []>, IIC_SprMTSPR, []>,
isRecordForm { isRecordForm {
let RST = 0; let RST = 0;
let B = 0; let RB = 0;
} }
def TRECHKPT : XForm_base_r3xo <31, 1006, def TRECHKPT : XForm_base_r3xo <31, 1006,
(outs), (ins), "trechkpt.", IIC_SprMTSPR, []>, (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,
isRecordForm { isRecordForm {
let RST = 0; let RST = 0;
let A = 0; let RA = 0;
let B = 0; let RB = 0;
} }
} }
def TCHECK : XForm_htm3 <31, 718, def TCHECK : XForm_htm3 <31, 718,
(outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>; (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>;
// Builtins // Builtins
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 908 Lines • ▼ Show 20 Lines def O : XOForm_3<opcode, xo, 1, OOL, IOL,
[]>, RecFormRel; []>, RecFormRel;
let Defs = [CARRY, XER, CR0] in let Defs = [CARRY, XER, CR0] in
def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL,
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin, !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
[]>, isRecordForm, RecFormRel; []>, isRecordForm, RecFormRel;
} }
} }
multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
let BaseName = asmbase in {
def NAME : MForm_1<opcode, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel;
let Defs = [CR0] in
def _rec : MForm_1<opcode, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
[]>, isRecordForm, RecFormRel;
}
}
multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin, string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> { list<dag> pattern> {
let BaseName = asmbase in { let BaseName = asmbase in {
def NAME : MForm_2<opcode, OOL, IOL, def NAME : MForm_2<opcode, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)), itin, !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
pattern>, RecFormRel; pattern>, RecFormRel;
let Defs = [CR0] in let Defs = [CR0] in
▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(retflag)]>, Requires<[In32BitMode]>; [(retflag)]>, Requires<[In32BitMode]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>; []>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
[]>; []>;
def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
"bcctr 12, $bi, 0", IIC_BrB, []>; "bcctr 12, $BI, 0", IIC_BrB, []>;
def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
"bcctr 4, $bi, 0", IIC_BrB, []>; "bcctr 4, $BI, 0", IIC_BrB, []>;
} }
} }
} }
// Set the float rounding mode. // Set the float rounding mode.
let Uses = [RM], Defs = [RM] in { let Uses = [RM], Defs = [RM] in {
def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
"#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;
Show All 11 Lines
let Defs = [LR] in let Defs = [LR] in
def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,
PPC970_Unit_BRU; PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
hasSideEffects = 0 in { hasSideEffects = 0 in {
let isBarrier = 1 in { let isBarrier = 1 in {
let isPredicable = 1 in let isPredicable = 1 in
def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI),
"b $dst", IIC_BrB, "b $LI", IIC_BrB,
[(br bb:$dst)]>; [(br bb:$LI)]>;
def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI),
"ba $dst", IIC_BrB, []>; "ba $LI", IIC_BrB, []>;
} }
// BCC represents an arbitrary conditional branch on a predicate. // BCC represents an arbitrary conditional branch on a predicate.
// FIXME: should be able to write a pattern for PPCcondbranch, but can't use // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD),
"b${cond:cc}${cond:pm} ${cond:reg}, $dst" "b${cond:cc}${cond:pm} ${cond:reg}, $BD"
/*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>;
def BCC : BCC_class; def BCC : BCC_class;
// The same as BCC, except that it's not a terminator. Used for introducing // The same as BCC, except that it's not a terminator. Used for introducing
// control flow dependency without creating new blocks. // control flow dependency without creating new blocks.
let isTerminator = 0 in def CTRL_DEP : BCC_class; let isTerminator = 0 in def CTRL_DEP : BCC_class;
def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD),
"b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">;
let isReturn = 1, Uses = [LR, RM] in let isReturn = 1, Uses = [LR, RM] in
def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
let Pattern = [(brcond i1:$bi, bb:$dst)] in let Pattern = [(brcond i1:$BI, bb:$BD)] in
def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),
"bc 12, $bi, $dst">; "bc 12, $BI, $BD">;
let Pattern = [(brcond (not i1:$bi), bb:$dst)] in let Pattern = [(brcond (not i1:$BI), bb:$BD)] in
def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),
"bc 4, $bi, $dst">; "bc 4, $BI, $BD">;
let isReturn = 1, Uses = [LR, RM] in { let isReturn = 1, Uses = [LR, RM] in {
def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI),
"bclr 12, $bi, 0", IIC_BrB, []>; "bclr 12, $BI, 0", IIC_BrB, []>;
def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI),
"bclr 4, $bi, 0", IIC_BrB, []>; "bclr 4, $BI, 0", IIC_BrB, []>;
} }
} }
let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
"bdzlr", IIC_BrB, []>; "bdzlr", IIC_BrB, []>;
def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
"bdnzlr", IIC_BrB, []>; "bdnzlr", IIC_BrB, []>;
def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
"bdzlr+", IIC_BrB, []>; "bdzlr+", IIC_BrB, []>;
def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
"bdnzlr+", IIC_BrB, []>; "bdnzlr+", IIC_BrB, []>;
def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
"bdzlr-", IIC_BrB, []>; "bdzlr-", IIC_BrB, []>;
def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
"bdnzlr-", IIC_BrB, []>; "bdnzlr-", IIC_BrB, []>;
} }
let Defs = [CTR], Uses = [CTR] in { let Defs = [CTR], Uses = [CTR] in {
def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
"bdz $dst">; "bdz $BD">;
def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
"bdnz $dst">; "bdnz $BD">;
def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdza $dst">; "bdza $BD">;
def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdnza $dst">; "bdnza $BD">;
def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD),
"bdz+ $dst">; "bdz+ $BD">;
def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD),
"bdnz+ $dst">; "bdnz+ $BD">;
def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdza+ $dst">; "bdza+ $BD">;
def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdnza+ $dst">; "bdnza+ $BD">;
def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD),
"bdz- $dst">; "bdz- $BD">;
def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD),
"bdnz- $dst">; "bdnz- $BD">;
def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdza- $dst">; "bdza- $BD">;
def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD),
"bdnza- $dst">; "bdnza- $BD">;
} }
} }
// The unconditional BCL used by the SjLj setjmp code. // The unconditional BCL used by the SjLj setjmp code.
let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7,
hasSideEffects = 0 in { hasSideEffects = 0 in {
let Defs = [LR], Uses = [RM] in { let Defs = [LR], Uses = [RM] in {
def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD),
"bcl 20, 31, $dst">; "bcl 20, 31, $BD">;
} }
} }
let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
// Convenient aliases for call instructions // Convenient aliases for call instructions
let Uses = [RM] in { let Uses = [RM] in {
def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; // See Pat patterns below. "bl $LI", IIC_BrB, []>; // See Pat patterns below.
def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
"bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI),
"bl $func", IIC_BrB, []>; "bl $LI", IIC_BrB, []>;
def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD),
"b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">;
def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD),
"b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">;
def BCL : BForm_4<16, 12, 0, 1, (outs), def BCL : BForm_4<16, 12, 0, 1, (outs),
(ins crbitrc:$bi, condbrtarget:$dst), (ins crbitrc:$BI, condbrtarget:$BD),
"bcl 12, $bi, $dst">; "bcl 12, $BI, $BD">;
def BCLn : BForm_4<16, 4, 0, 1, (outs), def BCLn : BForm_4<16, 4, 0, 1, (outs),
(ins crbitrc:$bi, condbrtarget:$dst), (ins crbitrc:$BI, condbrtarget:$BD),
"bcl 4, $bi, $dst">; "bcl 4, $BI, $BD">;
def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins calltarget:$func), (outs), (ins calltarget:$LI),
"bl $func\n\tnop", IIC_BrB, []>; "bl $LI\n\tnop", IIC_BrB, []>;
} }
} }
let Uses = [CTR, RM] in { let Uses = [CTR, RM] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl)]>, "bctrl", IIC_BrB, [(PPCbctrl)]>,
Requires<[In32BitMode]>; Requires<[In32BitMode]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
[]>; []>;
def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
"bcctrl 12, $bi, 0", IIC_BrB, []>; "bcctrl 12, $BI, 0", IIC_BrB, []>;
def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
"bcctrl 4, $bi, 0", IIC_BrB, []>; "bcctrl 4, $BI, 0", IIC_BrB, []>;
} }
} }
let Uses = [LR, RM] in { let Uses = [LR, RM] in {
def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
"blrl", IIC_BrB, []>; "blrl", IIC_BrB, []>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
[]>; []>;
def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI),
"bclrl 12, $bi, 0", IIC_BrB, []>; "bclrl 12, $BI, 0", IIC_BrB, []>;
def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI),
"bclrl 4, $bi, 0", IIC_BrB, []>; "bclrl 4, $BI, 0", IIC_BrB, []>;
} }
} }
let Defs = [CTR], Uses = [CTR, RM] in { let Defs = [CTR], Uses = [CTR, RM] in {
def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD),
"bdzl $dst">; "bdzl $BD">;
def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD),
"bdnzl $dst">; "bdnzl $BD">;
def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdzla $dst">; "bdzla $BD">;
def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdnzla $dst">; "bdnzla $BD">;
def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD),
"bdzl+ $dst">; "bdzl+ $BD">;
def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD),
"bdnzl+ $dst">; "bdnzl+ $BD">;
def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdzla+ $dst">; "bdzla+ $BD">;
def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdnzla+ $dst">; "bdnzla+ $BD">;
def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD),
"bdzl- $dst">; "bdzl- $BD">;
def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD),
"bdnzl- $dst">; "bdnzl- $BD">;
def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdzla- $dst">; "bdzla- $BD">;
def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD),
"bdnzla- $dst">; "bdnzla- $BD">;
} }
let Defs = [CTR], Uses = [CTR, LR, RM] in { let Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
"bdzlrl", IIC_BrB, []>; "bdzlrl", IIC_BrB, []>;
def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
"bdnzlrl", IIC_BrB, []>; "bdnzlrl", IIC_BrB, []>;
def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
"bdzlrl+", IIC_BrB, []>; "bdzlrl+", IIC_BrB, []>;
def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
"bdnzlrl+", IIC_BrB, []>; "bdnzlrl+", IIC_BrB, []>;
def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
"bdzlrl-", IIC_BrB, []>; "bdzlrl-", IIC_BrB, []>;
def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
"bdnzlrl-", IIC_BrB, []>; "bdnzlrl-", IIC_BrB, []>;
} }
} }
let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {
// Convenient aliases for call instructions // Convenient aliases for call instructions
let Uses = [RM] in { let Uses = [RM] in {
def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
"bl $func", IIC_BrB, []>; // See Pat patterns below. "bl $LI", IIC_BrB, []>; // See Pat patterns below.
def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
"bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>;
def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins calltarget:$func), (outs), (ins calltarget:$LI),
"bl $func\n\tnop", IIC_BrB, []>; "bl $LI\n\tnop", IIC_BrB, []>;
} }
let Uses = [CTR, RM] in { let Uses = [CTR, RM] in {
let isPredicable = 1 in let isPredicable = 1 in
def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>, "bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
Requires<[In32BitMode]>; Requires<[In32BitMode]>;
} }
} }
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def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
"#TC_RETURNr $dst $offset", "#TC_RETURNr $dst $offset",
[]>; []>;
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in {
def BCTRL_LWZinto_toc: def BCTRL_LWZinto_toc:
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
(ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
[(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
} }
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in {
def BCTRL_LWZinto_toc_RM: def BCTRL_LWZinto_toc_RM:
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
(ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
[(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
} }
let isCodeGenOnly = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, hasSideEffects = 0 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>, Requires<[In32BitMode]>; []>, Requires<[In32BitMode]>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI),
"b $dst", IIC_BrB, "b $LI", IIC_BrB,
[]>; []>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI),
"ba $dst", IIC_BrB, "ba $LI", IIC_BrB,
[]>; []>;
} }
// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp // While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
// is not. // is not.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
let Defs = [CTR] in let Defs = [CTR] in
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// from emitting it. // from emitting it.
let isBranch = 1, isTerminator = 1, Size = 0 in { let isBranch = 1, isTerminator = 1, Size = 0 in {
def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst),
"#EH_SjLj_Setup\t$dst", []>; "#EH_SjLj_Setup\t$dst", []>;
} }
// System call. // System call.
let PPC970_Unit = 7 in { let PPC970_Unit = 7 in {
def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), def SC : SCForm<17, 1, (outs), (ins i32imm:$LEV),
"sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>;
} }
// Branch history rolling buffer. // Branch history rolling buffer.
def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
[(PPCclrbhrb)]>, [(PPCclrbhrb)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
// The $dmy argument used for MFBHRBE is not needed; however, including // The $dmy argument used for MFBHRBE is not needed; however, including
// it avoids automatic generation of PPCFastISel::fastEmit_i(), which // it avoids automatic generation of PPCFastISel::fastEmit_i(), which
// interferes with necessary special handling (see PPCFastISel.cpp). // interferes with necessary special handling (see PPCFastISel.cpp).
def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT),
(ins u10imm:$imm, u10imm:$dmy), (ins u10imm:$imm, u10imm:$dmy),
"mfbhrbe $rD, $imm", IIC_BrB, "mfbhrbe $RT, $imm", IIC_BrB,
[(set i32:$rD, [(set i32:$RT,
(PPCmfbhrbe imm:$imm, imm:$dmy))]>, (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
PPC970_DGroup_First; PPC970_DGroup_First;
def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S",
IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, IIC_BrB, [(PPCrfebb (i32 imm:$S))]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def : InstAlias<"rfebb", (RFEBB 1)>; def : InstAlias<"rfebb", (RFEBB 1)>;
// DCB* instructions. // DCB* instructions.
def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr",
IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr",
IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr",
IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr",
IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr",
IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr),
"dcbf $dst, $TH", IIC_LdStDCBF, []>, "dcbf $addr, $TH", IIC_LdStDCBF, []>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
"dcbt $dst, $TH", IIC_LdStDCBF, []>, "dcbt $addr, $TH", IIC_LdStDCBF, []>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
"dcbtst $dst, $TH", IIC_LdStDCBF, []>, "dcbtst $addr, $TH", IIC_LdStDCBF, []>,
PPC970_DGroup_Single; PPC970_DGroup_Single;
} // hasSideEffects = 0 } // hasSideEffects = 0
def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
"icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>;
def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
"icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;
def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
"icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;
def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
"icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>;
def : Pat<(int_ppc_dcbt xoaddr:$dst), def : Pat<(int_ppc_dcbt xoaddr:$dst),
(DCBT 0, xoaddr:$dst)>; (DCBT 0, xoaddr:$dst)>;
def : Pat<(int_ppc_dcbtst xoaddr:$dst), def : Pat<(int_ppc_dcbtst xoaddr:$dst),
(DCBTST 0, xoaddr:$dst)>; (DCBTST 0, xoaddr:$dst)>;
def : Pat<(int_ppc_dcbf xoaddr:$dst), def : Pat<(int_ppc_dcbf xoaddr:$dst),
(DCBF 0, xoaddr:$dst)>; (DCBF 0, xoaddr:$dst)>;
def : Pat<(int_ppc_icbt xoaddr:$dst), def : Pat<(int_ppc_icbt xoaddr:$dst),
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def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new),
(ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>;
def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new),
(ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>;
// Instructions to support atomic operations // Instructions to support atomic operations
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lbarx $rD, $src", IIC_LdStLWARX, []>, "lbarx $RST, $addr", IIC_LdStLWARX, []>,
Requires<[HasPartwordAtomics]>; Requires<[HasPartwordAtomics]>;
def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lharx $rD, $src", IIC_LdStLWARX, []>, "lharx $RST, $addr", IIC_LdStLWARX, []>,
Requires<[HasPartwordAtomics]>; Requires<[HasPartwordAtomics]>;
def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwarx $rD, $src", IIC_LdStLWARX, []>; "lwarx $RST, $addr", IIC_LdStLWARX, []>;
// Instructions to support lock versions of atomics // Instructions to support lock versions of atomics
// (EH=1 - see Power ISA 2.07 Book II 4.4.2) // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm,
Requires<[HasPartwordAtomics]>; Requires<[HasPartwordAtomics]>;
def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm,
Requires<[HasPartwordAtomics]>; Requires<[HasPartwordAtomics]>;
def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm;
// The atomic instructions use the destination register as well as the next one // The atomic instructions use the destination register as well as the next one
// or two registers in order (modulo 31). // or two registers in order (modulo 31).
let hasExtraSrcRegAllocReq = 1 in let hasExtraSrcRegAllocReq = 1 in
def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB),
"lwat $rD, $rA, $FC", IIC_LdStLoad>, "lwat $RST, $RA, $RB", IIC_LdStLoad>,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
} }
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbcx. $rS, $dst", IIC_LdStSTWCX, []>, "stbcx. $RST, $addr", IIC_LdStSTWCX, []>,
isRecordForm, Requires<[HasPartwordAtomics]>; isRecordForm, Requires<[HasPartwordAtomics]>;
def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthcx. $rS, $dst", IIC_LdStSTWCX, []>, "sthcx. $RST, $addr", IIC_LdStSTWCX, []>,
isRecordForm, Requires<[HasPartwordAtomics]>; isRecordForm, Requires<[HasPartwordAtomics]>;
def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm;
} }
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
"stwat $rS, $rA, $FC", IIC_LdStStore>, "stwat $RST, $RA, $RB", IIC_LdStStore>,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm, variable_ops), def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops),
"twi $to, $rA, $imm", IIC_IntTrapW, []>; "twi $RST, $RA, $D", IIC_IntTrapW, []>;
def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB, variable_ops), def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops),
"tw $to, $rA, $rB", IIC_IntTrapW, []>; "tw $RST, $RA, $RB", IIC_IntTrapW, []>;
def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm, variable_ops), def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops),
"tdi $to, $rA, $imm", IIC_IntTrapD, []>; "tdi $RST, $RA, $D", IIC_IntTrapD, []>;
def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB, variable_ops), def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops),
"td $to, $rA, $rB", IIC_IntTrapD, []>; "td $RST, $RA, $RB", IIC_IntTrapD, []>;
def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),
"popcntb $rA, $rS", IIC_IntGeneral, "popcntb $RA, $RST", IIC_IntGeneral,
[(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PPC32 Load Instructions. // PPC32 Load Instructions.
// //
// Unindexed (r+i) Loads. // Unindexed (r+i) Loads.
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), def LBZ : DForm_1<34, (outs gprc:$RST), (ins memri:$addr),
"lbz $rD, $src", IIC_LdStLoad, "lbz $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64, [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), def LHA : DForm_1<42, (outs gprc:$RST), (ins memri:$addr),
"lha $rD, $src", IIC_LdStLHA, "lha $RST, $addr", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 DForm:$src))]>, [(set i32:$RST, (sextloadi16 DForm:$addr))]>,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), def LHZ : DForm_1<40, (outs gprc:$RST), (ins memri:$addr),
"lhz $rD, $src", IIC_LdStLoad, "lhz $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64, [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), def LWZ : DForm_1<32, (outs gprc:$RST), (ins memri:$addr),
"lwz $rD, $src", IIC_LdStLoad, "lwz $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (load DForm:$src))]>, ZExt32To64; [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), def LFS : DForm_1<48, (outs f4rc:$RST), (ins memri:$addr),
"lfs $rD, $src", IIC_LdStLFD, "lfs $RST, $addr", IIC_LdStLFD,
[(set f32:$rD, (load DForm:$src))]>; [(set f32:$RST, (load DForm:$addr))]>;
def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), def LFD : DForm_1<50, (outs f8rc:$RST), (ins memri:$addr),
"lfd $rD, $src", IIC_LdStLFD, "lfd $RST, $addr", IIC_LdStLFD,
[(set f64:$rD, (load DForm:$src))]>; [(set f64:$RST, (load DForm:$addr))]>;
} }
// Unindexed (r+i) Loads with Update (preinc). // Unindexed (r+i) Loads with Update (preinc).
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lbzu $rD, $addr", IIC_LdStLoadUpd, "lbzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lhau $rD, $addr", IIC_LdStLHAU, "lhau $RST, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lhzu $rD, $addr", IIC_LdStLoadUpd, "lhzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lwzu $rD, $addr", IIC_LdStLoadUpd, "lwzu $RST, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lfsu $rD, $addr", IIC_LdStLFDU, "lfsu $RST, $addr", IIC_LdStLFDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lfdu $rD, $addr", IIC_LdStLFDU, "lfdu $RST, $addr", IIC_LdStLFDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
} }
// Indexed (r+r) Loads with Update (preinc). // Indexed (r+r) Loads with Update (preinc).
def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lbzux $rD, $addr", IIC_LdStLoadUpdX, "lbzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lhaux $rD, $addr", IIC_LdStLHAUX, "lhaux $RST, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lhzux $rD, $addr", IIC_LdStLoadUpdX, "lhzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lwzux $rD, $addr", IIC_LdStLoadUpdX, "lwzux $RST, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lfsux $rD, $addr", IIC_LdStLFDUX, "lfsux $RST, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins (memrr $RA, $RB):$addr),
"lfdux $rD, $addr", IIC_LdStLFDUX, "lfdux $RST, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
} }
} }
} }
// Indexed (r+r) Loads. // Indexed (r+r) Loads.
// //
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lbzx $rD, $src", IIC_LdStLoad, "lbzx $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64, [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lhax $rD, $src", IIC_LdStLHA, "lhax $RST, $addr", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 XForm:$src))]>, [(set i32:$RST, (sextloadi16 XForm:$addr))]>,
PPC970_DGroup_Cracked, SExt32To64; PPC970_DGroup_Cracked, SExt32To64;
def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lhzx $rD, $src", IIC_LdStLoad, "lhzx $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (zextloadi16 XForm:$src))]>, ZExt32To64, [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64,
SExt32To64; SExt32To64;
def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwzx $rD, $src", IIC_LdStLoad, "lwzx $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (load XForm:$src))]>, ZExt32To64; [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64;
def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lhbrx $rD, $src", IIC_LdStLoad, "lhbrx $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>, ZExt32To64; [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64;
def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwbrx $rD, $src", IIC_LdStLoad, "lwbrx $RST, $addr", IIC_LdStLoad,
[(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>, ZExt32To64; [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr),
"lfsx $frD, $src", IIC_LdStLFD, "lfsx $RST, $addr", IIC_LdStLFD,
[(set f32:$frD, (load XForm:$src))]>; [(set f32:$RST, (load XForm:$addr))]>;
def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lfdx $frD, $src", IIC_LdStLFD, "lfdx $RST, $addr", IIC_LdStLFD,
[(set f64:$frD, (load XForm:$src))]>; [(set f64:$RST, (load XForm:$addr))]>;
def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lfiwax $frD, $src", IIC_LdStLFD, "lfiwax $RST, $addr", IIC_LdStLFD,
[(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>;
def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lfiwzx $frD, $src", IIC_LdStLFD, "lfiwzx $RST, $addr", IIC_LdStLFD,
[(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>;
} }
} }
// Load Multiple // Load Multiple
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), def LMW : DForm_1<46, (outs gprc:$RST), (ins memri:$src),
"lmw $rD, $src", IIC_LdStLMW, []>; "lmw $RST, $src", IIC_LdStLMW, []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PPC32 Store Instructions. // PPC32 Store Instructions.
// //
// Unindexed (r+i) Stores. // Unindexed (r+i) Stores.
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), def STB : DForm_1<38, (outs), (ins gprc:$RST, memri:$dst),
"stb $rS, $dst", IIC_LdStStore, "stb $RST, $dst", IIC_LdStStore,
[(truncstorei8 i32:$rS, DForm:$dst)]>; [(truncstorei8 i32:$RST, DForm:$dst)]>;
def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), def STH : DForm_1<44, (outs), (ins gprc:$RST, memri:$dst),
"sth $rS, $dst", IIC_LdStStore, "sth $RST, $dst", IIC_LdStStore,
[(truncstorei16 i32:$rS, DForm:$dst)]>; [(truncstorei16 i32:$RST, DForm:$dst)]>;
def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), def STW : DForm_1<36, (outs), (ins gprc:$RST, memri:$dst),
"stw $rS, $dst", IIC_LdStStore, "stw $RST, $dst", IIC_LdStStore,
[(store i32:$rS, DForm:$dst)]>; [(store i32:$RST, DForm:$dst)]>;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), def STFS : DForm_1<52, (outs), (ins f4rc:$RST, memri:$dst),
"stfs $rS, $dst", IIC_LdStSTFD, "stfs $RST, $dst", IIC_LdStSTFD,
[(store f32:$rS, DForm:$dst)]>; [(store f32:$RST, DForm:$dst)]>;
def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), def STFD : DForm_1<54, (outs), (ins f8rc:$RST, memri:$dst),
"stfd $rS, $dst", IIC_LdStSTFD, "stfd $RST, $dst", IIC_LdStSTFD,
[(store f64:$rS, DForm:$dst)]>; [(store f64:$RST, DForm:$dst)]>;
} }
} }
// Unindexed (r+i) Stores with Update (preinc). // Unindexed (r+i) Stores with Update (preinc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
"stbu $rS, $dst", IIC_LdStSTU, []>, "stbu $RST, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
"sthu $rS, $dst", IIC_LdStSTU, []>, "sthu $RST, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst),
"stwu $rS, $dst", IIC_LdStSTU, []>, "stwu $RST, $dst", IIC_LdStSTU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, memri:$dst),
"stfsu $rS, $dst", IIC_LdStSTFDU, []>, "stfsu $RST, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, memri:$dst),
"stfdu $rS, $dst", IIC_LdStSTFDU, []>, "stfdu $RST, $dst", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
} }
} }
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STBU $rS, iaddroff:$ptroff, $ptrreg)>; (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STHU $rS, iaddroff:$ptroff, $ptrreg)>; (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STWU $rS, iaddroff:$ptroff, $ptrreg)>; (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STFSU $rS, iaddroff:$ptroff, $ptrreg)>; (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
(STFDU $rS, iaddroff:$ptroff, $ptrreg)>; (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
// Indexed (r+r) Stores. // Indexed (r+r) Stores.
let PPC970_Unit = 2 in { let PPC970_Unit = 2 in {
def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbx $rS, $dst", IIC_LdStStore, "stbx $RST, $addr", IIC_LdStStore,
[(truncstorei8 i32:$rS, XForm:$dst)]>, [(truncstorei8 i32:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthx $rS, $dst", IIC_LdStStore, "sthx $RST, $addr", IIC_LdStStore,
[(truncstorei16 i32:$rS, XForm:$dst)]>, [(truncstorei16 i32:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwx $rS, $dst", IIC_LdStStore, "stwx $RST, $addr", IIC_LdStStore,
[(store i32:$rS, XForm:$dst)]>, [(store i32:$RST, XForm:$addr)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthbrx $rS, $dst", IIC_LdStStore, "sthbrx $RST, $addr", IIC_LdStStore,
[(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwbrx $rS, $dst", IIC_LdStStore, "stwbrx $RST, $addr", IIC_LdStStore,
[(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfiwx $frS, $dst", IIC_LdStSTFD, "stfiwx $RST, $addr", IIC_LdStSTFD,
[(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>;
def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr),
"stfsx $frS, $dst", IIC_LdStSTFD, "stfsx $RST, $addr", IIC_LdStSTFD,
[(store f32:$frS, XForm:$dst)]>; [(store f32:$RST, XForm:$addr)]>;
def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfdx $frS, $dst", IIC_LdStSTFD, "stfdx $RST, $addr", IIC_LdStSTFD,
[(store f64:$frS, XForm:$dst)]>; [(store f64:$RST, XForm:$addr)]>;
} }
} }
// Indexed (r+r) Stores with Update (preinc). // Indexed (r+r) Stores with Update (preinc).
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbux $rS, $dst", IIC_LdStSTUX, []>, "stbux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthux $rS, $dst", IIC_LdStSTUX, []>, "sthux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwux $rS, $dst", IIC_LdStSTUX, []>, "stwux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),
(ins f4rc:$rS, memrr:$dst), (ins f4rc:$RST, (memrr $RA, $RB):$addr),
"stfsux $rS, $dst", IIC_LdStSTFDU, []>, "stfsux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),
(ins f8rc:$rS, memrr:$dst), (ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfdux $rS, $dst", IIC_LdStSTFDU, []>, "stfdux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, RegConstraint<"$addr.ptrreg = $ea_res">,
NoEncode<"$ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
} }
// Patterns to match the pre-inc stores. We can't put the patterns on // Patterns to match the pre-inc stores. We can't put the patterns on
// the instruction definitions directly as ISel wants the address base // the instruction definitions directly as ISel wants the address base
// and offset to be separate operands, not a single complex operand. // and offset to be separate operands, not a single complex operand.
def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STBUX $rS, $ptrreg, $ptroff)>; (STBUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STHUX $rS, $ptrreg, $ptroff)>; (STHUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STWUX $rS, $ptrreg, $ptroff)>; (STWUX $rS, $ptrreg, $ptroff)>;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STFSUX $rS, $ptrreg, $ptroff)>; (STFSUX $rS, $ptrreg, $ptroff)>;
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STFDUX $rS, $ptrreg, $ptroff)>; (STFDUX $rS, $ptrreg, $ptroff)>;
} }
// Store Multiple // Store Multiple
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), def STMW : DForm_1<47, (outs), (ins gprc:$RST, memri:$dst),
"stmw $rS, $dst", IIC_LdStLMW, []>; "stmw $RST, $dst", IIC_LdStLMW, []>;
def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L),
"sync $L", IIC_LdStSync, []>; "sync $L", IIC_LdStSync, []>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MSYNC : XForm_24_sync<31, 598, (outs), (ins), def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
"msync", IIC_LdStSync, []> { "msync", IIC_LdStSync, []> {
let L = 0; let L = 0;
Show All 18 Lines
def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; def : Pat<(int_ppc_eieio), (PseudoEIEIO)>;
def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PPC32 Arithmetic Instructions. // PPC32 Arithmetic Instructions.
// //
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
"addi $rD, $rA, $imm", IIC_IntSimple, "addi $RST, $RA, $D", IIC_IntSimple,
[(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>;
let BaseName = "addic" in { let BaseName = "addic" in {
let Defs = [CARRY] in let Defs = [CARRY] in
def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"addic $rD, $rA, $imm", IIC_IntGeneral, "addic $RST, $RA, $D", IIC_IntGeneral,
[(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>,
RecFormRel, PPC970_DGroup_Cracked; RecFormRel, PPC970_DGroup_Cracked;
let Defs = [CARRY, CR0] in let Defs = [CARRY, CR0] in
def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"addic. $rD, $rA, $imm", IIC_IntGeneral, "addic. $RST, $RA, $D", IIC_IntGeneral,
[]>, isRecordForm, RecFormRel; []>, isRecordForm, RecFormRel;
} }
def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D),
"addis $rD, $rA, $imm", IIC_IntSimple, "addis $RST, $RA, $D", IIC_IntSimple,
[(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
"la $rD, $sym($rA)", IIC_IntGeneral, "la $RST, $D($RA)", IIC_IntGeneral,
[(set i32:$rD, (add i32:$rA, [(set i32:$RST, (add i32:$RA,
(PPClo tglobaladdr:$sym, 0)))]>; (PPClo tglobaladdr:$D, 0)))]>;
def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"mulli $rD, $rA, $imm", IIC_IntMulLI, "mulli $RST, $RA, $D", IIC_IntMulLI,
[(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>;
let Defs = [CARRY] in let Defs = [CARRY] in
def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
"subfic $rD, $rA, $imm", IIC_IntGeneral, "subfic $RST, $RA, $D", IIC_IntGeneral,
[(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D),
"li $rD, $imm", IIC_IntSimple, "li $RST, $D", IIC_IntSimple,
[(set i32:$rD, imm32SExt16:$imm)]>, SExt32To64; [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64;
def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D),
"lis $rD, $imm", IIC_IntSimple, "lis $RST, $D", IIC_IntSimple,
[(set i32:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64; [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64;
} }
} }
def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
let Defs = [CR0] in { let Defs = [CR0] in {
def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"andi. $dst, $src1, $src2", IIC_IntGeneral, "andi. $RA, $RST, $D", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>,
isRecordForm, ZExt32To64, SExt32To64; isRecordForm, ZExt32To64, SExt32To64;
def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"andis. $dst, $src1, $src2", IIC_IntGeneral, "andis. $RA, $RST, $D", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>,
isRecordForm, ZExt32To64; isRecordForm, ZExt32To64;
} }
def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"ori $dst, $src1, $src2", IIC_IntSimple, "ori $RA, $RST, $D", IIC_IntSimple,
[(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>;
def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"oris $dst, $src1, $src2", IIC_IntSimple, "oris $RA, $RST, $D", IIC_IntSimple,
[(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>;
def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"xori $dst, $src1, $src2", IIC_IntSimple, "xori $RA, $RST, $D", IIC_IntSimple,
[(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>;
def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
"xoris $dst, $src1, $src2", IIC_IntSimple, "xoris $RA, $RST, $D", IIC_IntSimple,
[(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>;
def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
[]>; []>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
// The POWER6 and POWER7 have special group-terminating nops. // The POWER6 and POWER7 have special group-terminating nops.
def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
"ori 1, 1, 0", IIC_IntSimple, []>; "ori 1, 1, 0", IIC_IntSimple, []>;
def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
"ori 2, 2, 0", IIC_IntSimple, []>; "ori 2, 2, 0", IIC_IntSimple, []>;
} }
let isCompare = 1, hasSideEffects = 0 in { let isCompare = 1, hasSideEffects = 0 in {
def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D),
"cmpwi $crD, $rA, $imm", IIC_IntCompare>; "cmpwi $BF, $RA, $D", IIC_IntCompare>;
def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D),
"cmplwi $dst, $src1, $src2", IIC_IntCompare>; "cmplwi $BF, $RA, $D", IIC_IntCompare>;
def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF),
(ins u1imm:$L, gprc:$rA, gprc:$rB), (ins u1imm:$L, gprc:$RA, gprc:$RB),
"cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>,
Requires<[IsISA3_0]>; Requires<[IsISA3_0]>;
} }
} }
let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
let isCommutable = 1 in { let isCommutable = 1 in {
defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"nand", "$rA, $rS, $rB", IIC_IntSimple, "nand", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>;
defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"and", "$rA, $rS, $rB", IIC_IntSimple, "and", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (and i32:$rS, i32:$rB))]>; [(set i32:$RA, (and i32:$RST, i32:$RB))]>;
} // isCommutable } // isCommutable
defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"andc", "$rA, $rS, $rB", IIC_IntSimple, "andc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"or", "$rA, $rS, $rB", IIC_IntSimple, "or", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (or i32:$rS, i32:$rB))]>; [(set i32:$RA, (or i32:$RST, i32:$RB))]>;
defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"nor", "$rA, $rS, $rB", IIC_IntSimple, "nor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>;
} // isCommutable } // isCommutable
defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"orc", "$rA, $rS, $rB", IIC_IntSimple, "orc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"eqv", "$rA, $rS, $rB", IIC_IntSimple, "eqv", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>;
defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"xor", "$rA, $rS, $rB", IIC_IntSimple, "xor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$rA, (xor i32:$rS, i32:$rB))]>; [(set i32:$RA, (xor i32:$RST, i32:$RB))]>;
} // isCommutable } // isCommutable
defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"slw", "$rA, $rS, $rB", IIC_IntGeneral, "slw", "$RA, $RST, $RB", IIC_IntGeneral,
[(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>, ZExt32To64; [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64;
defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"srw", "$rA, $rS, $rB", IIC_IntGeneral, "srw", "$RA, $RST, $RB", IIC_IntGeneral,
[(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>, ZExt32To64; [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64;
defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"sraw", "$rA, $rS, $rB", IIC_IntShift, "sraw", "$RA, $RST, $RB", IIC_IntShift,
[(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>, SExt32To64; [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64;
} }
def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
def : InstAlias<"nop", (ORI R0, R0, 0)>; def : InstAlias<"nop", (ORI R0, R0, 0)>;
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB),
"srawi", "$rA, $rS, $SH", IIC_IntShift, "srawi", "$RA, $RST, $RB", IIC_IntShift,
[(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>, [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>,
SExt32To64; SExt32To64;
defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST),
"cntlzw", "$rA, $rS", IIC_IntGeneral, "cntlzw", "$RA, $RST", IIC_IntGeneral,
[(set i32:$rA, (ctlz i32:$rS))]>, ZExt32To64; [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64;
defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST),
"cnttzw", "$rA, $rS", IIC_IntGeneral, "cnttzw", "$RA, $RST", IIC_IntGeneral,
[(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>, [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>,
ZExt32To64; ZExt32To64;
defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST),
"extsb", "$rA, $rS", IIC_IntSimple, "extsb", "$RA, $RST", IIC_IntSimple,
[(set i32:$rA, (sext_inreg i32:$rS, i8))]>, SExt32To64; [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64;
defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST),
"extsh", "$rA, $rS", IIC_IntSimple, "extsh", "$RA, $RST", IIC_IntSimple,
[(set i32:$rA, (sext_inreg i32:$rS, i16))]>, SExt32To64; [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64;
let isCommutable = 1 in let isCommutable = 1 in
def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"cmpb $rA, $rS, $rB", IIC_IntGeneral, "cmpb $RA, $RST, $RB", IIC_IntGeneral,
[(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>;
} }
let isCompare = 1, hasSideEffects = 0 in { let isCompare = 1, hasSideEffects = 0 in {
def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB),
"cmpw $crD, $rA, $rB", IIC_IntCompare>; "cmpw $BF, $RA, $RB", IIC_IntCompare>;
def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB),
"cmplw $crD, $rA, $rB", IIC_IntCompare>; "cmplw $BF, $RA, $RB", IIC_IntCompare>;
} }
} }
let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations.
let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in {
def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>; "fcmpu $BF, $RA, $RB", IIC_FPCompare>;
def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>; "fcmpo $BF, $RA, $RB", IIC_FPCompare>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>; "fcmpu $BF, $RA, $RB", IIC_FPCompare>;
def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>; "fcmpo $BF, $RA, $RB", IIC_FPCompare>;
} }
} }
def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
"ftdiv $crD, $fA, $fB", IIC_FPCompare>; "ftdiv $BF, $RA, $RB", IIC_FPCompare>;
def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB),
"ftsqrt $crD, $fB", IIC_FPCompare, "ftsqrt $BF, $RB", IIC_FPCompare,
[(set i32:$crD, (PPCftsqrt f64:$fB))]>; [(set i32:$BF, (PPCftsqrt f64:$RB))]>;
let mayRaiseFPException = 1, hasSideEffects = 0 in { let mayRaiseFPException = 1, hasSideEffects = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB),
"frin", "$frD, $frB", IIC_FPGeneral, "frin", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (any_fround f64:$frB))]>; [(set f64:$RST, (any_fround f64:$RB))]>;
defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB),
"frin", "$frD, $frB", IIC_FPGeneral, "frin", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (any_fround f32:$frB))]>; [(set f32:$RST, (any_fround f32:$RB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB),
"frip", "$frD, $frB", IIC_FPGeneral, "frip", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (any_fceil f64:$frB))]>; [(set f64:$RST, (any_fceil f64:$RB))]>;
defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB),
"frip", "$frD, $frB", IIC_FPGeneral, "frip", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (any_fceil f32:$frB))]>; [(set f32:$RST, (any_fceil f32:$RB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB),
"friz", "$frD, $frB", IIC_FPGeneral, "friz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (any_ftrunc f64:$frB))]>; [(set f64:$RST, (any_ftrunc f64:$RB))]>;
defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB),
"friz", "$frD, $frB", IIC_FPGeneral, "friz", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (any_ftrunc f32:$frB))]>; [(set f32:$RST, (any_ftrunc f32:$RB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB),
"frim", "$frD, $frB", IIC_FPGeneral, "frim", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (any_ffloor f64:$frB))]>; [(set f64:$RST, (any_ffloor f64:$RB))]>;
defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB),
"frim", "$frD, $frB", IIC_FPGeneral, "frim", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (any_ffloor f32:$frB))]>; [(set f32:$RST, (any_ffloor f32:$RB))]>;
} }
let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in {
defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiw", "$frD, $frB", IIC_FPGeneral, "fctiw", "$RST, $RB", IIC_FPGeneral,
[]>; []>;
defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiwu", "$frD, $frB", IIC_FPGeneral, "fctiwu", "$RST, $RB", IIC_FPGeneral,
[]>; []>;
defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB),
"fctiwz", "$frD, $frB", IIC_FPGeneral, "fctiwz", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>;
defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB),
"frsp", "$frD, $frB", IIC_FPGeneral, "frsp", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (any_fpround f64:$frB))]>; [(set f32:$RST, (any_fpround f64:$RB))]>;
defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB),
"fsqrt", "$frD, $frB", IIC_FPSqrtD, "fsqrt", "$RST, $RB", IIC_FPSqrtD,
[(set f64:$frD, (any_fsqrt f64:$frB))]>; [(set f64:$RST, (any_fsqrt f64:$RB))]>;
defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB),
"fsqrts", "$frD, $frB", IIC_FPSqrtS, "fsqrts", "$RST, $RB", IIC_FPSqrtS,
[(set f32:$frD, (any_fsqrt f32:$frB))]>; [(set f32:$RST, (any_fsqrt f32:$RB))]>;
} }
} }
def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>;
/// Note that FMR is defined as pseudo-ops on the PPC970 because they are /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
/// often coalesced away and we don't want the dispatch group builder to think /// often coalesced away and we don't want the dispatch group builder to think
/// that they will fill slots (which could cause the load of a LSU reject to /// that they will fill slots (which could cause the load of a LSU reject to
/// sneak into a d-group with a store). /// sneak into a d-group with a store).
let hasSideEffects = 0, Predicates = [HasFPU] in let hasSideEffects = 0, Predicates = [HasFPU] in
defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB),
"fmr", "$frD, $frB", IIC_FPGeneral, "fmr", "$RST, $RB", IIC_FPGeneral,
[]>, // (set f32:$frD, f32:$frB) []>, // (set f32:$RST, f32:$RB)
PPC970_Unit_Pseudo; PPC970_Unit_Pseudo;
let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations.
// These are artificially split into two different forms, for 4/8 byte FP. // These are artificially split into two different forms, for 4/8 byte FP.
defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB),
"fabs", "$frD, $frB", IIC_FPGeneral, "fabs", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (fabs f32:$frB))]>; [(set f32:$RST, (fabs f32:$RB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB),
"fabs", "$frD, $frB", IIC_FPGeneral, "fabs", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (fabs f64:$frB))]>; [(set f64:$RST, (fabs f64:$RB))]>;
defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB),
"fnabs", "$frD, $frB", IIC_FPGeneral, "fnabs", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (fneg (fabs f32:$frB)))]>; [(set f32:$RST, (fneg (fabs f32:$RB)))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB),
"fnabs", "$frD, $frB", IIC_FPGeneral, "fnabs", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (fneg (fabs f64:$frB)))]>; [(set f64:$RST, (fneg (fabs f64:$RB)))]>;
defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB),
"fneg", "$frD, $frB", IIC_FPGeneral, "fneg", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (fneg f32:$frB))]>; [(set f32:$RST, (fneg f32:$RB))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB),
"fneg", "$frD, $frB", IIC_FPGeneral, "fneg", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (fneg f64:$frB))]>; [(set f64:$RST, (fneg f64:$RB))]>;
defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB),
"fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral,
[(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral,
[(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>;
// Reciprocal estimates. // Reciprocal estimates.
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB),
"fre", "$frD, $frB", IIC_FPGeneral, "fre", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCfre f64:$frB))]>; [(set f64:$RST, (PPCfre f64:$RB))]>;
defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB),
"fres", "$frD, $frB", IIC_FPGeneral, "fres", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (PPCfre f32:$frB))]>; [(set f32:$RST, (PPCfre f32:$RB))]>;
defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB),
"frsqrte", "$frD, $frB", IIC_FPGeneral, "frsqrte", "$RST, $RB", IIC_FPGeneral,
[(set f64:$frD, (PPCfrsqrte f64:$frB))]>; [(set f64:$RST, (PPCfrsqrte f64:$RB))]>;
defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB),
"frsqrtes", "$frD, $frB", IIC_FPGeneral, "frsqrtes", "$RST, $RB", IIC_FPGeneral,
[(set f32:$frD, (PPCfrsqrte f32:$frB))]>; [(set f32:$RST, (PPCfrsqrte f32:$RB))]>;
} }
} }
// XL-Form instructions. condition register logical ops. // XL-Form instructions. condition register logical ops.
// //
let hasSideEffects = 0 in let hasSideEffects = 0 in
def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
"mcrf $BF, $BFA", IIC_BrMCR>, "mcrf $BF, $BFA", IIC_BrMCR>,
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def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
(ins crbitrc:$CRA, crbitrc:$CRB), (ins crbitrc:$CRA, crbitrc:$CRB),
"crorc $CRD, $CRA, $CRB", IIC_BrCR, "crorc $CRD, $CRA, $CRB", IIC_BrCR,
[(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins),
"creqv $dst, $dst, $dst", IIC_BrCR, "creqv $CRD, $CRD, $CRD", IIC_BrCR,
[(set i1:$dst, 1)]>; [(set i1:$CRD, 1)]>;
def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins),
"crxor $dst, $dst, $dst", IIC_BrCR, "crxor $CRD, $CRD, $CRD", IIC_BrCR,
[(set i1:$dst, 0)]>; [(set i1:$CRD, 0)]>;
} }
let Defs = [CR1EQ], CRD = 6 in { let Defs = [CR1EQ], CRD = 6 in {
def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
"creqv 6, 6, 6", IIC_BrCR, "creqv 6, 6, 6", IIC_BrCR,
[(PPCcr6set)]>; [(PPCcr6set)]>;
def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
"crxor 6, 6, 6", IIC_BrCR, "crxor 6, 6, 6", IIC_BrCR,
[(PPCcr6unset)]>; [(PPCcr6unset)]>;
} }
} }
// XFX-Form instructions. Instructions that deal with SPRs. // XFX-Form instructions. Instructions that deal with SPRs.
// //
def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR),
"mfspr $RT, $SPR", IIC_SprMFSPR>; "mfspr $RST, $SPR", IIC_SprMFSPR>;
def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST),
"mtspr $SPR, $RT", IIC_SprMTSPR>; "mtspr $SPR, $RST", IIC_SprMTSPR>;
def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR),
"mftb $RT, $SPR", IIC_SprMFTB>; "mftb $RST, $SPR", IIC_SprMFTB>;
def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR),
"mfpmr $RT, $SPR", IIC_SprMFPMR>; "mfpmr $RST, $SPR", IIC_SprMFPMR>;
def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST),
"mtpmr $SPR, $RT", IIC_SprMTPMR>; "mtpmr $SPR, $RST", IIC_SprMTPMR>;
// A pseudo-instruction used to implement the read of the 64-bit cycle counter // A pseudo-instruction used to implement the read of the 64-bit cycle counter
// on a 32-bit target. // on a 32-bit target.
let hasSideEffects = 1 in let hasSideEffects = 1 in
def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins),
"#ReadTB", []>; "#ReadTB", []>;
let Uses = [CTR] in { let Uses = [CTR] in {
def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins),
"mfctr $rT", IIC_SprMFSPR>, "mfctr $RST", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in {
def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST),
"mtctr $rS", IIC_SprMTSPR>, "mtctr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in {
let Pattern = [(int_set_loop_iterations i32:$rS)] in let Pattern = [(int_set_loop_iterations i32:$RST)] in
def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST),
"mtctr $rS", IIC_SprMTSPR>, "mtctr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in
def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride),
"#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>;
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let Defs = [LR] in { let Defs = [LR] in {
def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST),
"mtlr $rS", IIC_SprMTSPR>, "mtlr $RST", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Uses = [LR] in { let Uses = [LR] in {
def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins),
"mflr $rT", IIC_SprMFSPR>, "mflr $RST", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
} }
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX), def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST),
"mtspr 3, $rX", IIC_SprMTSPR>, "mtspr 3, $RST", IIC_SprMTSPR>,
PPC970_DGroup_Single, PPC970_Unit_FXU; PPC970_DGroup_Single, PPC970_Unit_FXU;
def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins), def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins),
"mfspr $rX, 3", IIC_SprMFSPR>, "mfspr $RST, 3", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
// Disable these alias on AIX since they are not supported. // Disable these alias on AIX since they are not supported.
let Predicates = [ModernAs] in { let Predicates = [ModernAs] in {
// Aliases for moving to/from dscr to mtspr/mfspr // Aliases for moving to/from dscr to mtspr/mfspr
def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>;
def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>;
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
// like a GPR on the PPC970. As such, copies in and out have the same // like a GPR on the PPC970. As such, copies in and out have the same
// performance characteristics as an OR instruction. // performance characteristics as an OR instruction.
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST),
"mtspr 256, $rS", IIC_IntGeneral>, "mtspr 256, $RST", IIC_IntGeneral>,
PPC970_DGroup_Single, PPC970_Unit_FXU; PPC970_DGroup_Single, PPC970_Unit_FXU;
def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins),
"mfspr $rT, 256", IIC_IntGeneral>, "mfspr $RST, 256", IIC_IntGeneral>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, def MTVRSAVEv : XFXForm_1_ext<31, 467, 256,
(outs VRSAVERC:$reg), (ins gprc:$rS), (outs VRSAVERC:$SPR), (ins gprc:$RST),
"mtspr 256, $rS", IIC_IntGeneral>, "mtspr 256, $RST", IIC_IntGeneral>,
PPC970_DGroup_Single, PPC970_Unit_FXU; PPC970_DGroup_Single, PPC970_Unit_FXU;
def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST),
(ins VRSAVERC:$reg), (ins VRSAVERC:$SPR),
"mfspr $rT, 256", IIC_IntGeneral>, "mfspr $RST, 256", IIC_IntGeneral>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. // Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
// mtocrf's input needs to be prepared by shifting by an amount dependent // mtocrf's input needs to be prepared by shifting by an amount dependent
// on the cr register selected. Thus, post-ra anti-dep breaking must not // on the cr register selected. Thus, post-ra anti-dep breaking must not
// later change that register assignment. // later change that register assignment.
let hasExtraDefRegAllocReq = 1 in { let hasExtraDefRegAllocReq = 1 in {
def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST),
"mtocrf $FXM, $ST", IIC_BrMCRX>, "mtocrf $FXM, $RST", IIC_BrMCRX>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
// is dependent on the cr fields being set. // is dependent on the cr fields being set.
def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST),
"mtcrf $FXM, $rS", IIC_BrMCRX>, "mtcrf $FXM, $RST", IIC_BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraDefRegAllocReq = 1 } // hasExtraDefRegAllocReq = 1
// mfocrf's input needs to be prepared by shifting by an amount dependent // mfocrf's input needs to be prepared by shifting by an amount dependent
// on the cr register selected. Thus, post-ra anti-dep breaking must not // on the cr register selected. Thus, post-ra anti-dep breaking must not
// later change that register assignment. // later change that register assignment.
let hasExtraSrcRegAllocReq = 1 in { let hasExtraSrcRegAllocReq = 1 in {
def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM),
"mfocrf $rT, $FXM", IIC_SprMFCRF>, "mfocrf $RST, $FXM", IIC_SprMFCRF>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
// is dependent on the cr fields being copied. // is dependent on the cr fields being copied.
def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins),
"mfcr $rT", IIC_SprMFCR>, "mfcr $RT", IIC_SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // hasExtraSrcRegAllocReq = 1 } // hasExtraSrcRegAllocReq = 1
def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
"mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
} // hasSideEffects = 0 } // hasSideEffects = 0
def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;
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def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
"mtfsb1 $FM", IIC_IntMTFSB0, "mtfsb1 $FM", IIC_IntMTFSB0,
[(int_ppc_mtfsb1 timm:$FM)]>, [(int_ppc_mtfsb1 timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
} }
let Defs = [RM], hasSideEffects = 1 in { let Defs = [RM], hasSideEffects = 1 in {
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT),
"mtfsf $FM, $rT", IIC_IntMTFSB0, "mtfsf $FM, $RT", IIC_IntMTFSB0,
[(int_ppc_mtfsf timm:$FM, f64:$rT)]>, [(int_ppc_mtfsf timm:$FM, f64:$RT)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
} }
let Uses = [RM], hasSideEffects = 1 in { let Uses = [RM], hasSideEffects = 1 in {
def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins),
"mffs $rT", IIC_IntMFFS, "mffs $RST", IIC_IntMFFS,
[(set f64:$rT, (PPCmffs))]>, [(set f64:$RST, (PPCmffs))]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
let Defs = [CR1] in let Defs = [CR1] in
def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins),
"mffs. $rT", IIC_IntMFFS, []>, isRecordForm; "mffs. $RST", IIC_IntMFFS, []>, isRecordForm;
def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins),
"mffsce $rT", IIC_IntMFFS, []>, "mffsce $RST", IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST),
(ins f8rc:$FRB), "mffscdrn $rT, $FRB", (ins f8rc:$FRB), "mffscdrn $RST, $FRB",
IIC_IntMFFS, []>, IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST),
(ins u3imm:$DRM), (ins u3imm:$DRM),
"mffscdrni $rT, $DRM", "mffscdrni $RST, $DRM",
IIC_IntMFFS, []>, IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST),
(ins f8rc:$FRB), "mffscrn $rT, $FRB", (ins f8rc:$FRB), "mffscrn $RST, $FRB",
IIC_IntMFFS, []>, IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST),
(ins u2imm:$RM), "mffscrni $rT, $RM", (ins u2imm:$RM), "mffscrni $RST, $RM",
IIC_IntMFFS, []>, IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins),
"mffsl $rT", IIC_IntMFFS, []>, "mffsl $RST", IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
} }
} }
let Predicates = [IsISA3_0] in { let Predicates = [IsISA3_0] in {
def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB),
"modsw $rT, $rA, $rB", IIC_IntDivW, "modsw $RST, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (srem i32:$rA, i32:$rB))]>; [(set i32:$RST, (srem i32:$RA, i32:$RB))]>;
def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB),
"moduw $rT, $rA, $rB", IIC_IntDivW, "moduw $RST, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (urem i32:$rA, i32:$rB))]>; [(set i32:$RST, (urem i32:$RA, i32:$RB))]>;
let hasSideEffects = 1 in let hasSideEffects = 1 in
def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT),
(ins gprc:$rA, gprc:$rB, u2imm:$CY), (ins gprc:$RA, gprc:$RB, u2imm:$CY),
"addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>;
} }
let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
// XO-Form instructions. Arithmetic instructions that can set overflow bit // XO-Form instructions. Arithmetic instructions that can set overflow bit
let isCommutable = 1 in let isCommutable = 1 in
defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"add", "$rT, $rA, $rB", IIC_IntSimple, "add", "$RT, $RA, $RB", IIC_IntSimple,
[(set i32:$rT, (add i32:$rA, i32:$rB))]>; [(set i32:$RT, (add i32:$RA, i32:$RB))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB),
"add $rT, $rA, $rB", IIC_IntSimple, "add $RT, $RA, $RB", IIC_IntSimple,
[(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>;
let isCommutable = 1 in let isCommutable = 1 in
defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"addc", "$rT, $rA, $rB", IIC_IntGeneral, "addc", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i32:$rT, (addc i32:$rA, i32:$rB))]>, [(set i32:$RT, (addc i32:$RA, i32:$RB))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"divw", "$rT, $rA, $rB", IIC_IntDivW, "divw", "$RT, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>;
defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"divwu", "$rT, $rA, $rB", IIC_IntDivW, "divwu", "$RT, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>;
defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"divwe", "$rT, $rA, $rB", IIC_IntDivW, "divwe", "$RT, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>,
Requires<[HasExtDiv]>; Requires<[HasExtDiv]>;
defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"divweu", "$rT, $rA, $rB", IIC_IntDivW, "divweu", "$RT, $RA, $RB", IIC_IntDivW,
[(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>,
Requires<[HasExtDiv]>; Requires<[HasExtDiv]>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"mulhw", "$rT, $rA, $rB", IIC_IntMulHW, "mulhw", "$RT, $RA, $RB", IIC_IntMulHW,
[(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>;
defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU,
[(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>;
defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"mullw", "$rT, $rA, $rB", IIC_IntMulHW, "mullw", "$RT, $RA, $RB", IIC_IntMulHW,
[(set i32:$rT, (mul i32:$rA, i32:$rB))]>; [(set i32:$RT, (mul i32:$RA, i32:$RB))]>;
} // isCommutable } // isCommutable
defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"subf", "$rT, $rA, $rB", IIC_IntGeneral, "subf", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i32:$rT, (sub i32:$rB, i32:$rA))]>; [(set i32:$RT, (sub i32:$RB, i32:$RA))]>;
defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"subfc", "$rT, $rA, $rB", IIC_IntGeneral, "subfc", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i32:$rT, (subc i32:$rB, i32:$rA))]>, [(set i32:$RT, (subc i32:$RB, i32:$RA))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA),
"neg", "$rT, $rA", IIC_IntSimple, "neg", "$RT, $RA", IIC_IntSimple,
[(set i32:$rT, (ineg i32:$rA))]>; [(set i32:$RT, (ineg i32:$RA))]>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
let isCommutable = 1 in let isCommutable = 1 in
defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"adde", "$rT, $rA, $rB", IIC_IntGeneral, "adde", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i32:$rT, (adde i32:$rA, i32:$rB))]>; [(set i32:$RT, (adde i32:$RA, i32:$RB))]>;
defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA),
"addme", "$rT, $rA", IIC_IntGeneral, "addme", "$RT, $RA", IIC_IntGeneral,
[(set i32:$rT, (adde i32:$rA, -1))]>; [(set i32:$RT, (adde i32:$RA, -1))]>;
defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA),
"addze", "$rT, $rA", IIC_IntGeneral, "addze", "$RT, $RA", IIC_IntGeneral,
[(set i32:$rT, (adde i32:$rA, 0))]>; [(set i32:$RT, (adde i32:$RA, 0))]>;
defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"subfe", "$rT, $rA, $rB", IIC_IntGeneral, "subfe", "$RT, $RA, $RB", IIC_IntGeneral,
[(set i32:$rT, (sube i32:$rB, i32:$rA))]>; [(set i32:$RT, (sube i32:$RB, i32:$RA))]>;
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA),
"subfme", "$rT, $rA", IIC_IntGeneral, "subfme", "$RT, $RA", IIC_IntGeneral,
[(set i32:$rT, (sube -1, i32:$rA))]>; [(set i32:$RT, (sube -1, i32:$RA))]>;
defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA),
"subfze", "$rT, $rA", IIC_IntGeneral, "subfze", "$RT, $RA", IIC_IntGeneral,
[(set i32:$rT, (sube 0, i32:$rA))]>; [(set i32:$RT, (sube 0, i32:$RA))]>;
} }
} }
def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;
def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;
def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines defm FSUBS : AForm_2r<59, 20,
[(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>;
} }
} }
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
let isSelect = 1 in let isSelect = 1 in
def ISEL : AForm_4<31, 15, def ISEL : AForm_4<31, 15,
(outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND),
"isel $rT, $rA, $rB, $cond", IIC_IntISEL, "isel $RT, $RA, $RB, $COND", IIC_IntISEL,
[]>; []>;
} }
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
// M-Form instructions. rotate and mask instructions. // M-Form instructions. rotate and mask instructions.
// //
let isCommutable = 1 in { let isCommutable = 1 in {
// RLWIMI can be commuted if the rotate amount is zero. // RLWIMI can be commuted if the rotate amount is zero.
defm RLWIMI : MForm_2r<20, (outs gprc:$rA), defm RLWIMI : MForm_2r<20, (outs gprc:$RA),
(ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB,
u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
IIC_IntRotate, []>, PPC970_DGroup_Cracked, IIC_IntRotate, []>, PPC970_DGroup_Cracked,
RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
} }
let BaseName = "rlwinm" in { let BaseName = "rlwinm" in {
def RLWINM : MForm_2<21, def RLWINM : MForm_2<21,
(outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,
[]>, RecFormRel; []>, RecFormRel;
let Defs = [CR0] in let Defs = [CR0] in
def RLWINM_rec : MForm_2<21, def RLWINM_rec : MForm_2<21,
(outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,
[]>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked;
} }
defm RLWNM : MForm_2r<23, (outs gprc:$rA), defm RLWNM : MForm_1r<23, (outs gprc:$RA),
(ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME),
"rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral,
[]>; []>;
} }
} // hasSideEffects = 0 } // hasSideEffects = 0
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns // PowerPC Instruction Patterns
// //
▲ Show 20 Lines • Show All 1,050 Lines • ▼ Show 20 Lines
def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Instructions used for assembler/disassembler only // PowerPC Instructions used for assembler/disassembler only
// //
// FIXME: For B=0 or B > 8, the registers following RT are used. // FIXME: For B=0 or B > 8, the registers following RT are used.
// WARNING: Do not add patterns for this instruction without fixing this. // WARNING: Do not add patterns for this instruction without fixing this.
def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST),
(ins gprc:$A, u5imm:$B), (ins gprc:$RA, u5imm:$RB),
"lswi $RT, $A, $B", IIC_LdStLoad, []>; "lswi $RST, $RA, $RB", IIC_LdStLoad, []>;
// FIXME: For B=0 or B > 8, the registers following RT are used. // FIXME: For B=0 or B > 8, the registers following RT are used.
// WARNING: Do not add patterns for this instruction without fixing this. // WARNING: Do not add patterns for this instruction without fixing this.
def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), def STSWI : XForm_base_r3xo_memOp<31, 725, (outs),
(ins gprc:$RT, gprc:$A, u5imm:$B), (ins gprc:$RST, gprc:$RA, u5imm:$RB),
"stswi $RT, $A, $B", IIC_LdStLoad, []>; "stswi $RST, $RA, $RB", IIC_LdStLoad, []>;
def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
"isync", IIC_SprISYNC, []>; "isync", IIC_SprISYNC, []>;
def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr),
"icbi $src", IIC_LdStICBI, []>; "icbi $addr", IIC_LdStICBI, []>;
def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L),
"wait $L", IIC_LdStLoad, []>; "wait $L", IIC_LdStLoad, []>;
def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
"mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
Show All 19 Lines
def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
Requires<[IsBookE]> { Requires<[IsBookE]> {
bits<1> E; bits<1> E;
let Inst{16} = E; let Inst{16} = E;
let Inst{21-30} = 163; let Inst{21-30} = 163;
} }
def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB),
"dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB),
"iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins),
"mfmsr $RT", IIC_SprMFMSR, []>; "mfmsr $RST", IIC_SprMFMSR, []>;
def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L),
"mtmsrd $RS, $L", IIC_SprMTMSRD>; "mtmsrd $RS, $L", IIC_SprMTMSRD>;
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
"mcrfs $BF, $BFA", IIC_BrMCR>; "mcrfs $BF, $BFA", IIC_BrMCR>;
// All MTFSF variants may change the rounding mode so conservatively set it // All MTFSF variants may change the rounding mode so conservatively set it
Show All 23 Lines
def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>;
def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
} }
def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
"slbie $RB", IIC_SprSLBIE, []>; "slbie $RB", IIC_SprSLBIE, []>;
def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB),
"slbmte $RS, $RB", IIC_SprSLBMTE, []>; "slbmte $RST, $RB", IIC_SprSLBMTE, []>;
def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB),
"slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>;
def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
"slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
let Defs = [CR0] in let Defs = [CR0] in
def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB),
"slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm;
def TLBIA : XForm_0<31, 370, (outs), (ins), def TLBIA : XForm_0<31, 370, (outs), (ins),
"tlbia", IIC_SprTLBIA, []>; "tlbia", IIC_SprTLBIA, []>;
def TLBSYNC : XForm_0<31, 566, (outs), (ins), def TLBSYNC : XForm_0<31, 566, (outs), (ins),
"tlbsync", IIC_SprTLBSYNC, []>; "tlbsync", IIC_SprTLBSYNC, []>;
def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
"tlbiel $RB", IIC_SprTLBIEL, []>; "tlbiel $RB", IIC_SprTLBIEL, []>;
def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
"tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
"tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB),
"tlbie $RB,$RS", IIC_SprTLBIE, []>; "tlbie $RB,$RST", IIC_SprTLBIE, []>;
def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
IIC_LdStLoad>, Requires<[IsBookE]>; IIC_LdStLoad>, Requires<[IsBookE]>;
def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",
IIC_LdStLoad>, Requires<[IsBookE]>; IIC_LdStLoad>, Requires<[IsBookE]>;
def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
"tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
"tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS),
"tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS),
"tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"tlbsx $RST, $A, $B", IIC_LdStLoad, []>, "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>,
Requires<[IsPPC4xx]>; Requires<[IsPPC4xx]>;
def TLBSX2D : XForm_base_r3xo<31, 914, (outs), def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
(ins gprc:$RST, gprc:$A, gprc:$B), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>,
Requires<[IsPPC4xx]>, isRecordForm; Requires<[IsPPC4xx]>, isRecordForm;
def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
Requires<[IsBookE]>; Requires<[IsBookE]>;
def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
Requires<[IsBookE]>; Requires<[IsBookE]>;
def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR),
"mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR),
"mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST),
(ins gprc:$A, gprc:$B), (ins gprc:$RA, gprc:$RB),
"lbzcix $RST, $A, $B", IIC_LdStLoad, []>; "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST),
(ins gprc:$A, gprc:$B), (ins gprc:$RA, gprc:$RB),
"lhzcix $RST, $A, $B", IIC_LdStLoad, []>; "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST),
(ins gprc:$A, gprc:$B), (ins gprc:$RA, gprc:$RB),
"lwzcix $RST, $A, $B", IIC_LdStLoad, []>; "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST),
(ins gprc:$A, gprc:$B), (ins gprc:$RA, gprc:$RB),
"ldcix $RST, $A, $B", IIC_LdStLoad, []>; "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs),
(ins gprc:$RST, gprc:$A, gprc:$B), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"stbcix $RST, $A, $B", IIC_LdStLoad, []>; "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs),
(ins gprc:$RST, gprc:$A, gprc:$B), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"sthcix $RST, $A, $B", IIC_LdStLoad, []>; "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs),
(ins gprc:$RST, gprc:$A, gprc:$B), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"stwcix $RST, $A, $B", IIC_LdStLoad, []>; "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>;
def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs),
(ins gprc:$RST, gprc:$A, gprc:$B), (ins gprc:$RST, gprc:$RA, gprc:$RB),
"stdcix $RST, $A, $B", IIC_LdStLoad, []>; "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>;
// External PID Load Store Instructions // External PID Load Store Instructions
def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lbepx $rD, $src", IIC_LdStLoad, []>, "lbepx $RST, $addr", IIC_LdStLoad, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr),
"lfdepx $frD, $src", IIC_LdStLFD, []>, "lfdepx $RST, $addr", IIC_LdStLFD, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lhepx $rD, $src", IIC_LdStLoad, []>, "lhepx $RST, $addr", IIC_LdStLoad, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
"lwepx $rD, $src", IIC_LdStLoad, []>, "lwepx $RST, $addr", IIC_LdStLoad, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbepx $rS, $dst", IIC_LdStStore, []>, "stbepx $RST, $addr", IIC_LdStStore, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfdepx $frS, $dst", IIC_LdStSTFD, []>, "stfdepx $RST, $addr", IIC_LdStSTFD, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthepx $rS, $dst", IIC_LdStStore, []>, "sthepx $RST, $addr", IIC_LdStStore, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwepx $rS, $dst", IIC_LdStStore, []>, "stwepx $RST, $addr", IIC_LdStStore, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr",
IIC_LdStDCBF, []>, Requires<[IsE500]>; IIC_LdStDCBF, []>, Requires<[IsE500]>;
def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr",
IIC_LdStDCBF, []>, Requires<[IsE500]>; IIC_LdStDCBF, []>, Requires<[IsE500]>;
def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH),
"dcbtep $TH, $dst", IIC_LdStDCBF, []>, "dcbtep $TH, $addr", IIC_LdStDCBF, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH),
"dcbtstep $TH, $dst", IIC_LdStDCBF, []>, "dcbtstep $TH, $addr", IIC_LdStDCBF, []>,
Requires<[IsE500]>; Requires<[IsE500]>;
def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr",
IIC_LdStDCBF, []>, Requires<[IsE500]>; IIC_LdStDCBF, []>, Requires<[IsE500]>;
def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr",
IIC_LdStDCBF, []>, Requires<[IsE500]>; IIC_LdStDCBF, []>, Requires<[IsE500]>;
def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr",
IIC_LdStICBI, []>, Requires<[IsE500]>; IIC_LdStICBI, []>, Requires<[IsE500]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Assembler Instruction Aliases // PowerPC Assembler Instruction Aliases
// //
// Pseudo-instructions for alternate assembly syntax (never used by codegen). // Pseudo-instructions for alternate assembly syntax (never used by codegen).
// These are aliases that require C++ handling to convert to the target // These are aliases that require C++ handling to convert to the target
▲ Show 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
(ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
// These generic branch instruction forms are used for the assembler parser only. // These generic branch instruction forms are used for the assembler parser only.
// Defs and Uses are conservative, since we don't know the BO value. // Defs and Uses are conservative, since we don't know the BO value.
let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in {
let Defs = [CTR], Uses = [CTR, RM] in { let Defs = [CTR], Uses = [CTR, RM] in {
def gBC : BForm_3<16, 0, 0, (outs), def gBC : BForm_3<16, 0, 0, (outs),
(ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD),
"bc $bo, $bi, $dst">; "bc $BO, $BI, $BD">;
def gBCA : BForm_3<16, 1, 0, (outs), def gBCA : BForm_3<16, 1, 0, (outs),
(ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD),
"bca $bo, $bi, $dst">; "bca $BO, $BI, $BD">;
let isAsmParserOnly = 1 in { let isAsmParserOnly = 1 in {
def gBCat : BForm_3_at<16, 0, 0, (outs), def gBCat : BForm_3_at<16, 0, 0, (outs),
(ins u5imm:$bo, atimm:$at, crbitrc:$bi, (ins u5imm:$BO, atimm:$at, crbitrc:$BI,
condbrtarget:$dst), condbrtarget:$BD),
"bc$at $bo, $bi, $dst">; "bc$at $BO, $BI, $BD">;
def gBCAat : BForm_3_at<16, 1, 0, (outs), def gBCAat : BForm_3_at<16, 1, 0, (outs),
(ins u5imm:$bo, atimm:$at, crbitrc:$bi, (ins u5imm:$BO, atimm:$at, crbitrc:$BI,
abscondbrtarget:$dst), abscondbrtarget:$BD),
"bca$at $bo, $bi, $dst">; "bca$at $BO, $BI, $BD">;
} // isAsmParserOnly = 1 } // isAsmParserOnly = 1
} }
let Defs = [LR, CTR], Uses = [CTR, RM] in { let Defs = [LR, CTR], Uses = [CTR, RM] in {
def gBCL : BForm_3<16, 0, 1, (outs), def gBCL : BForm_3<16, 0, 1, (outs),
(ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD),
"bcl $bo, $bi, $dst">; "bcl $BO, $BI, $BD">;
def gBCLA : BForm_3<16, 1, 1, (outs), def gBCLA : BForm_3<16, 1, 1, (outs),
(ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD),
"bcla $bo, $bi, $dst">; "bcla $BO, $BI, $BD">;
let isAsmParserOnly = 1 in { let isAsmParserOnly = 1 in {
def gBCLat : BForm_3_at<16, 0, 1, (outs), def gBCLat : BForm_3_at<16, 0, 1, (outs),
(ins u5imm:$bo, atimm:$at, crbitrc:$bi, (ins u5imm:$BO, atimm:$at, crbitrc:$BI,
condbrtarget:$dst), condbrtarget:$BD),
"bcl$at $bo, $bi, $dst">; "bcl$at $BO, $BI, $BD">;
def gBCLAat : BForm_3_at<16, 1, 1, (outs), def gBCLAat : BForm_3_at<16, 1, 1, (outs),
(ins u5imm:$bo, atimm:$at, crbitrc:$bi, (ins u5imm:$BO, atimm:$at, crbitrc:$BI,
abscondbrtarget:$dst), abscondbrtarget:$BD),
"bcla$at $bo, $bi, $dst">; "bcla$at $BO, $BI, $BD">;
} // // isAsmParserOnly = 1 } // // isAsmParserOnly = 1
} }
let Defs = [CTR], Uses = [CTR, LR, RM] in let Defs = [CTR], Uses = [CTR, LR, RM] in
def gBCLR : XLForm_2<19, 16, 0, (outs), def gBCLR : XLForm_2<19, 16, 0, (outs),
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bclr $bo, $bi, $bh", IIC_BrB, []>; "bclr $BO, $BI, $BH", IIC_BrB, []>;
let Defs = [LR, CTR], Uses = [CTR, LR, RM] in let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
def gBCLRL : XLForm_2<19, 16, 1, (outs), def gBCLRL : XLForm_2<19, 16, 1, (outs),
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bclrl $bo, $bi, $bh", IIC_BrB, []>; "bclrl $BO, $BI, $BH", IIC_BrB, []>;
let Defs = [CTR], Uses = [CTR, LR, RM] in let Defs = [CTR], Uses = [CTR, LR, RM] in
def gBCCTR : XLForm_2<19, 528, 0, (outs), def gBCCTR : XLForm_2<19, 528, 0, (outs),
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bcctr $bo, $bi, $bh", IIC_BrB, []>; "bcctr $BO, $BI, $BH", IIC_BrB, []>;
let Defs = [LR, CTR], Uses = [CTR, LR, RM] in let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
def gBCCTRL : XLForm_2<19, 528, 1, (outs), def gBCCTRL : XLForm_2<19, 528, 1, (outs),
(ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bcctrl $bo, $bi, $bh", IIC_BrB, []>; "bcctrl $BO, $BI, $BH", IIC_BrB, []>;
} }
multiclass BranchSimpleMnemonicAT<string pm, int at> { multiclass BranchSimpleMnemonicAT<string pm, int at> {
def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
condbrtarget:$dst)>; condbrtarget:$dst)>;
def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
condbrtarget:$dst)>; condbrtarget:$dst)>;
def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
▲ Show 20 Lines • Show All 423 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrMMA.td

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Linesmulticlass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
} }
} }
// End of class definitions. // End of class definitions.
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
let Predicates = [MMA] in { let Predicates = [MMA] in {
def XXMFACC : def XXMFACC :
XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS", XForm_AT3<31, 0, 177, (outs acc:$ATo), (ins acc:$AT), "xxmfacc $AT",
IIC_VecGeneral, IIC_VecGeneral,
[(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>, [(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>,
RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">; RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">;
def XXMTACC : def XXMTACC :
XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT", XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT",
IIC_VecGeneral, IIC_VecGeneral,
[(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>, [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp), def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp),
"#KILL_PAIR", []>, "#KILL_PAIR", []>,
RegConstraint<"$XTp = $XSp">; RegConstraint<"$XTp = $XSp">;
▲ Show 20 Lines • Show All 325 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrP10.td

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)), !strconcat(asmbase, !strconcat(". ", asmstr)),
itin, []>, isRecordForm, RecFormRel; itin, []>, isRecordForm, RecFormRel;
} }
} }
class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> { : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> FRS; bits<5> RST;
bits<39> D_RA; bits<39> D_RA;
let Pattern = pattern; let Pattern = pattern;
// The prefix. // The prefix.
let Inst{6-7} = 2; let Inst{6-7} = 2;
let Inst{8-10} = 0; let Inst{8-10} = 0;
let Inst{11} = PCRel; let Inst{11} = PCRel;
let Inst{12-13} = 0; let Inst{12-13} = 0;
let Inst{14-31} = D_RA{33-16}; // d0 let Inst{14-31} = D_RA{33-16}; // d0
// The instruction. // The instruction.
let Inst{38-42} = FRS{4-0}; let Inst{38-42} = RST{4-0};
let Inst{43-47} = D_RA{38-34}; // RA let Inst{43-47} = D_RA{38-34}; // RA
let Inst{48-63} = D_RA{15-0}; // d1 let Inst{48-63} = D_RA{15-0}; // d1
} }
class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> { : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>; !strconcat(asmstr, ", 0"), itin, []>;
def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>, isPCRel; !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
} }
class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> { : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RST;
bits<39> D_RA; bits<39> D_RA;
let Pattern = pattern; let Pattern = pattern;
// The prefix. // The prefix.
let Inst{6-10} = 0; let Inst{6-10} = 0;
let Inst{11} = PCRel; let Inst{11} = PCRel;
let Inst{12-13} = 0; let Inst{12-13} = 0;
let Inst{14-31} = D_RA{33-16}; // d0 let Inst{14-31} = D_RA{33-16}; // d0
// The instruction. // The instruction.
let Inst{38-42} = RT{4-0}; let Inst{38-42} = RST{4-0};
let Inst{43-47} = D_RA{38-34}; // RA let Inst{43-47} = D_RA{38-34}; // RA
let Inst{48-63} = D_RA{15-0}; // d1 let Inst{48-63} = D_RA{15-0}; // d1
} }
// 8LS:D-Form: [ 1 0 0 // R // d0 // 8LS:D-Form: [ 1 0 0 // R // d0
// PO TX T RA d1 ] // PO TX T RA d1 ]
class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL, class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, string asmstr, InstrItinClass itin,
list<dag> pattern> list<dag> pattern>
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
bits<6> XT; bits<6> XST;
bits<39> D_RA; bits<39> D_RA;
let Pattern = pattern; let Pattern = pattern;
// The prefix. // The prefix.
let Inst{6-7} = 0; let Inst{6-7} = 0;
let Inst{8} = 0; let Inst{8} = 0;
let Inst{9-10} = 0; // reserved let Inst{9-10} = 0; // reserved
let Inst{11} = PCRel; let Inst{11} = PCRel;
let Inst{12-13} = 0; // reserved let Inst{12-13} = 0; // reserved
let Inst{14-31} = D_RA{33-16}; // d0 let Inst{14-31} = D_RA{33-16}; // d0
// The instruction. // The instruction.
let Inst{37} = XT{5}; let Inst{37} = XST{5};
let Inst{38-42} = XT{4-0}; let Inst{38-42} = XST{4-0};
let Inst{43-47} = D_RA{38-34}; // RA let Inst{43-47} = D_RA{38-34}; // RA
let Inst{48-63} = D_RA{15-0}; // d1 let Inst{48-63} = D_RA{15-0}; // d1
} }
// X-Form: [PO T IMM VRB XO TX] // X-Form: [PO T IMM VRB XO TX]
class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesclass VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Inst{16-20} = VB; let Inst{16-20} = VB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
// VX-Form: [PO VRT RA VRB XO]. // VX-Form: [PO VRT RA VRB XO].
// Destructive (insert) forms are suffixed with _ins. // Destructive (insert) forms are suffixed with _ins.
class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB),
!strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>, !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
// VX-Form: [PO VRT RA RB XO]. // VX-Form: [PO VRT RA RB XO].
// Destructive (insert) forms are suffixed with _ins. // Destructive (insert) forms are suffixed with _ins.
class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB), : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB),
!strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>, !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
// VX-Form: [ PO BF // VRA VRB XO ] // VX-Form: [ PO BF // VRA VRB XO ]
class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<3> BF; bits<3> BF;
bits<5> VA; bits<5> VA;
bits<5> VB; bits<5> VB;
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Linesclass XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
let Inst{30} = XB{5}; let Inst{30} = XB{5};
let Inst{31} = 0; let Inst{31} = 0;
} }
// X-Form: [ PO RT BI /// XO / ] // X-Form: [ PO RT BI /// XO / ]
class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let B = 0; bits<5> BI;
let RA = BI;
let RB = 0;
} }
multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr, dag PCRel_IOL, string asmstr,
InstrItinClass itin> { InstrItinClass itin> {
def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>; !strconcat(asmstr, ", 0"), itin, []>;
def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lineslet Predicates = [PrefixInstrs] in {
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
(ins s34imm:$SI), (ins s34imm:$SI),
"pli $RT, $SI", IIC_IntSimple, []>; "pli $RT, $SI", IIC_IntSimple, []>;
} }
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
defm PLXV : defm PLXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), (ins memri34_pcrel:$D_RA),
"plxv $XT, $D_RA", IIC_LdStLFD>; "plxv $XST, $D_RA", IIC_LdStLFD>;
defm PLFS : defm PLFS :
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA", (ins memri34_pcrel:$D_RA), "plfs $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLFD : defm PLFD :
MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA", (ins memri34_pcrel:$D_RA), "plfd $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLXSSP : defm PLXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), (ins memri34_pcrel:$D_RA),
"plxssp $VRT, $D_RA", IIC_LdStLFD>; "plxssp $RST, $D_RA", IIC_LdStLFD>;
defm PLXSD : defm PLXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), (ins memri34_pcrel:$D_RA),
"plxsd $VRT, $D_RA", IIC_LdStLFD>; "plxsd $RST, $D_RA", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PLBZ8 : defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLHZ8 : defm PLHZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLHA8 : defm PLHA8 :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLWA8 : defm PLWA8 :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), (ins memri34_pcrel:$D_RA),
"plwa $RT, $D_RA", IIC_LdStLFD>; "plwa $RST, $D_RA", IIC_LdStLFD>;
defm PLWZ8 : defm PLWZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
} }
defm PLBZ : defm PLBZ :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLHZ : defm PLHZ :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLHA : defm PLHA :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLWZ : defm PLWZ :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLWA : defm PLWA :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", (ins memri34_pcrel:$D_RA), "plwa $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
defm PLD : defm PLD :
8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RT), (ins memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "pld $RT, $D_RA", (ins memri34_pcrel:$D_RA), "pld $RST, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
} }
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
defm PSTXV : defm PSTXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA), 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, memri34:$D_RA),
(ins vsrc:$XS, memri34_pcrel:$D_RA), (ins vsrc:$XST, memri34_pcrel:$D_RA),
"pstxv $XS, $D_RA", IIC_LdStLFD>; "pstxv $XST, $D_RA", IIC_LdStLFD>;
defm PSTFS : defm PSTFS :
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, memri34:$D_RA),
(ins f4rc:$FRS, memri34_pcrel:$D_RA), (ins f4rc:$RST, memri34_pcrel:$D_RA),
"pstfs $FRS, $D_RA", IIC_LdStLFD>; "pstfs $RST, $D_RA", IIC_LdStLFD>;
defm PSTFD : defm PSTFD :
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, memri34:$D_RA),
(ins f8rc:$FRS, memri34_pcrel:$D_RA), (ins f8rc:$RST, memri34_pcrel:$D_RA),
"pstfd $FRS, $D_RA", IIC_LdStLFD>; "pstfd $RST, $D_RA", IIC_LdStLFD>;
defm PSTXSSP : defm PSTXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, memri34:$D_RA),
(ins vfrc:$VRS, memri34_pcrel:$D_RA), (ins vfrc:$RST, memri34_pcrel:$D_RA),
"pstxssp $VRS, $D_RA", IIC_LdStLFD>; "pstxssp $RST, $D_RA", IIC_LdStLFD>;
defm PSTXSD : defm PSTXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, memri34:$D_RA),
(ins vfrc:$VRS, memri34_pcrel:$D_RA), (ins vfrc:$RST, memri34_pcrel:$D_RA),
"pstxsd $VRS, $D_RA", IIC_LdStLFD>; "pstxsd $RST, $D_RA", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PSTB8 : defm PSTB8 :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, memri34:$D_RA),
(ins g8rc:$RS, memri34_pcrel:$D_RA), (ins g8rc:$RST, memri34_pcrel:$D_RA),
"pstb $RS, $D_RA", IIC_LdStLFD>; "pstb $RST, $D_RA", IIC_LdStLFD>;
defm PSTH8 : defm PSTH8 :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, memri34:$D_RA),
(ins g8rc:$RS, memri34_pcrel:$D_RA), (ins g8rc:$RST, memri34_pcrel:$D_RA),
"psth $RS, $D_RA", IIC_LdStLFD>; "psth $RST, $D_RA", IIC_LdStLFD>;
defm PSTW8 : defm PSTW8 :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, memri34:$D_RA),
(ins g8rc:$RS, memri34_pcrel:$D_RA), (ins g8rc:$RST, memri34_pcrel:$D_RA),
"pstw $RS, $D_RA", IIC_LdStLFD>; "pstw $RST, $D_RA", IIC_LdStLFD>;
} }
defm PSTB : defm PSTB :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, memri34:$D_RA),
(ins gprc:$RS, memri34_pcrel:$D_RA), (ins gprc:$RST, memri34_pcrel:$D_RA),
"pstb $RS, $D_RA", IIC_LdStLFD>; "pstb $RST, $D_RA", IIC_LdStLFD>;
defm PSTH : defm PSTH :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, memri34:$D_RA),
(ins gprc:$RS, memri34_pcrel:$D_RA), (ins gprc:$RST, memri34_pcrel:$D_RA),
"psth $RS, $D_RA", IIC_LdStLFD>; "psth $RST, $D_RA", IIC_LdStLFD>;
defm PSTW : defm PSTW :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA), MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, memri34:$D_RA),
(ins gprc:$RS, memri34_pcrel:$D_RA), (ins gprc:$RST, memri34_pcrel:$D_RA),
"pstw $RS, $D_RA", IIC_LdStLFD>; "pstw $RST, $D_RA", IIC_LdStLFD>;
defm PSTD : defm PSTD :
8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA), 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, memri34:$D_RA),
(ins g8rc:$RS, memri34_pcrel:$D_RA), (ins g8rc:$RST, memri34_pcrel:$D_RA),
"pstd $RS, $D_RA", IIC_LdStLFD>; "pstd $RST, $D_RA", IIC_LdStLFD>;
} }
} }
class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> { : I<opcode, OOL, IOL, asmstr, itin> {
bits<5> XTp; bits<5> XTp;
bits<17> DQ_RA; bits<17> DQ_RA;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-9} = XTp{3-0}; let Inst{6-9} = XTp{3-0};
let Inst{10} = XTp{4}; let Inst{10} = XTp{4};
let Inst{11-15} = DQ_RA{16-12}; // Register # let Inst{11-15} = DQ_RA{16-12}; // Register #
let Inst{16-27} = DQ_RA{11-0}; // Displacement. let Inst{16-27} = DQ_RA{11-0}; // Displacement.
let Inst{28-31} = xo; let Inst{28-31} = xo;
} }
class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern> string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
bits<5> XTp; bits<5> XTp;
bits<5> A; bits<5> RA;
bits<5> B; bits<5> RB;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-9} = XTp{3-0}; let Inst{6-9} = XTp{3-0};
let Inst{10} = XTp{4}; let Inst{10} = XTp{4};
let Inst{11-15} = A; let Inst{11-15} = RA;
let Inst{16-20} = B; let Inst{16-20} = RB;
let Inst{21-30} = xo; let Inst{21-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }
class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> { : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<5> XTp; bits<5> XTp;
▲ Show 20 Lines • Show All 260 Lines • ▼ Show 20 Lineslet Predicates = [PairedVectorMemops] in {
def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
(v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
} }
let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in { let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
(ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA", (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
IIC_LdStLFD, []>; IIC_LdStLFD, []>;
def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src), def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr),
"lxvpx $XTp, $src", IIC_LdStLFD, "lxvpx $XTp, $addr", IIC_LdStLFD,
[]>; []>;
} }
let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in { let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA", memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
IIC_LdStLFD, []>; IIC_LdStLFD, []>;
def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst), def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr),
"stxvpx $XTp, $dst", IIC_LdStLFD, "stxvpx $XTp, $addr", IIC_LdStLFD,
[]>; []>;
} }
let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in { let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
defm PLXVP : defm PLXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA), 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
(ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA", (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
IIC_LdStLFD>; IIC_LdStLFD>;
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lineslet Predicates = [PCRelativeMemops] in {
// materialize tls global address with paddi instruction. // materialize tls global address with paddi instruction.
def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
(PADDI8 $in, $addr)>; (PADDI8 $in, $addr)>;
} }
let Predicates = [PrefixInstrs] in { let Predicates = [PrefixInstrs] in {
def XXPERMX : def XXPERMX :
8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC, u3imm:$UIM), vsrc:$XC, u3imm:$IMM),
"xxpermx $XT, $XA, $XB, $XC, $UIM", "xxpermx $XT, $XA, $XB, $XC, $IMM",
IIC_VecPerm, []>; IIC_VecPerm, []>;
def XXBLENDVB : def XXBLENDVB :
8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
IIC_VecGeneral, []>; IIC_VecGeneral, []>;
def XXBLENDVH : def XXBLENDVH :
8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
Show All 26 Lines def XXSPLTI32DX :
"xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
[(set v2i64:$XT, [(set v2i64:$XT,
(PPCxxsplti32dx v2i64:$XTi, i32:$IX, (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
i32:$IMM32))]>, i32:$IMM32))]>,
RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
} }
let Predicates = [IsISA3_1] in { let Predicates = [IsISA3_1] in {
def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI), def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI),
"setbc $RT, $BI", IIC_IntCompare, []>, "setbc $RST, $BI", IIC_IntCompare, []>,
SExt32To64, ZExt32To64; SExt32To64, ZExt32To64;
def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI), def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI),
"setbcr $RT, $BI", IIC_IntCompare, []>, "setbcr $RST, $BI", IIC_IntCompare, []>,
SExt32To64, ZExt32To64; SExt32To64, ZExt32To64;
def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI), def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI),
"setnbc $RT, $BI", IIC_IntCompare, []>, "setnbc $RST, $BI", IIC_IntCompare, []>,
SExt32To64; SExt32To64;
def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI), def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI),
"setnbcr $RT, $BI", IIC_IntCompare, []>, "setnbcr $RST, $BI", IIC_IntCompare, []>,
SExt32To64; SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI), def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI),
"setbc $RT, $BI", IIC_IntCompare, []>, "setbc $RST, $BI", IIC_IntCompare, []>,
SExt32To64, ZExt32To64; SExt32To64, ZExt32To64;
def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI), def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI),
"setbcr $RT, $BI", IIC_IntCompare, []>, "setbcr $RST, $BI", IIC_IntCompare, []>,
SExt32To64, ZExt32To64; SExt32To64, ZExt32To64;
def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI), def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI),
"setnbc $RT, $BI", IIC_IntCompare, []>, "setnbc $RST, $BI", IIC_IntCompare, []>,
SExt32To64; SExt32To64;
def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI), def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI),
"setnbcr $RT, $BI", IIC_IntCompare, []>, "setnbcr $RST, $BI", IIC_IntCompare, []>,
SExt32To64; SExt32To64;
} }
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),
"vsldbi $VRT, $VRA, $VRB, $SH", "vsldbi $VRT, $VRA, $VRB, $SD",
IIC_VecGeneral, IIC_VecGeneral,
[(set v16i8:$VRT, [(set v16i8:$VRT,
(int_ppc_altivec_vsldbi v16i8:$VRA, (int_ppc_altivec_vsldbi v16i8:$VRA,
v16i8:$VRB, v16i8:$VRB,
timm:$SH))]>; timm:$SD))]>;
def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),
"vsrdbi $VRT, $VRA, $VRB, $SH", "vsrdbi $VRT, $VRA, $VRB, $SD",
IIC_VecGeneral, IIC_VecGeneral,
[(set v16i8:$VRT, [(set v16i8:$VRT,
(int_ppc_altivec_vsrdbi v16i8:$VRA, (int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB, v16i8:$VRB,
timm:$SH))]>; timm:$SD))]>;
defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB),
"vstribr", "$vT, $vB", IIC_VecGeneral, "vstribr", "$VT, $VB", IIC_VecGeneral,
[(set v16i8:$vT, [(set v16i8:$VT,
(int_ppc_altivec_vstribr v16i8:$vB))]>; (int_ppc_altivec_vstribr v16i8:$VB))]>;
defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB), defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB),
"vstribl", "$vT, $vB", IIC_VecGeneral, "vstribl", "$VT, $VB", IIC_VecGeneral,
[(set v16i8:$vT, [(set v16i8:$VT,
(int_ppc_altivec_vstribl v16i8:$vB))]>; (int_ppc_altivec_vstribl v16i8:$VB))]>;
defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB), defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB),
"vstrihr", "$vT, $vB", IIC_VecGeneral, "vstrihr", "$VT, $VB", IIC_VecGeneral,
[(set v8i16:$vT, [(set v8i16:$VT,
(int_ppc_altivec_vstrihr v8i16:$vB))]>; (int_ppc_altivec_vstrihr v8i16:$VB))]>;
defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB), defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB),
"vstrihl", "$vT, $vB", IIC_VecGeneral, "vstrihl", "$VT, $VB", IIC_VecGeneral,
[(set v8i16:$vT, [(set v8i16:$VT,
(int_ppc_altivec_vstrihl v8i16:$vB))]>; (int_ppc_altivec_vstrihl v8i16:$VB))]>;
def VINSW : def VINSW :
VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB), VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB),
"vinsw $vD, $rB, $UIM", IIC_VecGeneral, "vinsw $VD, $VB, $VA", IIC_VecGeneral,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>, (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VINSD : def VINSD :
VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB), VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),
"vinsd $vD, $rB, $UIM", IIC_VecGeneral, "vinsd $VD, $VB, $VA", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>, (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VINSBVLX : def VINSBVLX :
VXForm_VTB5_RA5_ins<15, "vinsbvlx", VXForm_VTB5_RA5_ins<15, "vinsbvlx",
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA,
v16i8:$vB))]>; v16i8:$VB))]>;
def VINSBVRX : def VINSBVRX :
VXForm_VTB5_RA5_ins<271, "vinsbvrx", VXForm_VTB5_RA5_ins<271, "vinsbvrx",
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA,
v16i8:$vB))]>; v16i8:$VB))]>;
def VINSHVLX : def VINSHVLX :
VXForm_VTB5_RA5_ins<79, "vinshvlx", VXForm_VTB5_RA5_ins<79, "vinshvlx",
[(set v8i16:$vD, [(set v8i16:$VD,
(int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA,
v8i16:$vB))]>; v8i16:$VB))]>;
def VINSHVRX : def VINSHVRX :
VXForm_VTB5_RA5_ins<335, "vinshvrx", VXForm_VTB5_RA5_ins<335, "vinshvrx",
[(set v8i16:$vD, [(set v8i16:$VD,
(int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA,
v8i16:$vB))]>; v8i16:$VB))]>;
def VINSWVLX : def VINSWVLX :
VXForm_VTB5_RA5_ins<143, "vinswvlx", VXForm_VTB5_RA5_ins<143, "vinswvlx",
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA,
v4i32:$vB))]>; v4i32:$VB))]>;
def VINSWVRX : def VINSWVRX :
VXForm_VTB5_RA5_ins<399, "vinswvrx", VXForm_VTB5_RA5_ins<399, "vinswvrx",
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA,
v4i32:$vB))]>; v4i32:$VB))]>;
def VINSBLX : def VINSBLX :
VXForm_VRT5_RAB5_ins<527, "vinsblx", VXForm_VRT5_RAB5_ins<527, "vinsblx",
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA, (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSBRX : def VINSBRX :
VXForm_VRT5_RAB5_ins<783, "vinsbrx", VXForm_VRT5_RAB5_ins<783, "vinsbrx",
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA, (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSHLX : def VINSHLX :
VXForm_VRT5_RAB5_ins<591, "vinshlx", VXForm_VRT5_RAB5_ins<591, "vinshlx",
[(set v8i16:$vD, [(set v8i16:$VD,
(int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA, (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSHRX : def VINSHRX :
VXForm_VRT5_RAB5_ins<847, "vinshrx", VXForm_VRT5_RAB5_ins<847, "vinshrx",
[(set v8i16:$vD, [(set v8i16:$VD,
(int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA, (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSWLX : def VINSWLX :
VXForm_VRT5_RAB5_ins<655, "vinswlx", VXForm_VRT5_RAB5_ins<655, "vinswlx",
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA, (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSWRX : def VINSWRX :
VXForm_VRT5_RAB5_ins<911, "vinswrx", VXForm_VRT5_RAB5_ins<911, "vinswrx",
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA, (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA,
i32:$rB))]>; i32:$VB))]>;
def VINSDLX : def VINSDLX :
VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),
"vinsdlx $vD, $rA, $rB", IIC_VecGeneral, "vinsdlx $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VINSDRX : def VINSDRX :
VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),
"vinsdrx $vD, $rA, $rB", IIC_VecGeneral, "vinsdrx $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB), def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB),
"vextractbm $rD, $vB", IIC_VecGeneral, "vextractbm $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, [(set i32:$VD,
(int_ppc_altivec_vextractbm v16i8:$vB))]>, (int_ppc_altivec_vextractbm v16i8:$VB))]>,
ZExt32To64; ZExt32To64;
def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB), def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB),
"vextracthm $rD, $vB", IIC_VecGeneral, "vextracthm $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, [(set i32:$VD,
(int_ppc_altivec_vextracthm v8i16:$vB))]>, (int_ppc_altivec_vextracthm v8i16:$VB))]>,
ZExt32To64; ZExt32To64;
def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB), def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB),
"vextractwm $rD, $vB", IIC_VecGeneral, "vextractwm $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, [(set i32:$VD,
(int_ppc_altivec_vextractwm v4i32:$vB))]>, (int_ppc_altivec_vextractwm v4i32:$VB))]>,
ZExt32To64; ZExt32To64;
def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB), def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB),
"vextractdm $rD, $vB", IIC_VecGeneral, "vextractdm $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, [(set i32:$VD,
(int_ppc_altivec_vextractdm v2i64:$vB))]>, (int_ppc_altivec_vextractdm v2i64:$VB))]>,
ZExt32To64; ZExt32To64;
def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB), def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB),
"vextractqm $rD, $vB", IIC_VecGeneral, "vextractqm $VD, $VB", IIC_VecGeneral,
[(set i32:$rD, [(set i32:$VD,
(int_ppc_altivec_vextractqm v1i128:$vB))]>; (int_ppc_altivec_vextractqm v1i128:$VB))]>;
def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB),
"vexpandbm $vD, $vB", IIC_VecGeneral, "vexpandbm $VD, $VB", IIC_VecGeneral,
[(set v16i8:$vD, (int_ppc_altivec_vexpandbm [(set v16i8:$VD, (int_ppc_altivec_vexpandbm
v16i8:$vB))]>; v16i8:$VB))]>;
def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB),
"vexpandhm $vD, $vB", IIC_VecGeneral, "vexpandhm $VD, $VB", IIC_VecGeneral,
[(set v8i16:$vD, (int_ppc_altivec_vexpandhm [(set v8i16:$VD, (int_ppc_altivec_vexpandhm
v8i16:$vB))]>; v8i16:$VB))]>;
def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB),
"vexpandwm $vD, $vB", IIC_VecGeneral, "vexpandwm $VD, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (int_ppc_altivec_vexpandwm [(set v4i32:$VD, (int_ppc_altivec_vexpandwm
v4i32:$vB))]>; v4i32:$VB))]>;
def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB),
"vexpanddm $vD, $vB", IIC_VecGeneral, "vexpanddm $VD, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (int_ppc_altivec_vexpanddm [(set v2i64:$VD, (int_ppc_altivec_vexpanddm
v2i64:$vB))]>; v2i64:$VB))]>;
def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB),
"vexpandqm $vD, $vB", IIC_VecGeneral, "vexpandqm $VD, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vexpandqm [(set v1i128:$VD, (int_ppc_altivec_vexpandqm
v1i128:$vB))]>; v1i128:$VB))]>;
def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB),
"mtvsrbm $vD, $rB", IIC_VecGeneral, "mtvsrbm $VD, $VB", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_mtvsrbm i64:$rB))]>; (int_ppc_altivec_mtvsrbm i64:$VB))]>;
def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB), def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB),
"mtvsrhm $vD, $rB", IIC_VecGeneral, "mtvsrhm $VD, $VB", IIC_VecGeneral,
[(set v8i16:$vD, [(set v8i16:$VD,
(int_ppc_altivec_mtvsrhm i64:$rB))]>; (int_ppc_altivec_mtvsrhm i64:$VB))]>;
def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB), def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB),
"mtvsrwm $vD, $rB", IIC_VecGeneral, "mtvsrwm $VD, $VB", IIC_VecGeneral,
[(set v4i32:$vD, [(set v4i32:$VD,
(int_ppc_altivec_mtvsrwm i64:$rB))]>; (int_ppc_altivec_mtvsrwm i64:$VB))]>;
def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB), def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB),
"mtvsrdm $vD, $rB", IIC_VecGeneral, "mtvsrdm $VD, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_mtvsrdm i64:$rB))]>; (int_ppc_altivec_mtvsrdm i64:$VB))]>;
def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB), def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB),
"mtvsrqm $vD, $rB", IIC_VecGeneral, "mtvsrqm $VD, $VB", IIC_VecGeneral,
[(set v1i128:$vD, [(set v1i128:$VD,
(int_ppc_altivec_mtvsrqm i64:$rB))]>; (int_ppc_altivec_mtvsrqm i64:$VB))]>;
def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D), def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D),
"mtvsrbmi $vD, $D", IIC_VecGeneral, "mtvsrbmi $RT, $D", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$RT,
(int_ppc_altivec_mtvsrbm imm:$D))]>; (int_ppc_altivec_mtvsrbm imm:$D))]>;
def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD), def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD),
(ins vrrc:$vB, u1imm:$MP), (ins vrrc:$VB, u1imm:$MP),
"vcntmbb $rD, $vB, $MP", IIC_VecGeneral, "vcntmbb $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$rD, (int_ppc_altivec_vcntmbb [(set i64:$RD, (int_ppc_altivec_vcntmbb
v16i8:$vB, timm:$MP))]>; v16i8:$VB, timm:$MP))]>;
def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD), def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD),
(ins vrrc:$vB, u1imm:$MP), (ins vrrc:$VB, u1imm:$MP),
"vcntmbh $rD, $vB, $MP", IIC_VecGeneral, "vcntmbh $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$rD, (int_ppc_altivec_vcntmbh [(set i64:$RD, (int_ppc_altivec_vcntmbh
v8i16:$vB, timm:$MP))]>; v8i16:$VB, timm:$MP))]>;
def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD), def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD),
(ins vrrc:$vB, u1imm:$MP), (ins vrrc:$VB, u1imm:$MP),
"vcntmbw $rD, $vB, $MP", IIC_VecGeneral, "vcntmbw $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$rD, (int_ppc_altivec_vcntmbw [(set i64:$RD, (int_ppc_altivec_vcntmbw
v4i32:$vB, timm:$MP))]>; v4i32:$VB, timm:$MP))]>;
def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD), def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD),
(ins vrrc:$vB, u1imm:$MP), (ins vrrc:$VB, u1imm:$MP),
"vcntmbd $rD, $vB, $MP", IIC_VecGeneral, "vcntmbd $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$rD, (int_ppc_altivec_vcntmbd [(set i64:$RD, (int_ppc_altivec_vcntmbd
v2i64:$vB, timm:$MP))]>; v2i64:$VB, timm:$MP))]>;
def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD), def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextdubvlx $vD, $vA, $vB, $rC", "vextdubvlx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextdubvlx v16i8:$vA, (int_ppc_altivec_vextdubvlx v16i8:$RA,
v16i8:$vB, v16i8:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD), def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextdubvrx $vD, $vA, $vB, $rC", "vextdubvrx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextdubvrx v16i8:$vA, (int_ppc_altivec_vextdubvrx v16i8:$RA,
v16i8:$vB, v16i8:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD), def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextduhvlx $vD, $vA, $vB, $rC", "vextduhvlx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextduhvlx v8i16:$vA, (int_ppc_altivec_vextduhvlx v8i16:$RA,
v8i16:$vB, v8i16:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD), def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextduhvrx $vD, $vA, $vB, $rC", "vextduhvrx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextduhvrx v8i16:$vA, (int_ppc_altivec_vextduhvrx v8i16:$RA,
v8i16:$vB, v8i16:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD), def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextduwvlx $vD, $vA, $vB, $rC", "vextduwvlx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextduwvlx v4i32:$vA, (int_ppc_altivec_vextduwvlx v4i32:$RA,
v4i32:$vB, v4i32:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD), def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextduwvrx $vD, $vA, $vB, $rC", "vextduwvrx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextduwvrx v4i32:$vA, (int_ppc_altivec_vextduwvrx v4i32:$RA,
v4i32:$vB, v4i32:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD), def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextddvlx $vD, $vA, $vB, $rC", "vextddvlx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextddvlx v2i64:$vA, (int_ppc_altivec_vextddvlx v2i64:$RA,
v2i64:$vB, v2i64:$RB,
i32:$rC))]>; i32:$RC))]>;
def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD), def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC), (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextddvrx $vD, $vA, $vB, $rC", "vextddvrx $RT, $RA, $RB, $RC",
IIC_VecGeneral, IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$RT,
(int_ppc_altivec_vextddvrx v2i64:$vA, (int_ppc_altivec_vextddvrx v2i64:$RA,
v2i64:$vB, v2i64:$RB,
i32:$rC))]>; i32:$RC))]>;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral, "vpdepd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>;
def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vpextd $vD, $vA, $vB", IIC_VecGeneral, "vpextd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>;
def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"pdepd $rA, $rS, $rB", IIC_IntGeneral, "pdepd $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>; [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>;
def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"pextd $rA, $rS, $rB", IIC_IntGeneral, "pextd $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>; [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>;
def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vcfuged $vD, $vA, $vB", IIC_VecGeneral, "vcfuged $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>;
def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N), def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N),
"vgnb $rD, $vB, $N", IIC_VecGeneral, "vgnb $RD, $VB, $N", IIC_VecGeneral,
[(set i64:$rD, [(set i64:$RD,
(int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>; (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>;
def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"cfuged $rA, $rS, $rB", IIC_IntGeneral, "cfuged $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>; [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>;
def XXEVAL : def XXEVAL :
8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
vsrc:$XC, u8imm:$IMM), vsrc:$XC, u8imm:$IMM),
"xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
[(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
v2i64:$XB, v2i64:$XC, timm:$IMM))]>; v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vclzdm $vD, $vA, $vB", IIC_VecGeneral, "vclzdm $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>;
def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vctzdm $vD, $vA, $vB", IIC_VecGeneral, "vctzdm $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$VD,
(int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>;
def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"cntlzdm $rA, $rS, $rB", IIC_IntGeneral, "cntlzdm $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, [(set i64:$RA,
(int_ppc_cntlzdm i64:$rS, i64:$rB))]>; (int_ppc_cntlzdm i64:$RST, i64:$RB))]>;
def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"cnttzdm $rA, $rS, $rB", IIC_IntGeneral, "cnttzdm $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$rA, [(set i64:$RA,
(int_ppc_cnttzdm i64:$rS, i64:$rB))]>; (int_ppc_cnttzdm i64:$RST, i64:$RB))]>;
def XXGENPCVBM : def XXGENPCVBM :
XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
"xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
def XXGENPCVHM : def XXGENPCVHM :
XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
"xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
def XXGENPCVWM : def XXGENPCVWM :
XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
"xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
def XXGENPCVDM : def XXGENPCVDM :
XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
"xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),
"vclrlb $vD, $vA, $rB", IIC_VecGeneral, "vclrlb $VD, $VA, $VB", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>;
def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),
"vclrrb $vD, $vA, $rB", IIC_VecGeneral, "vclrrb $VD, $VA, $VB", IIC_VecGeneral,
[(set v16i8:$vD, [(set v16i8:$VD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>;
def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulld $vD, $vA, $vB", IIC_VecGeneral, "vmulld $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>;
def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulhsw $vD, $vA, $vB", IIC_VecGeneral, "vmulhsw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>;
def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulhuw $vD, $vA, $vB", IIC_VecGeneral, "vmulhuw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>;
def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulhsd $vD, $vA, $vB", IIC_VecGeneral, "vmulhsd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>;
def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulhud $vD, $vA, $vB", IIC_VecGeneral, "vmulhud $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>;
def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmodsw $vD, $vA, $vB", IIC_VecGeneral, "vmodsw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>;
def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmoduw $vD, $vA, $vB", IIC_VecGeneral, "vmoduw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>;
def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmodsd $vD, $vA, $vB", IIC_VecGeneral, "vmodsd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>;
def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmodud $vD, $vA, $vB", IIC_VecGeneral, "vmodud $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>;
def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivsw $vD, $vA, $vB", IIC_VecGeneral, "vdivsw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>;
def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivuw $vD, $vA, $vB", IIC_VecGeneral, "vdivuw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>;
def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivsd $vD, $vA, $vB", IIC_VecGeneral, "vdivsd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>;
def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivud $vD, $vA, $vB", IIC_VecGeneral, "vdivud $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>; [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>;
def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivesw $vD, $vA, $vB", IIC_VecGeneral, "vdivesw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA, [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA,
v4i32:$vB))]>; v4i32:$VB))]>;
def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdiveuw $vD, $vA, $vB", IIC_VecGeneral, "vdiveuw $VD, $VA, $VB", IIC_VecGeneral,
[(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA, [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA,
v4i32:$vB))]>; v4i32:$VB))]>;
def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivesd $vD, $vA, $vB", IIC_VecGeneral, "vdivesd $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA, [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdiveud $vD, $vA, $vB", IIC_VecGeneral, "vdiveud $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA, [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
"xvtlsbb $BF, $XB", IIC_VecGeneral, []>; "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
// The XFormMemOp flag for the following 8 instructions is set on // The XFormMemOp flag for the following 8 instructions is set on
// the instruction format. // the instruction format.
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
} }
let mayLoad = 0, mayStore = 1 in { let mayLoad = 0, mayStore = 1 in {
def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
} }
def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulesd $vD, $vA, $vB", IIC_VecGeneral, "vmulesd $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA, [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmuleud $vD, $vA, $vB", IIC_VecGeneral, "vmuleud $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA, [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmulosd $vD, $vA, $vB", IIC_VecGeneral, "vmulosd $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA, [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmuloud $vD, $vA, $vB", IIC_VecGeneral, "vmuloud $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA, [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA,
v2i64:$vB))]>; v2i64:$VB))]>;
def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
"vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vmsumcud [(set v1i128:$RT, (int_ppc_altivec_vmsumcud
v2i64:$vA, v2i64:$vB, v1i128:$vC))]>; v2i64:$RA, v2i64:$RB, v1i128:$RC))]>;
def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivsq $vD, $vA, $vB", IIC_VecGeneral, "vdivsq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>;
def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivuq $vD, $vA, $vB", IIC_VecGeneral, "vdivuq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>;
def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdivesq $vD, $vA, $vB", IIC_VecGeneral, "vdivesq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA, [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA,
v1i128:$vB))]>; v1i128:$VB))]>;
def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vdiveuq $vD, $vA, $vB", IIC_VecGeneral, "vdiveuq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA, [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA,
v1i128:$vB))]>; v1i128:$VB))]>;
def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>; def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>;
def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>; def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>;
def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>; def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>;
def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>; def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>;
def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>; def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>;
def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>; def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>;
def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmodsq $vD, $vA, $vB", IIC_VecGeneral, "vmodsq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>;
def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vmoduq $vD, $vA, $vB", IIC_VecGeneral, "vmoduq $VD, $VA, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>; [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>;
def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB), def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB),
"vextsd2q $vD, $vB", IIC_VecGeneral, "vextsd2q $VD, $VB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>; [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>;
def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),
"vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>; "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>;
def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),
"vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>; "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>;
def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
[(set v1i128:$vD, [(set v1i128:$VD,
(int_ppc_altivec_vrlqnm v1i128:$vA, (int_ppc_altivec_vrlqnm v1i128:$VA,
v1i128:$vB))]>; v1i128:$VB))]>;
def VRLQMI : VXForm_1<69, (outs vrrc:$vD), def VRLQMI : VXForm_1<69, (outs vrrc:$VD),
(ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
"vrlqmi $vD, $vA, $vB", IIC_VecFP, "vrlqmi $VD, $VA, $VB", IIC_VecFP,
[(set v1i128:$vD, [(set v1i128:$VD,
(int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB, (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB,
v1i128:$vDi))]>, v1i128:$VDi))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
"lxvkq $XT, $UIM", IIC_VecGeneral, []>; "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
} }
let Predicates = [IsISA3_1, HasVSX] in { let Predicates = [IsISA3_1, HasVSX] in {
def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",
[(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>; [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>;
def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",
[(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>; [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>;
} }
// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. // Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
// This is analogous to the CRNotPat multiclass but specifically for Power10 // This is analogous to the CRNotPat multiclass but specifically for Power10
// and newer subtargets since the extended forms use Set Boolean instructions. // and newer subtargets since the extended forms use Set Boolean instructions.
// The first two anonymous patterns defined are actually a duplicate of those // The first two anonymous patterns defined are actually a duplicate of those
// in CRNotPat, but it is preferable to define both multiclasses as complete // in CRNotPat, but it is preferable to define both multiclasses as complete
// ones rather than pulling that small common section out. // ones rather than pulling that small common section out.
▲ Show 20 Lines • Show All 525 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrSPE.td

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesclass EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
let Inst{21-28} = xo; let Inst{21-28} = xo;
let Inst{29-31} = crD; let Inst{29-31} = crD;
} }
class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr, class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> : InstrItinClass itin, list<dag> pattern> :
I<4, OOL, IOL, asmstr, itin> { I<4, OOL, IOL, asmstr, itin> {
bits<5> RT; bits<5> RT;
bits<21> D; // FIXME: bogus names, to force positional matching for the moment.
bits<21> dst_foo;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{20} = D{0}; let Inst{11-20} = dst_foo{0-9};
let Inst{19} = D{1};
let Inst{18} = D{2};
let Inst{17} = D{3};
let Inst{16} = D{4};
let Inst{15} = D{5};
let Inst{14} = D{6};
let Inst{13} = D{7};
let Inst{12} = D{8};
let Inst{11} = D{9};
let Inst{11-20} = D{0-9};
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
let DecoderNamespace = "SPE", Predicates = [HasSPE] in { let DecoderNamespace = "SPE", Predicates = [HasSPE] in {
def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
"brinc $RT, $RA, $RB", IIC_IntSimple, []>; "brinc $RT, $RA, $RB", IIC_IntSimple, []>;
▲ Show 20 Lines • Show All 315 Lines • ▼ Show 20 Linesdef EVFSTSTGT : EVXForm_3<668, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfststgt $crD, $RA, $RB", IIC_VecGeneral, []>; "evfststgt $crD, $RA, $RB", IIC_VecGeneral, []>;
def EVFSTSTLT : EVXForm_3<669, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB), def EVFSTSTLT : EVXForm_3<669, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"evfststlt $crD, $RA, $RB", IIC_VecGeneral, []>; "evfststlt $crD, $RA, $RB", IIC_VecGeneral, []>;
} }
def EVLDD : EVXForm_D<769, (outs sperc:$RT), (ins spe8dis:$dst), def EVLDD : EVXForm_D<769, (outs sperc:$RT), (ins spe8dis:$dst),
"evldd $RT, $dst", IIC_LdStLoad, "evldd $RT, $dst", IIC_LdStLoad,
[(set f64:$RT, (load iaddr:$dst))]>; [(set f64:$RT, (load iaddr:$dst))]>;
def EVLDDX : EVXForm_1<768, (outs sperc:$RT), (ins memrr:$src), def EVLDDX : EVXForm_1<768, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlddx $RT, $src", IIC_LdStLoad, "evlddx $RT, $src", IIC_LdStLoad,
[(set f64:$RT, (load xaddr:$src))]>; [(set f64:$RT, (load xaddr:$src))]>;
def EVLDH : EVXForm_D<773, (outs sperc:$RT), (ins spe8dis:$dst), def EVLDH : EVXForm_D<773, (outs sperc:$RT), (ins spe8dis:$dst),
"evldh $RT, $dst", IIC_LdStLoad, []>; "evldh $RT, $dst", IIC_LdStLoad, []>;
def EVLDHX : EVXForm_1<772, (outs sperc:$RT), (ins memrr:$src), def EVLDHX : EVXForm_1<772, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evldhx $RT, $src", IIC_LdStLoad, []>; "evldhx $RT, $src", IIC_LdStLoad, []>;
def EVLDW : EVXForm_D<771, (outs sperc:$RT), (ins spe8dis:$dst), def EVLDW : EVXForm_D<771, (outs sperc:$RT), (ins spe8dis:$dst),
"evldw $RT, $dst", IIC_LdStLoad, "evldw $RT, $dst", IIC_LdStLoad,
[]>; []>;
def EVLDWX : EVXForm_1<770, (outs sperc:$RT), (ins memrr:$src), def EVLDWX : EVXForm_1<770, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evldwx $RT, $src", IIC_LdStLoad, "evldwx $RT, $src", IIC_LdStLoad,
[]>; []>;
def EVLHHESPLAT : EVXForm_D<777, (outs sperc:$RT), (ins spe2dis:$dst), def EVLHHESPLAT : EVXForm_D<777, (outs sperc:$RT), (ins spe2dis:$dst),
"evlhhesplat $RT, $dst", IIC_LdStLoad, []>; "evlhhesplat $RT, $dst", IIC_LdStLoad, []>;
def EVLHHESPLATX : EVXForm_1<776, (outs sperc:$RT), (ins memrr:$src), def EVLHHESPLATX : EVXForm_1<776, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlhhesplatx $RT, $src", IIC_LdStLoad, []>; "evlhhesplatx $RT, $src", IIC_LdStLoad, []>;
def EVLHHOUSPLAT : EVXForm_D<781, (outs sperc:$RT), (ins spe2dis:$dst), def EVLHHOUSPLAT : EVXForm_D<781, (outs sperc:$RT), (ins spe2dis:$dst),
"evlhhousplat $RT, $dst", IIC_LdStLoad, []>; "evlhhousplat $RT, $dst", IIC_LdStLoad, []>;
def EVLHHOUSPLATX : EVXForm_1<780, (outs sperc:$RT), (ins memrr:$src), def EVLHHOUSPLATX : EVXForm_1<780, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlhhousplatx $RT, $src", IIC_LdStLoad, []>; "evlhhousplatx $RT, $src", IIC_LdStLoad, []>;
def EVLHHOSSPLAT : EVXForm_D<783, (outs sperc:$RT), (ins spe2dis:$dst), def EVLHHOSSPLAT : EVXForm_D<783, (outs sperc:$RT), (ins spe2dis:$dst),
"evlhhossplat $RT, $dst", IIC_LdStLoad, []>; "evlhhossplat $RT, $dst", IIC_LdStLoad, []>;
def EVLHHOSSPLATX : EVXForm_1<782, (outs sperc:$RT), (ins memrr:$src), def EVLHHOSSPLATX : EVXForm_1<782, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlhhossplatx $RT, $src", IIC_LdStLoad, []>; "evlhhossplatx $RT, $src", IIC_LdStLoad, []>;
def EVLWHE : EVXForm_D<785, (outs sperc:$RT), (ins spe4dis:$dst), def EVLWHE : EVXForm_D<785, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhe $RT, $dst", IIC_LdStLoad, []>; "evlwhe $RT, $dst", IIC_LdStLoad, []>;
def EVLWHEX : EVXForm_1<784, (outs sperc:$RT), (ins memrr:$src), def EVLWHEX : EVXForm_1<784, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlwhex $RT, $src", IIC_LdStLoad, []>; "evlwhex $RT, $src", IIC_LdStLoad, []>;
def EVLWHOS : EVXForm_D<791, (outs sperc:$RT), (ins spe4dis:$dst), def EVLWHOS : EVXForm_D<791, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhos $RT, $dst", IIC_LdStLoad, []>; "evlwhos $RT, $dst", IIC_LdStLoad, []>;
def EVLWHOSX : EVXForm_1<790, (outs sperc:$RT), (ins memrr:$src), def EVLWHOSX : EVXForm_1<790, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlwhosx $RT, $src", IIC_LdStLoad, []>; "evlwhosx $RT, $src", IIC_LdStLoad, []>;
def EVLWHOU : EVXForm_D<789, (outs sperc:$RT), (ins spe4dis:$dst), def EVLWHOU : EVXForm_D<789, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhou $RT, $dst", IIC_LdStLoad, []>; "evlwhou $RT, $dst", IIC_LdStLoad, []>;
def EVLWHOUX : EVXForm_1<788, (outs sperc:$RT), (ins memrr:$src), def EVLWHOUX : EVXForm_1<788, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlwhoux $RT, $src", IIC_LdStLoad, []>; "evlwhoux $RT, $src", IIC_LdStLoad, []>;
def EVLWHSPLAT : EVXForm_D<797, (outs sperc:$RT), (ins spe4dis:$dst), def EVLWHSPLAT : EVXForm_D<797, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwhsplat $RT, $dst", IIC_LdStLoad, []>; "evlwhsplat $RT, $dst", IIC_LdStLoad, []>;
def EVLWHSPLATX : EVXForm_1<796, (outs sperc:$RT), (ins memrr:$src), def EVLWHSPLATX : EVXForm_1<796, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlwhsplatx $RT, $src", IIC_LdStLoad, []>; "evlwhsplatx $RT, $src", IIC_LdStLoad, []>;
def EVLWWSPLAT : EVXForm_D<793, (outs sperc:$RT), (ins spe4dis:$dst), def EVLWWSPLAT : EVXForm_D<793, (outs sperc:$RT), (ins spe4dis:$dst),
"evlwwsplat $RT, $dst", IIC_LdStLoad, []>; "evlwwsplat $RT, $dst", IIC_LdStLoad, []>;
def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins memrr:$src), def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins (memrr $RA, $RB):$src),
"evlwwsplatx $RT, $src", IIC_LdStLoad, []>; "evlwwsplatx $RT, $src", IIC_LdStLoad, []>;
def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>; "evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB), def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB),
"evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>; "evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>; "evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>;
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Linesdef EVSRWS : EVXForm_1<545, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
[]>; []>;
def EVSRWU : EVXForm_1<544, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EVSRWU : EVXForm_1<544, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evsrwu $RT, $RA, $RB", IIC_VecGeneral, "evsrwu $RT, $RA, $RB", IIC_VecGeneral,
[]>; []>;
def EVSTDD : EVXForm_D<801, (outs), (ins sperc:$RT, spe8dis:$dst), def EVSTDD : EVXForm_D<801, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstdd $RT, $dst", IIC_LdStStore, "evstdd $RT, $dst", IIC_LdStStore,
[(store f64:$RT, iaddr:$dst)]>; [(store f64:$RT, iaddr:$dst)]>;
def EVSTDDX : EVXForm_1<800, (outs), (ins sperc:$RT, memrr:$dst), def EVSTDDX : EVXForm_1<800, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstddx $RT, $dst", IIC_LdStStore, "evstddx $RT, $dst", IIC_LdStStore,
[(store f64:$RT, xaddr:$dst)]>; [(store f64:$RT, xaddr:$dst)]>;
def EVSTDH : EVXForm_D<805, (outs), (ins sperc:$RT, spe8dis:$dst), def EVSTDH : EVXForm_D<805, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstdh $RT, $dst", IIC_LdStStore, []>; "evstdh $RT, $dst", IIC_LdStStore, []>;
def EVSTDHX : EVXForm_1<804, (outs), (ins sperc:$RT, memrr:$dst), def EVSTDHX : EVXForm_1<804, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstdhx $RT, $dst", IIC_LdStStore, []>; "evstdhx $RT, $dst", IIC_LdStStore, []>;
def EVSTDW : EVXForm_D<803, (outs), (ins sperc:$RT, spe8dis:$dst), def EVSTDW : EVXForm_D<803, (outs), (ins sperc:$RT, spe8dis:$dst),
"evstdw $RT, $dst", IIC_LdStStore, "evstdw $RT, $dst", IIC_LdStStore,
[]>; []>;
def EVSTDWX : EVXForm_1<802, (outs), (ins sperc:$RT, memrr:$dst), def EVSTDWX : EVXForm_1<802, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstdwx $RT, $dst", IIC_LdStStore, "evstdwx $RT, $dst", IIC_LdStStore,
[]>; []>;
def EVSTWHE : EVXForm_D<817, (outs), (ins sperc:$RT, spe4dis:$dst), def EVSTWHE : EVXForm_D<817, (outs), (ins sperc:$RT, spe4dis:$dst),
"evstwhe $RT, $dst", IIC_LdStStore, []>; "evstwhe $RT, $dst", IIC_LdStStore, []>;
def EVSTWHEX : EVXForm_1<816, (outs), (ins sperc:$RT, memrr:$dst), def EVSTWHEX : EVXForm_1<816, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstwhex $RT, $dst", IIC_LdStStore, []>; "evstwhex $RT, $dst", IIC_LdStStore, []>;
def EVSTWHO : EVXForm_D<821, (outs), (ins sperc:$RT, spe4dis:$dst), def EVSTWHO : EVXForm_D<821, (outs), (ins sperc:$RT, spe4dis:$dst),
"evstwho $RT, $dst", IIC_LdStStore, []>; "evstwho $RT, $dst", IIC_LdStStore, []>;
def EVSTWHOX : EVXForm_1<820, (outs), (ins sperc:$RT, memrr:$dst), def EVSTWHOX : EVXForm_1<820, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstwhox $RT, $dst", IIC_LdStStore, []>; "evstwhox $RT, $dst", IIC_LdStStore, []>;
def EVSTWWE : EVXForm_D<825, (outs), (ins sperc:$RT, spe4dis:$dst), def EVSTWWE : EVXForm_D<825, (outs), (ins sperc:$RT, spe4dis:$dst),
"evstwwe $RT, $dst", IIC_LdStStore, []>; "evstwwe $RT, $dst", IIC_LdStStore, []>;
def EVSTWWEX : EVXForm_1<824, (outs), (ins sperc:$RT, memrr:$dst), def EVSTWWEX : EVXForm_1<824, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstwwex $RT, $dst", IIC_LdStStore, []>; "evstwwex $RT, $dst", IIC_LdStStore, []>;
def EVSTWWO : EVXForm_D<829, (outs), (ins sperc:$RT, spe4dis:$dst), def EVSTWWO : EVXForm_D<829, (outs), (ins sperc:$RT, spe4dis:$dst),
"evstwwo $RT, $dst", IIC_LdStStore, []>; "evstwwo $RT, $dst", IIC_LdStStore, []>;
def EVSTWWOX : EVXForm_1<828, (outs), (ins sperc:$RT, memrr:$dst), def EVSTWWOX : EVXForm_1<828, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst),
"evstwwox $RT, $dst", IIC_LdStStore, []>; "evstwwox $RT, $dst", IIC_LdStStore, []>;
def EVSUBFSSIAAW : EVXForm_2<1219, (outs sperc:$RT), (ins sperc:$RA), def EVSUBFSSIAAW : EVXForm_2<1219, (outs sperc:$RT), (ins sperc:$RA),
"evsubfssiaaw $RT, $RA", IIC_VecComplex, []>; "evsubfssiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFSMIAAW : EVXForm_2<1227, (outs sperc:$RT), (ins sperc:$RA), def EVSUBFSMIAAW : EVXForm_2<1227, (outs sperc:$RT), (ins sperc:$RA),
"evsubfsmiaaw $RT, $RA", IIC_VecComplex, []>; "evsubfsmiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFUMIAAW : EVXForm_2<1226, (outs sperc:$RT), (ins sperc:$RA), def EVSUBFUMIAAW : EVXForm_2<1226, (outs sperc:$RT), (ins sperc:$RA),
"evsubfumiaaw $RT, $RA", IIC_VecComplex, []>; "evsubfumiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFUSIAAW : EVXForm_2<1218, (outs sperc:$RT), (ins sperc:$RA), def EVSUBFUSIAAW : EVXForm_2<1218, (outs sperc:$RT), (ins sperc:$RA),
"evsubfusiaaw $RT, $RA", IIC_VecComplex, []>; "evsubfusiaaw $RT, $RA", IIC_VecComplex, []>;
def EVSUBFW : EVXForm_1<516, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EVSUBFW : EVXForm_1<516, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evsubfw $RT, $RA, $RB", IIC_VecGeneral, "evsubfw $RT, $RA, $RB", IIC_VecGeneral,
[]>; []>;
def EVSUBIFW : EVXForm_1<518, (outs sperc:$RT), (ins u5imm:$RA, sperc:$RB), def EVSUBIFW : EVXForm_1<518, (outs sperc:$RT), (ins u5imm:$RA, sperc:$RB),
"evsubifw $RT, $RA, $RB", IIC_VecGeneral, []>; "evsubifw $RT, $RA, $RB", IIC_VecGeneral, []>;
def EVXOR : EVXForm_1<534, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EVXOR : EVXForm_1<534, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"evxor $RT, $RA, $RB", IIC_VecGeneral, "evxor $RT, $RA, $RB", IIC_VecGeneral,
[]>; []>;
let isAsmParserOnly = 1 in { let isAsmParserOnly = 1 in {
// Identical to the integer Load/Stores, but to handle floats // Identical to the integer Load/Stores, but to handle floats
def SPELWZ : DForm_1<32, (outs spe4rc:$rD), (ins memri:$src), def SPELWZ : DForm_1<32, (outs spe4rc:$RST), (ins memri:$addr),
"lwz $rD, $src", IIC_LdStLoad, "lwz $RST, $addr", IIC_LdStLoad,
[(set f32:$rD, (load iaddr:$src))]>; [(set f32:$RST, (load iaddr:$addr))]>;
def SPELWZX : XForm_1<31, 23, (outs spe4rc:$rD), (ins memrr:$src), def SPELWZX : XForm_1<31, 23, (outs spe4rc:$RST), (ins (memrr $RA, $RB):$addr),
"lwzx $rD, $src", IIC_LdStLoad, "lwzx $RST, $addr", IIC_LdStLoad,
[(set f32:$rD, (load xaddr:$src))]>; [(set f32:$RST, (load xaddr:$addr))]>;
def SPESTW : DForm_1<36, (outs), (ins spe4rc:$rS, memri:$src), def SPESTW : DForm_1<36, (outs), (ins spe4rc:$RST, memri:$addr),
"stw $rS, $src", IIC_LdStStore, "stw $RST, $addr", IIC_LdStStore,
[(store f32:$rS, iaddr:$src)]>; [(store f32:$RST, iaddr:$addr)]>;
def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$rS, memrr:$dst), def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$RST, (memrr $RA, $RB):$addr),
"stwx $rS, $dst", IIC_LdStStore, "stwx $RST, $addr", IIC_LdStStore,
[(store f32:$rS, xaddr:$dst)]>; [(store f32:$RST, xaddr:$addr)]>;
} }
} // HasSPE } // HasSPE
let Predicates = [HasSPE] in { let Predicates = [HasSPE] in {
def SELECT_CC_SPE4 : PPCCustomInserterPseudo<(outs spe4rc:$dst), def SELECT_CC_SPE4 : PPCCustomInserterPseudo<(outs spe4rc:$dst),
(ins crrc:$cond, spe4rc:$T, spe4rc:$F, (ins crrc:$cond, spe4rc:$T, spe4rc:$F,
i32imm:$BROPC), "#SELECT_CC_SPE4", i32imm:$BROPC), "#SELECT_CC_SPE4",
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Linesclass XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> { : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let XB = XA; let XB = XA;
} }
let Predicates = [HasVSX, HasP9Vector] in { let Predicates = [HasVSX, HasP9Vector] in {
class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB), : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vrrc:$RB),
!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;
// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm; : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm;
// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less), // [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
// So we use different operand class for VRB // So we use different operand class for VRB
class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
RegisterOperand vbtype, list<dag> pattern> RegisterOperand vbtype, list<dag> pattern>
: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB), : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vbtype:$RB),
!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;
// [PO VRT XO VRB XO /] // [PO VRT XO VRB XO /]
class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB), : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$RST), (ins vrrc:$RB),
!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>;
// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm; : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm;
// [PO T XO B XO BX /] // [PO T XO B XO BX /]
class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
list<dag> pattern> list<dag> pattern>
: XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB), : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$RT), (ins vsfrc:$XB),
!strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>; !strconcat(opc, " $RT, $XB"), IIC_VecFP, pattern>;
// [PO T XO B XO BX TX] // [PO T XO B XO BX TX]
class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
RegisterOperand vtype, list<dag> pattern> RegisterOperand vtype, list<dag> pattern>
: XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB), : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),
!strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>; !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
// [PO T A B XO AX BX TX], src and dest register use different operand class // [PO T A B XO AX BX TX], src and dest register use different operand class
class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc, class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
RegisterOperand xty, RegisterOperand aty, RegisterOperand bty, RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB), : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
!strconcat(opc, " $XT, $XA, $XB"), itin, pattern>; !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
// [PO VRT VRA VRB XO /] // [PO VRT VRA VRB XO /]
class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB), : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RA, vrrc:$RB),
!strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>; !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>;
// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc, class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm; : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm;
// [PO VRT VRA VRB XO /] // [PO VRT VRA VRB XO /]
class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc, class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB), : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RSTi, vrrc:$RA, vrrc:$RB),
!strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>, !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>,
RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">; RegConstraint<"$RSTi = $RST">, NoEncode<"$RSTi">;
// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc, class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm; : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm;
class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
list<dag> pattern> list<dag> pattern>
: Z23Form_8<opcode, xo, : Z23Form_8<opcode, xo,
(outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc), (outs vrrc:$VRT), (ins u1imm:$R, vrrc:$VRB, u2imm:$idx),
!strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> { !strconcat(opc, " $R, $VRT, $VRB, $idx"), IIC_VecFP, pattern> {
let RC = ex; let RC = ex;
} }
// [PO BF // VRA VRB XO /] // [PO BF // VRA VRB XO /]
class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern> list<dag> pattern>
: XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB), : XForm_17<opcode, xo, (outs crrc:$BF), (ins vrrc:$RA, vrrc:$RB),
!strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> { !strconcat(opc, " $BF, $RA, $RB"), IIC_FPCompare> {
let Pattern = pattern; let Pattern = pattern;
} }
// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
// "out" and "in" dag // "out" and "in" dag
class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
RegisterOperand vtype, list<dag> pattern> RegisterOperand vtype, list<dag> pattern>
: XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src), : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins (memrr $RA, $RB):$addr),
!strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>; !strconcat(opc, " $XT, $addr"), IIC_LdStLFD, pattern>;
// [PO S RA RB XO SX] // [PO S RA RB XO SX]
class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
RegisterOperand vtype, list<dag> pattern> RegisterOperand vtype, list<dag> pattern>
: XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst), : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, (memrr $RA, $RB):$addr),
!strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>; !strconcat(opc, " $XT, $addr"), IIC_LdStSTFD, pattern>;
} // Predicates = HasP9Vector } // Predicates = HasP9Vector
} // AddedComplexity = 400, hasSideEffects = 0 } // AddedComplexity = 400, hasSideEffects = 0
multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> { multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> {
def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>; def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;
def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>; def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;
} }
//-------------------------- Instruction definitions -------------------------// //-------------------------- Instruction definitions -------------------------//
// VSX instructions require the VSX feature, they are to be selected over // VSX instructions require the VSX feature, they are to be selected over
// equivalent Altivec patterns (as they address a larger register set) and // equivalent Altivec patterns (as they address a larger register set) and
// they do not have unmodeled side effects. // they do not have unmodeled side effects.
let Predicates = [HasVSX], AddedComplexity = 400 in { let Predicates = [HasVSX], AddedComplexity = 400 in {
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
// Load indexed instructions // Load indexed instructions
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def LXSDX : XX1Form_memOp<31, 588, def LXSDX : XX1Form_memOp<31, 588,
(outs vsfrc:$XT), (ins memrr:$src), (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxsdx $XT, $src", IIC_LdStLFD, "lxsdx $XT, $addr", IIC_LdStLFD,
[]>; []>;
// Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
let CodeSize = 3 in let CodeSize = 3 in
def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),
"#XFLOADf64", "#XFLOADf64",
[(set f64:$XT, (load XForm:$src))]>; [(set f64:$XT, (load XForm:$addr))]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in let Predicates = [HasVSX, HasOnlySwappingMemOps] in
def LXVD2X : XX1Form_memOp<31, 844, def LXVD2X : XX1Form_memOp<31, 844,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxvd2x $XT, $src", IIC_LdStLFD, "lxvd2x $XT, $addr", IIC_LdStLFD,
[]>; []>;
def LXVDSX : XX1Form_memOp<31, 332, def LXVDSX : XX1Form_memOp<31, 332,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxvdsx $XT, $src", IIC_LdStLFD, []>; "lxvdsx $XT, $addr", IIC_LdStLFD, []>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in let Predicates = [HasVSX, HasOnlySwappingMemOps] in
def LXVW4X : XX1Form_memOp<31, 780, def LXVW4X : XX1Form_memOp<31, 780,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxvw4x $XT, $src", IIC_LdStLFD, "lxvw4x $XT, $addr", IIC_LdStLFD,
[]>; []>;
} // mayLoad } // mayLoad
// Store indexed instructions // Store indexed instructions
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def STXSDX : XX1Form_memOp<31, 716, def STXSDX : XX1Form_memOp<31, 716,
(outs), (ins vsfrc:$XT, memrr:$dst), (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),
"stxsdx $XT, $dst", IIC_LdStSTFD, "stxsdx $XT, $addr", IIC_LdStSTFD,
[]>; []>;
// Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
let CodeSize = 3 in let CodeSize = 3 in
def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),
"#XFSTOREf64", "#XFSTOREf64",
[(store f64:$XT, XForm:$dst)]>; [(store f64:$XT, XForm:$addr)]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in { let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
// The behaviour of this instruction is endianness-specific so we provide no // The behaviour of this instruction is endianness-specific so we provide no
// pattern to match it without considering endianness. // pattern to match it without considering endianness.
def STXVD2X : XX1Form_memOp<31, 972, def STXVD2X : XX1Form_memOp<31, 972,
(outs), (ins vsrc:$XT, memrr:$dst), (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr),
"stxvd2x $XT, $dst", IIC_LdStSTFD, "stxvd2x $XT, $addr", IIC_LdStSTFD,
[]>; []>;
def STXVW4X : XX1Form_memOp<31, 908, def STXVW4X : XX1Form_memOp<31, 908,
(outs), (ins vsrc:$XT, memrr:$dst), (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr),
"stxvw4x $XT, $dst", IIC_LdStSTFD, "stxvw4x $XT, $addr", IIC_LdStSTFD,
[]>; []>;
} }
} // mayStore } // mayStore
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
let Uses = [RM] in { let Uses = [RM] in {
// Add/Mul Instructions // Add/Mul Instructions
let isCommutable = 1 in { let isCommutable = 1 in {
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines def XSREDP : XX2Form<60, 90,
[(set f64:$XT, (PPCfre f64:$XB))]>; [(set f64:$XT, (PPCfre f64:$XB))]>;
def XSRSQRTEDP : XX2Form<60, 74, def XSRSQRTEDP : XX2Form<60, 74,
(outs vsfrc:$XT), (ins vsfrc:$XB), (outs vsfrc:$XT), (ins vsfrc:$XB),
"xsrsqrtedp $XT, $XB", IIC_VecFP, "xsrsqrtedp $XT, $XB", IIC_VecFP,
[(set f64:$XT, (PPCfrsqrte f64:$XB))]>; [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
let mayRaiseFPException = 0 in { let mayRaiseFPException = 0 in {
def XSTDIVDP : XX3Form_1<60, 61, def XSTDIVDP : XX3Form_1<60, 61,
(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),
"xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; "xstdivdp $CR, $XA, $XB", IIC_FPCompare, []>;
def XSTSQRTDP : XX2Form_1<60, 106, def XSTSQRTDP : XX2Form_1<60, 106,
(outs crrc:$crD), (ins vsfrc:$XB), (outs crrc:$CR), (ins vsfrc:$XB),
"xstsqrtdp $crD, $XB", IIC_FPCompare, "xstsqrtdp $CR, $XB", IIC_FPCompare,
[(set i32:$crD, (PPCftsqrt f64:$XB))]>; [(set i32:$CR, (PPCftsqrt f64:$XB))]>;
def XVTDIVDP : XX3Form_1<60, 125, def XVTDIVDP : XX3Form_1<60, 125,
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB),
"xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; "xvtdivdp $CR, $XA, $XB", IIC_FPCompare, []>;
def XVTDIVSP : XX3Form_1<60, 93, def XVTDIVSP : XX3Form_1<60, 93,
(outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB),
"xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>; "xvtdivsp $CR, $XA, $XB", IIC_FPCompare, []>;
def XVTSQRTDP : XX2Form_1<60, 234, def XVTSQRTDP : XX2Form_1<60, 234,
(outs crrc:$crD), (ins vsrc:$XB), (outs crrc:$CR), (ins vsrc:$XB),
"xvtsqrtdp $crD, $XB", IIC_FPCompare, "xvtsqrtdp $CR, $XB", IIC_FPCompare,
[(set i32:$crD, (PPCftsqrt v2f64:$XB))]>; [(set i32:$CR, (PPCftsqrt v2f64:$XB))]>;
def XVTSQRTSP : XX2Form_1<60, 170, def XVTSQRTSP : XX2Form_1<60, 170,
(outs crrc:$crD), (ins vsrc:$XB), (outs crrc:$CR), (ins vsrc:$XB),
"xvtsqrtsp $crD, $XB", IIC_FPCompare, "xvtsqrtsp $CR, $XB", IIC_FPCompare,
[(set i32:$crD, (PPCftsqrt v4f32:$XB))]>; [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>;
} }
def XVDIVDP : XX3Form<60, 120, def XVDIVDP : XX3Form<60, 120,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvdivdp $XT, $XA, $XB", IIC_FPDivD, "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
[(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>; [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>;
def XVDIVSP : XX3Form<60, 88, def XVDIVSP : XX3Form<60, 88,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Show All 24 Lines def XVRSQRTEDP : XX2Form<60, 202,
[(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>; [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
def XVRSQRTESP : XX2Form<60, 138, def XVRSQRTESP : XX2Form<60, 138,
(outs vsrc:$XT), (ins vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XB),
"xvrsqrtesp $XT, $XB", IIC_VecFP, "xvrsqrtesp $XT, $XB", IIC_VecFP,
[(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>; [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
// Compare Instructions // Compare Instructions
def XSCMPODP : XX3Form_1<60, 43, def XSCMPODP : XX3Form_1<60, 43,
(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),
"xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>; "xscmpodp $CR, $XA, $XB", IIC_FPCompare, []>;
def XSCMPUDP : XX3Form_1<60, 35, def XSCMPUDP : XX3Form_1<60, 35,
(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),
"xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>; "xscmpudp $CR, $XA, $XB", IIC_FPCompare, []>;
defm XVCMPEQDP : XX3Form_Rcr<60, 99, defm XVCMPEQDP : XX3Form_Rcr<60, 99,
"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>; int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
defm XVCMPEQSP : XX3Form_Rcr<60, 67, defm XVCMPEQSP : XX3Form_Rcr<60, 67,
"xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>; int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
defm XVCMPGEDP : XX3Form_Rcr<60, 115, defm XVCMPGEDP : XX3Form_Rcr<60, 115,
▲ Show 20 Lines • Show All 350 Lines • ▼ Show 20 Lineslet hasSideEffects = 0 in {
def XXMRGHW : XX3Form<60, 18, def XXMRGHW : XX3Form<60, 18,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>; "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
def XXMRGLW : XX3Form<60, 50, def XXMRGLW : XX3Form<60, 50,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
def XXPERMDI : XX3Form_2<60, 10, def XXPERMDI : XX3Form_2<60, 10,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D),
"xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, "xxpermdi $XT, $XA, $XB, $D", IIC_VecPerm,
[(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB, [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
imm32SExt16:$DM))]>; imm32SExt16:$D))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
// Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which
// is not the same with the input register class(`vsrc`) of XXPERMDI instruction. // is not the same with the input register class(`vsrc`) of XXPERMDI instruction.
// We did this on purpose because: // We did this on purpose because:
// 1: The input is primarily for loads that load a partial vector(LFIWZX, // 1: The input is primarily for loads that load a partial vector(LFIWZX,
// etc.), no need for SUBREG_TO_REG. // etc.), no need for SUBREG_TO_REG.
// 2: With `vsfrc` register class, in the final assembly, float registers // 2: With `vsfrc` register class, in the final assembly, float registers
// like `f0` are used instead of vector scalar register like `vs0`. This // like `f0` are used instead of vector scalar register like `vs0`. This
// helps readability. // helps readability.
def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM), def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D),
"xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; "xxpermdi $XT, $XA, $XA, $D", IIC_VecPerm, []>;
def XXSEL : XX4Form<60, 3, def XXSEL : XX4Form<60, 3,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
"xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
def XXSLDWI : XX3Form_2<60, 2, def XXSLDWI : XX3Form_2<60, 2,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D),
"xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, "xxsldwi $XT, $XA, $XB, $D", IIC_VecPerm,
[(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,
imm32SExt16:$SHW))]>; imm32SExt16:$D))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def XXSLDWIs : XX3Form_2s<60, 2, def XXSLDWIs : XX3Form_2s<60, 2,
(outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D),
"xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; "xxsldwi $XT, $XA, $XA, $D", IIC_VecPerm, []>;
def XXSPLTW : XX2Form_2<60, 164, def XXSPLTW : XX2Form_2<60, 164,
(outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$D),
"xxspltw $XT, $XB, $UIM", IIC_VecPerm, "xxspltw $XT, $XB, $D", IIC_VecPerm,
[(set v4i32:$XT, [(set v4i32:$XT,
(PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>; (PPCxxsplt v4i32:$XB, imm32SExt16:$D))]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def XXSPLTWs : XX2Form_2<60, 164, def XXSPLTWs : XX2Form_2<60, 164,
(outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM), (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$D),
"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; "xxspltw $XT, $XB, $D", IIC_VecPerm, []>;
// The following VSX instructions were introduced in Power ISA 2.07 // The following VSX instructions were introduced in Power ISA 2.07
let Predicates = [HasVSX, HasP8Vector] in { let Predicates = [HasVSX, HasP8Vector] in {
let isCommutable = 1 in { let isCommutable = 1 in {
def XXLEQV : XX3Form<60, 186, def XXLEQV : XX3Form<60, 186,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xxleqv $XT, $XA, $XB", IIC_VecGeneral, "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
[(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>; [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>;
Show All 13 Lineslet Predicates = [HasVSX, HasP8Vector] in {
def XXLORC : XX3Form<60, 170, def XXLORC : XX3Form<60, 170,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xxlorc $XT, $XA, $XB", IIC_VecGeneral, "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
[(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>; [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>;
// VSX scalar loads introduced in ISA 2.07 // VSX scalar loads introduced in ISA 2.07
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src), def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxsspx $XT, $src", IIC_LdStLFD, []>; "lxsspx $XT, $addr", IIC_LdStLFD, []>;
def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src), def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxsiwax $XT, $src", IIC_LdStLFD, []>; "lxsiwax $XT, $addr", IIC_LdStLFD, []>;
def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr),
"lxsiwzx $XT, $src", IIC_LdStLFD, []>; "lxsiwzx $XT, $addr", IIC_LdStLFD, []>;
// Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later
let CodeSize = 3 in let CodeSize = 3 in
def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),
"#XFLOADf32", "#XFLOADf32",
[(set f32:$XT, (load XForm:$src))]>; [(set f32:$XT, (load XForm:$src))]>;
// Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later
def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#LIWAX", "#LIWAX",
[(set f64:$XT, (PPClfiwax ForceXForm:$src))]>; [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>;
// Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later
def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#LIWZX", "#LIWZX",
[(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>; [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>;
} // mayLoad } // mayLoad
// VSX scalar stores introduced in ISA 2.07 // VSX scalar stores introduced in ISA 2.07
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, (memrr $RA, $RB):$addr),
"stxsspx $XT, $dst", IIC_LdStSTFD, []>; "stxsspx $XT, $addr", IIC_LdStSTFD, []>;
def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr),
"stxsiwx $XT, $dst", IIC_LdStSTFD, []>; "stxsiwx $XT, $addr", IIC_LdStSTFD, []>;
// Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later
let CodeSize = 3 in let CodeSize = 3 in
def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),
"#XFSTOREf32", "#XFSTOREf32",
[(store f32:$XT, XForm:$dst)]>; [(store f32:$XT, XForm:$dst)]>;
// Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later
def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lineslet Predicates = [HasVSX, HasP8Vector] in {
// Conversions between vector and scalar single precision // Conversions between vector and scalar single precision
def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB), def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
"xscvdpspn $XT, $XB", IIC_VecFP, []>; "xscvdpspn $XT, $XB", IIC_VecFP, []>;
def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB), def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
"xscvspdpn $XT, $XB", IIC_VecFP, []>; "xscvspdpn $XT, $XB", IIC_VecFP, []>;
let Predicates = [HasVSX, HasDirectMove] in { let Predicates = [HasVSX, HasDirectMove] in {
// VSX direct move instructions // VSX direct move instructions
def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT), def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT),
"mfvsrd $rA, $XT", IIC_VecGeneral, "mfvsrd $RA, $XT", IIC_VecGeneral,
[(set i64:$rA, (PPCmfvsr f64:$XT))]>, [(set i64:$RA, (PPCmfvsr f64:$XT))]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in let isCodeGenOnly = 1, hasSideEffects = 1 in
def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT), def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT),
"mfvsrd $rA, $XT", IIC_VecGeneral, "mfvsrd $RA, $XT", IIC_VecGeneral,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT), def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral, "mfvsrwz $RA, $XT", IIC_VecGeneral,
[(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64; [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in let isCodeGenOnly = 1, hasSideEffects = 1 in
def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT), def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral, "mfvsrwz $RA, $XT", IIC_VecGeneral,
[]>; []>;
def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA), def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA),
"mtvsrd $XT, $rA", IIC_VecGeneral, "mtvsrd $XT, $RA", IIC_VecGeneral,
[(set f64:$XT, (PPCmtvsra i64:$rA))]>, [(set f64:$XT, (PPCmtvsra i64:$RA))]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in let isCodeGenOnly = 1, hasSideEffects = 1 in
def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA), def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA),
"mtvsrd $XT, $rA", IIC_VecGeneral, "mtvsrd $XT, $RA", IIC_VecGeneral,
[]>, []>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA), def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA),
"mtvsrwa $XT, $rA", IIC_VecGeneral, "mtvsrwa $XT, $RA", IIC_VecGeneral,
[(set f64:$XT, (PPCmtvsra i32:$rA))]>; [(set f64:$XT, (PPCmtvsra i32:$RA))]>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in let isCodeGenOnly = 1, hasSideEffects = 1 in
def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA), def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$RA),
"mtvsrwa $XT, $rA", IIC_VecGeneral, "mtvsrwa $XT, $RA", IIC_VecGeneral,
[]>; []>;
def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA), def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$RA),
"mtvsrwz $XT, $rA", IIC_VecGeneral, "mtvsrwz $XT, $RA", IIC_VecGeneral,
[(set f64:$XT, (PPCmtvsrz i32:$rA))]>; [(set f64:$XT, (PPCmtvsrz i32:$RA))]>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in let isCodeGenOnly = 1, hasSideEffects = 1 in
def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA), def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$RA),
"mtvsrwz $XT, $rA", IIC_VecGeneral, "mtvsrwz $XT, $RA", IIC_VecGeneral,
[]>; []>;
} // HasDirectMove } // HasDirectMove
} // HasVSX, HasP8Vector } // HasVSX, HasP8Vector
let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in { let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in {
def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA), def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA),
"mtvsrws $XT, $rA", IIC_VecGeneral, []>; "mtvsrws $XT, $RA", IIC_VecGeneral, []>;
def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB), def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB),
"mtvsrdd $XT, $rA, $rB", IIC_VecGeneral, "mtvsrdd $XT, $RA, $RB", IIC_VecGeneral,
[]>, Requires<[In64BitMode]>; []>, Requires<[In64BitMode]>;
def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT), def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT),
"mfvsrld $rA, $XT", IIC_VecGeneral, "mfvsrld $RA, $XT", IIC_VecGeneral,
[]>, Requires<[In64BitMode]>; []>, Requires<[In64BitMode]>;
} // HasVSX, IsISA3_0, HasDirectMove } // HasVSX, IsISA3_0, HasDirectMove
let Predicates = [HasVSX, HasP9Vector] in { let Predicates = [HasVSX, HasP9Vector] in {
// Quad-Precision Scalar Move Instructions: // Quad-Precision Scalar Move Instructions:
// Copy Sign // Copy Sign
def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
[(set f128:$vT, [(set f128:$RST,
(fcopysign f128:$vB, f128:$vA))]>; (fcopysign f128:$RB, f128:$RA))]>;
// Absolute/Negative-Absolute/Negate // Absolute/Negative-Absolute/Negate
def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp", def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp",
[(set f128:$vT, (fabs f128:$vB))]>; [(set f128:$RST, (fabs f128:$RB))]>;
def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp",
[(set f128:$vT, (fneg (fabs f128:$vB)))]>; [(set f128:$RST, (fneg (fabs f128:$RB)))]>;
def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp", def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",
[(set f128:$vT, (fneg f128:$vB))]>; [(set f128:$RST, (fneg f128:$RB))]>;
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Quad-Precision Scalar Floating-Point Arithmetic Instructions: // Quad-Precision Scalar Floating-Point Arithmetic Instructions:
// Add/Divide/Multiply/Subtract // Add/Divide/Multiply/Subtract
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp", def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp",
[(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>; [(set f128:$RST, (any_fadd f128:$RA, f128:$RB))]>;
def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp", def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp",
[(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>; [(set f128:$RST, (any_fmul f128:$RA, f128:$RB))]>;
} }
def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" ,
[(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>; [(set f128:$RST, (any_fsub f128:$RA, f128:$RB))]>;
def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp", def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp",
[(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>; [(set f128:$RST, (any_fdiv f128:$RA, f128:$RB))]>;
// Square-Root // Square-Root
def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp", def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp",
[(set f128:$vT, (any_fsqrt f128:$vB))]>; [(set f128:$RST, (any_fsqrt f128:$RB))]>;
// (Negative) Multiply-{Add/Subtract} // (Negative) Multiply-{Add/Subtract}
def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp", def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",
[(set f128:$vT, [(set f128:$RST,
(any_fma f128:$vA, f128:$vB, f128:$vTi))]>; (any_fma f128:$RA, f128:$RB, f128:$RSTi))]>;
def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" , def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" ,
[(set f128:$vT, [(set f128:$RST,
(any_fma f128:$vA, f128:$vB, (any_fma f128:$RA, f128:$RB,
(fneg f128:$vTi)))]>; (fneg f128:$RSTi)))]>;
def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp", def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",
[(set f128:$vT, [(set f128:$RST,
(fneg (any_fma f128:$vA, f128:$vB, (fneg (any_fma f128:$RA, f128:$RB,
f128:$vTi)))]>; f128:$RSTi)))]>;
def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp", def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",
[(set f128:$vT, [(set f128:$RST,
(fneg (any_fma f128:$vA, f128:$vB, (fneg (any_fma f128:$RA, f128:$RB,
(fneg f128:$vTi))))]>; (fneg f128:$RSTi))))]>;
let isCommutable = 1 in { let isCommutable = 1 in {
def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_addf128_round_to_odd (int_ppc_addf128_round_to_odd
f128:$vA, f128:$vB))]>; f128:$RA, f128:$RB))]>;
def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_mulf128_round_to_odd (int_ppc_mulf128_round_to_odd
f128:$vA, f128:$vB))]>; f128:$RA, f128:$RB))]>;
} }
def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_subf128_round_to_odd (int_ppc_subf128_round_to_odd
f128:$vA, f128:$vB))]>; f128:$RA, f128:$RB))]>;
def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_divf128_round_to_odd (int_ppc_divf128_round_to_odd
f128:$vA, f128:$vB))]>; f128:$RA, f128:$RB))]>;
def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_sqrtf128_round_to_odd f128:$vB))]>; (int_ppc_sqrtf128_round_to_odd f128:$RB))]>;
def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo", def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo",
[(set f128:$vT, [(set f128:$RST,
(int_ppc_fmaf128_round_to_odd (int_ppc_fmaf128_round_to_odd
f128:$vA,f128:$vB,f128:$vTi))]>; f128:$RA,f128:$RB,f128:$RSTi))]>;
def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" ,
[(set f128:$vT, [(set f128:$RST,
(int_ppc_fmaf128_round_to_odd (int_ppc_fmaf128_round_to_odd
f128:$vA, f128:$vB, (fneg f128:$vTi)))]>; f128:$RA, f128:$RB, (fneg f128:$RSTi)))]>;
def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo",
[(set f128:$vT, [(set f128:$RST,
(fneg (int_ppc_fmaf128_round_to_odd (fneg (int_ppc_fmaf128_round_to_odd
f128:$vA, f128:$vB, f128:$vTi)))]>; f128:$RA, f128:$RB, f128:$RSTi)))]>;
def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo",
[(set f128:$vT, [(set f128:$RST,
(fneg (int_ppc_fmaf128_round_to_odd (fneg (int_ppc_fmaf128_round_to_odd
f128:$vA, f128:$vB, (fneg f128:$vTi))))]>; f128:$RA, f128:$RB, (fneg f128:$RSTi))))]>;
} // mayRaiseFPException } // mayRaiseFPException
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
// QP Compare Ordered/Unordered // QP Compare Ordered/Unordered
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
// DP/QP Compare Exponents // DP/QP Compare Exponents
def XSCMPEXPDP : XX3Form_1<60, 59, def XSCMPEXPDP : XX3Form_1<60, 59,
(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB),
"xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>; "xscmpexpdp $CR, $XA, $XB", IIC_FPCompare, []>;
def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>; def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>;
def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>; def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>;
// DP Compare ==, >=, >, != // DP Compare ==, >=, >, !=
// Use vsrc for XT, because the entire register of XT is set. // Use vsrc for XT, because the entire register of XT is set.
// XT.dword[1] = 0x0000_0000_0000_0000 // XT.dword[1] = 0x0000_0000_0000_0000
def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc, def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
IIC_FPCompare, []>; IIC_FPCompare, []>;
def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc, def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
IIC_FPCompare, []>; IIC_FPCompare, []>;
def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc, def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
IIC_FPCompare, []>; IIC_FPCompare, []>;
} }
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Quad-Precision Floating-Point Conversion Instructions: // Quad-Precision Floating-Point Conversion Instructions:
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
// Convert DP -> QP // Convert DP -> QP
def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,
[(set f128:$vT, (any_fpextend f64:$vB))]>; [(set f128:$RST, (any_fpextend f64:$RB))]>;
// Round & Convert QP -> DP (dword[1] is set to zero) // Round & Convert QP -> DP (dword[1] is set to zero)
def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
[(set f64:$vT, [(set f64:$RST,
(int_ppc_truncf128_round_to_odd (int_ppc_truncf128_round_to_odd
f128:$vB))]>; f128:$RB))]>;
} }
// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>; def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>; def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>; def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>; def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>;
Show All 32 Lineslet Predicates = [HasVSX, HasP9Vector] in {
def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>; def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Insert/Extract Instructions // Insert/Extract Instructions
// Insert Exponent DP/QP // Insert Exponent DP/QP
// XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$RA, g8rc:$RB),
"xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>; "xsiexpdp $XT, $RA, $RB", IIC_VecFP, []>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
// vB NOTE: only vB.dword[0] is used, that's why we don't use // vB NOTE: only vB.dword[0] is used, that's why we don't use
// X_VT5_VA5_VB5 form // X_VT5_VA5_VB5 form
def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB), def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$FRT), (ins vrrc:$FRA, vsfrc:$FRB),
"xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>; "xsiexpqp $FRT, $FRA, $FRB", IIC_VecFP, []>;
} }
// Extract Exponent/Significand DP/QP // Extract Exponent/Significand DP/QP
def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>; def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>;
def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>; def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>;
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>; def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>;
def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>; def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>;
} }
// Vector Insert Word // Vector Insert Word
// XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
def XXINSERTW : def XXINSERTW :
XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
(ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM), (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM5),
"xxinsertw $XT, $XB, $UIM", IIC_VecFP, "xxinsertw $XT, $XB, $UIM5", IIC_VecFP,
[(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB, [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,
imm32SExt16:$UIM))]>, imm32SExt16:$UIM5))]>,
RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
// Vector Extract Unsigned Word // Vector Extract Unsigned Word
// FIXME: Setting the hasSideEffects flag here to match current behaviour. // FIXME: Setting the hasSideEffects flag here to match current behaviour.
let hasSideEffects = 1 in let hasSideEffects = 1 in
def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
(outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM), (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIM5),
"xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>; "xxextractuw $XT, $XB, $UIM5", IIC_VecFP, []>;
// Vector Insert Exponent DP/SP // Vector Insert Exponent DP/SP
def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>; IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;
def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc, def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
// Vector Extract Exponent/Significand DP/SP // Vector Extract Exponent/Significand DP/SP
Show All 15 Lineslet Predicates = [HasVSX, HasP9Vector] in {
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298, def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
(outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
"xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>; "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362, def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
(outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
"xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708,
(outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB), (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$VB),
"xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>; "xststdcqp $BF, $VB, $DCMX", IIC_VecFP, []>;
} }
// Vector Test Data Class SP/DP // Vector Test Data Class SP/DP
def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
"xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
[(set v4i32: $XT, [(set v4i32: $XT,
(int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>; (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>;
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lineslet Predicates = [HasVSX, HasP9Vector] in {
let hasSideEffects = 1 in let hasSideEffects = 1 in
def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
"xxspltib $XT, $IMM8", IIC_VecPerm, []>; "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
let mayLoad = 1, mayStore = 0 in { let mayLoad = 1, mayStore = 0 in {
// Load Vector // Load Vector
def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$addr),
"lxv $XT, $src", IIC_LdStLFD, []>; "lxv $XT, $addr", IIC_LdStLFD, []>;
// Load DWord // Load DWord
def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src), def LXSD : DSForm_1<57, 2, (outs vfrc:$RST), (ins memrix:$addr),
"lxsd $vD, $src", IIC_LdStLFD, []>; "lxsd $RST, $addr", IIC_LdStLFD, []>;
// Load SP from src, convert it to DP, and place in dword[0] // Load SP from src, convert it to DP, and place in dword[0]
def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src), def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins memrix:$addr),
"lxssp $vD, $src", IIC_LdStLFD, []>; "lxssp $RST, $addr", IIC_LdStLFD, []>;
// Load as Integer Byte/Halfword & Zero Indexed // Load as Integer Byte/Halfword & Zero Indexed
def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,
[(set f64:$XT, (PPClxsizx ForceXForm:$src, 1))]>; [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 1))]>;
def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc,
[(set f64:$XT, (PPClxsizx ForceXForm:$src, 2))]>; [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 2))]>;
// Load Vector Halfword*8/Byte*16 Indexed // Load Vector Halfword*8/Byte*16 Indexed
def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;
def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;
// Load Vector Indexed // Load Vector Indexed
def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc,
[(set v2f64:$XT, (load XForm:$src))]>; [(set v2f64:$XT, (load XForm:$addr))]>;
// Load Vector (Left-justified) with Length // Load Vector (Left-justified) with Length
def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),
"lxvl $XT, $src, $rB", IIC_LdStLoad, "lxvl $XT, $addr, $RB", IIC_LdStLoad,
[(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>; [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$addr, i64:$RB))]>;
def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),
"lxvll $XT, $src, $rB", IIC_LdStLoad, "lxvll $XT, $addr, $RB", IIC_LdStLoad,
[(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>; [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$addr, i64:$RB))]>;
// Load Vector Word & Splat Indexed // Load Vector Word & Splat Indexed
def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
} // mayLoad } // mayLoad
// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
// Store Vector // Store Vector
def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$addr),
"stxv $XT, $dst", IIC_LdStSTFD, []>; "stxv $XT, $addr", IIC_LdStSTFD, []>;
// Store DWord // Store DWord
def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst), def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$RST, memrix:$addr),
"stxsd $vS, $dst", IIC_LdStSTFD, []>; "stxsd $RST, $addr", IIC_LdStSTFD, []>;
// Convert DP of dword[0] to SP, and Store to dst // Convert DP of dword[0] to SP, and Store to dst
def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst), def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, memrix:$addr),
"stxssp $vS, $dst", IIC_LdStSTFD, []>; "stxssp $RST, $addr", IIC_LdStSTFD, []>;
// Store as Integer Byte/Halfword Indexed // Store as Integer Byte/Halfword Indexed
def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc,
[(PPCstxsix f64:$XT, ForceXForm:$dst, 1)]>; [(PPCstxsix f64:$XT, ForceXForm:$addr, 1)]>;
def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc,
[(PPCstxsix f64:$XT, ForceXForm:$dst, 2)]>; [(PPCstxsix f64:$XT, ForceXForm:$addr, 2)]>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>; def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>;
def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>; def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>;
} }
// Store Vector Halfword*8/Byte*16 Indexed // Store Vector Halfword*8/Byte*16 Indexed
def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>;
def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;
// Store Vector Indexed // Store Vector Indexed
def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc,
[(store v2f64:$XT, XForm:$dst)]>; [(store v2f64:$XT, XForm:$addr)]>;
// Store Vector (Left-justified) with Length // Store Vector (Left-justified) with Length
def STXVL : XX1Form_memOp<31, 397, (outs), def STXVL : XX1Form_memOp<31, 397, (outs),
(ins vsrc:$XT, memr:$dst, g8rc:$rB), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
"stxvl $XT, $dst, $rB", IIC_LdStLoad, "stxvl $XT, $addr, $RB", IIC_LdStLoad,
[(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, [(int_ppc_vsx_stxvl v4i32:$XT, addr:$addr,
i64:$rB)]>; i64:$RB)]>;
def STXVLL : XX1Form_memOp<31, 429, (outs), def STXVLL : XX1Form_memOp<31, 429, (outs),
(ins vsrc:$XT, memr:$dst, g8rc:$rB), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
"stxvll $XT, $dst, $rB", IIC_LdStLoad, "stxvll $XT, $addr, $RB", IIC_LdStLoad,
[(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, [(int_ppc_vsx_stxvll v4i32:$XT, addr:$addr,
i64:$rB)]>; i64:$RB)]>;
} // mayStore } // mayStore
def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src),
"#DFLOADf32", "#DFLOADf32",
[(set f32:$XT, (load DSForm:$src))]>; [(set f32:$XT, (load DSForm:$src))]>;
def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src), def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src),
"#DFLOADf64", "#DFLOADf64",
[(set f64:$XT, (load DSForm:$src))]>; [(set f64:$XT, (load DSForm:$src))]>;
▲ Show 20 Lines • Show All 3,410 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Show First 20 Lines • Show All 865 Lines • ▼ Show 20 Lines
def PPCDispSPE2Operand : AsmOperandClass { def PPCDispSPE2Operand : AsmOperandClass {
let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
} }
def dispSPE2 : Operand<iPTR> { def dispSPE2 : Operand<iPTR> {
let ParserMatchClass = PPCDispSPE2Operand; let ParserMatchClass = PPCDispSPE2Operand;
} }
// FIXME: Remove the functions like getMemRIEncoding and decodeMemRIOperands,
// and adjust the instruction definitions. There's no need to artificially merge
// the values into a single field anymore, now that sub-operands can be named in
// instruction definitions.
def memri : Operand<iPTR> { def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm"; let PrintMethod = "printMemRegImm";
let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
let EncoderMethod = "getMemRIEncoding"; let EncoderMethod = "getMemRIEncoding";
let DecoderMethod = "decodeMemRIOperands"; let DecoderMethod = "decodeMemRIOperands";
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def memrr : Operand<iPTR> { def memrr : Operand<iPTR> {
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines