[TargetLowering] Do not shrink shift amount in ShrinkDemandedOp

[bcl5980]

Summary

Shift amout is determined by TLI.getShiftAmountTy. We can't truncate it.

[bcl5980]

I haven't find any real case to test it. Does anyone has suggestion for that?

[craig.topper]

This is only called for constant shift amounts. Won't LegalizeDAG fix it if DAG combine changes it after legalization? Have you seen a failure in a larger test?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

586

amout->amount

588

This function is never called for SRL or SRA.

[bcl5980]

In D137481#3910229, @craig.topper wrote:

This is only called for constant shift amounts. Won't LegalizeDAG fix it if DAG combine changes it after legalization? Have you seen a failure in a larger test?

The motivation of this change comes from D136014. I compare two shift amount by apint trigged an assert. It happens in DAGCombiner, LegalizeDAG haven't executed yet.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
   unsigned DemandedSize = Demanded.getActiveBits();
   unsigned SmallVTBits = DemandedSize;
   if (!isPowerOf2_32(SmallVTBits))
     SmallVTBits = NextPowerOf2(SmallVTBits);
   for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
     EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
     if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
         TLI.isZExtFree(SmallVT, Op.getValueType())) {
+      SDValue RHS = Op.getOperand(1);
+      // Shift amout type is determined by TLI.getShiftAmountTy,
+      // we can't truncate here because it will cause type mismatch.
+      if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL &&
+          Op.getOpcode() != ISD::SRA)
+        RHS = DAG.getNode(ISD::TRUNCATE, dl, SmallVT, RHS);
       // We found a type with free casts.
       SDValue X = DAG.getNode(
           Op.getOpcode(), dl, SmallVT,
-          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
-          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
+          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), RHS);
       assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
       SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
       return TLO.CombineTo(Op, Z);
     }
   }
   return false;
 }