[LoongArch] Fix codegen for [su]itofp instructions

[wangleiat]

Summary

This patch fixes codegen for [su]itofp instructions.

In LoongArch, a legal int-to-float conversion is done in two steps:

1. Move the data from GPR to FPR. (FRLen >= GRLen)
2. Conversion in FPR. (the data in FPR is treated as a signed value)

Based on the above features, when the type's BitWidth meets the
requirements, all SINT_TO_FP are legal, all UINT_TO_FP are expand
and lowered to libcall when appropriate.
The only special case is, LoongArch64 with +f,-d features. At this
point, custom processing is required for [SU]INT_TO_FP. Of course, we
can also ignore it and use libcall directly.

[xen0n]

Seems we're using the same methodology recently... namely trying to bootstrap a native LLVM toolchain with LLVM/Clang themselves. Because I've seen the same crash yesterday night. Thanks for catching this.

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

290

sexti32 for uint? (I might be sleepy so this might not be wrong after all.) The codegen in the touched test cases look good though, this is a bit weird.

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

216–220

This makes me feel a bit nervous, because we conventionally use such bstrpick insns for zero extensions. The MSB immediate is tested to be strictly less than 32 so this is actually a guaranteed zero extension. Are we doing the right thing by matching the case in sexti32 too?

[xen0n]

Fixed formatting of commit message for you.

Note that there seems to be widespread misuse of [] and {} shorthand notations among Loongson people: they come from shell syntax, and should look like [abc], [a-c], {a,b} or {,a}, never [a/b] or {a/b}. Please keep this in mind (even the LoongArch ISA manual got this wrong, IMO it's better to tell someone to amend the manual instead of allowing the current practice last indefinitely).

[wangleiat]

In D136916#3893657, @xen0n wrote:

Fixed formatting of commit message for you.

Note that there seems to be widespread misuse of [] and {} shorthand notations among Loongson people: they come from shell syntax, and should look like [abc], [a-c], {a,b} or {,a}, never [a/b] or {a/b}. Please keep this in mind (even the LoongArch ISA manual got this wrong, IMO it's better to tell someone to amend the manual instead of allowing the current practice last indefinitely).

Thanks!

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

290

sexti32 for uint? (I might be sleepy so this might not be wrong after all.) The codegen in the touched test cases look good though, this is a bit weird.

sexti32 means, can we treat the current node as a signed number.

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

216–220

This makes me feel a bit nervous, because we conventionally use such bstrpick insns for zero extensions. The MSB immediate is tested to be strictly less than 32 so this is actually a guaranteed zero extension. Are we doing the right thing by matching the case in sexti32 too?

Yes, but when it only takes 31 bits, it can be considered either sign extension or zero extension.

[wangleiat]

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

290

sexti32 for uint? (I might be sleepy so this might not be wrong after all.) The codegen in the touched test cases look good though, this is a bit weird.

sexti32 means, can we treat the current node as a signed number.

In fact, this matching rule only appears when loongarch64 +f -d, but I don't want to add the corresponding hasNoBasicD() feature, and the corresponding legality judgment has been made in the lowering stage. (In theory, this constraint can be removed.)

[xen0n]

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

290

sexti32 for uint? (I might be sleepy so this might not be wrong after all.) The codegen in the touched test cases look good though, this is a bit weird.

sexti32 means, can we treat the current node as a signed number.

In fact, this matching rule only appears when loongarch64 +f -d, but I don't want to add the corresponding hasNoBasicD() feature, and the corresponding legality judgment has been made in the lowering stage. (In theory, this constraint can be removed.)

Okay, so we can put off this for a while, knowing that you're well aware of the details (better than I am)... Feel free to come back to polish it later.

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

216–220

Fair enough. Thanks for the explanation.

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

 
 let Predicates = [HasBasicF, IsLA64] in {
 // GPR -> FPR
 def : Pat<(loongarch_movgr2fr_w_la64 GPR:$src), (MOVGR2FR_W GPR:$src)>;
 // FPR -> GPR
 def : Pat<(loongarch_movfr2gr_s_la64 FPR32:$src),
           (MOVFR2GR_S FPR32:$src)>;
 // int -> f32
-def : Pat<(f32 (sint_to_fp GPR:$src)), (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
+def : Pat<(f32 (sint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
+          (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
+// uint -> f32
+def : Pat<(f32 (uint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
+          (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
 } // Predicates = [HasBasicF, IsLA64]
 
 // FP Rounding
 let Predicates = [HasBasicF, IsLA64] in {
 def : PatFpr<frint, FRINT_S, FPR32>;
 } // Predicates = [HasBasicF, IsLA64]
 
 let Predicates = [HasBasicF, IsLA32] in {
 // GPR -> FPR
 def : Pat<(bitconvert (i32 GPR:$src)), (MOVGR2FR_W GPR:$src)>;
 // FPR -> GPR
 def : Pat<(i32 (bitconvert FPR32:$src)), (MOVFR2GR_S FPR32:$src)>;
 // int -> f32
 def : Pat<(f32 (sint_to_fp (i32 GPR:$src))), (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
 } // Predicates = [HasBasicF, IsLA32]

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 def : Pat<(f64 fpimm0), (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0)>;
 def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0))>;
 def : Pat<(f64 fpimm1), (FCVT_D_S (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1))))>;
 } // Predicates = [HasBasicD, IsLA32]
 
 /// Convert int to FP
 
 let Predicates = [HasBasicD, IsLA64] in {
+def : Pat<(f32 (sint_to_fp GPR:$src)), (FFINT_S_L (MOVGR2FR_D GPR:$src))>;
 def : Pat<(f64 (sint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
           (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
 def : Pat<(f64 (sint_to_fp GPR:$src)), (FFINT_D_L (MOVGR2FR_D GPR:$src))>;
 
-def : Pat<(f64 (uint_to_fp (i64 (zexti32 (i64 GPR:$src))))),
-          (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
-
 def : Pat<(bitconvert GPR:$src), (MOVGR2FR_D GPR:$src)>;
 } // Predicates = [HasBasicD, IsLA64]
 let Predicates = [HasBasicD, IsLA32] in {
 def : Pat<(f64 (sint_to_fp (i32 GPR:$src))), (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
 } // Predicates = [HasBasicD, IsLA32]
 
 // Convert FP to int
 let Predicates = [HasBasicD, IsLA64] in {
 def : Pat<(bitconvert FPR64:$src), (MOVFR2GR_D FPR64:$src)>;
 } // Predicates = [HasBasicD, IsLA64]
 
 // FP Rounding
 let Predicates = [HasBasicD, IsLA64] in {
 def : PatFpr<frint, FRINT_D, FPR64>;
 } // Predicates = [HasBasicD, IsLA64]

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

 }
 
 bool LoongArchDAGToDAGISel::selectSExti32(SDValue N, SDValue &Val) {
   if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
       cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) {
     Val = N.getOperand(0);
     return true;
   }
+  if (N.getOpcode() == LoongArchISD::BSTRPICK &&
+      N.getConstantOperandVal(1) < UINT64_C(0X1F) &&
+      N.getConstantOperandVal(2) == UINT64_C(0)) {
+    Val = N;
+    return true;
+  }
   MVT VT = N.getSimpleValueType();
   if (CurDAG->ComputeNumSignBits(N) > (VT.getSizeInBits() - 32)) {
     Val = N;
     return true;
   }
 
   return false;
 }

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

private:
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

 #include "LoongArchMachineFunctionInfo.h"
 #include "LoongArchRegisterInfo.h"
 #include "LoongArchSubtarget.h"
 #include "LoongArchTargetMachine.h"
 #include "MCTargetDesc/LoongArchBaseInfo.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/IntrinsicsLoongArch.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/KnownBits.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch-isel-lowering"
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::BR_CC, GRLenVT, Expand);
   setOperationAction(ISD::SELECT_CC, GRLenVT, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, GRLenVT, Expand);
   if (!Subtarget.is64Bit())
     setLibcallName(RTLIB::MUL_I128, nullptr);
 
   setOperationAction(ISD::FP_TO_UINT, GRLenVT, Custom);
+  setOperationAction(ISD::UINT_TO_FP, GRLenVT, Expand);
+  if ((Subtarget.is64Bit() && Subtarget.hasBasicF() &&
+       !Subtarget.hasBasicD())) {
+    setOperationAction(ISD::SINT_TO_FP, GRLenVT, Custom);
     setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom);
+  }
 
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
 
   setStackPointerRegisterToSaveRestore(LoongArch::R3);
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
   case ISD::FP_TO_SINT:
     return lowerFP_TO_SINT(Op, DAG);
   case ISD::BITCAST:
     return lowerBITCAST(Op, DAG);
   case ISD::UINT_TO_FP:
     return lowerUINT_TO_FP(Op, DAG);
+  case ISD::SINT_TO_FP:
+    return lowerSINT_TO_FP(Op, DAG);
   case ISD::VASTART:
     return lowerVASTART(Op, DAG);
   case ISD::FRAMEADDR:
     return lowerFRAMEADDR(Op, DAG);
   case ISD::RETURNADDR:
     return lowerRETURNADDR(Op, DAG);
   }
   return SDValue();
SDValue LoongArchTargetLowering::lowerVASTART(SDValue Op,
   // memory location argument.
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
                       MachinePointerInfo(SV));
 }
 
 SDValue LoongArchTargetLowering::lowerUINT_TO_FP(SDValue Op,
                                                  SelectionDAG &DAG) const {
+  assert(Subtarget.is64Bit() && Subtarget.hasBasicF() &&
+         !Subtarget.hasBasicD() && "unexpected target features");
 
   SDLoc DL(Op);
-  auto &TLI = DAG.getTargetLoweringInfo();
-  SDValue Tmp1, Tmp2;
-  SDValue Op1 = Op.getOperand(0);
-  if (Op1->getOpcode() == ISD::AssertZext ||
-      Op1->getOpcode() == ISD::AssertSext)
+  SDValue Op0 = Op.getOperand(0);
+  if (Op0->getOpcode() == ISD::AND) {
+    auto *C = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
+    if (C && C->getZExtValue() < UINT64_C(0xFFFFFFFF))
       return Op;
-  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op.getOperand(0));
-  SDValue Res = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f64, Trunc);
-  SDNode *N = Res.getNode();
-  TLI.expandUINT_TO_FP(N, Tmp1, Tmp2, DAG);
-  return Tmp1;
+  }
+
+  if (Op0->getOpcode() == LoongArchISD::BSTRPICK &&
+      Op0.getConstantOperandVal(1) < UINT64_C(0X1F) &&
+      Op0.getConstantOperandVal(2) == UINT64_C(0))
+    return Op;
+
+  if (Op0.getOpcode() == ISD::AssertZext &&
+      dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLT(MVT::i32))
+    return Op;
+
+  EVT OpVT = Op0.getValueType();
+  EVT RetVT = Op.getValueType();
+  RTLIB::Libcall LC = RTLIB::getUINTTOFP(OpVT, RetVT);
+  MakeLibCallOptions CallOptions;
+  CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true);
+  SDValue Chain = SDValue();
+  SDValue Result;
+  std::tie(Result, Chain) =
+      makeLibCall(DAG, LC, Op.getValueType(), Op0, CallOptions, DL, Chain);
+  return Result;
+}
+
+SDValue LoongArchTargetLowering::lowerSINT_TO_FP(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  assert(Subtarget.is64Bit() && Subtarget.hasBasicF() &&
+         !Subtarget.hasBasicD() && "unexpected target features");
+
+  SDLoc DL(Op);
+  SDValue Op0 = Op.getOperand(0);
+
+  if ((Op0.getOpcode() == ISD::AssertSext ||
+       Op0.getOpcode() == ISD::SIGN_EXTEND_INREG) &&
+      dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32))
+    return Op;
+
+  EVT OpVT = Op0.getValueType();
+  EVT RetVT = Op.getValueType();
+  RTLIB::Libcall LC = RTLIB::getSINTTOFP(OpVT, RetVT);
+  MakeLibCallOptions CallOptions;
+  CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true);
+  SDValue Chain = SDValue();
+  SDValue Result;
+  std::tie(Result, Chain) =
+      makeLibCall(DAG, LC, Op.getValueType(), Op0, CallOptions, DL, Chain);
+  return Result;
 }
 
 SDValue LoongArchTargetLowering::lowerBITCAST(SDValue Op,
                                               SelectionDAG &DAG) const {
 
   SDLoc DL(Op);
   SDValue Op0 = Op.getOperand(0);
 

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

 ; LA32-NEXT:    fld.d $fa0, $a0, 0
 ; LA32-NEXT:    fld.d $fa1, $sp, 8
 ; LA32-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u32_to_double:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI12_0)
-; LA64-NEXT:    addi.d $a1, $a1, %pc_lo12(.LCPI12_0)
-; LA64-NEXT:    fld.d $fa0, $a1, 0
-; LA64-NEXT:    lu52i.d $a1, $zero, 1107
-; LA64-NEXT:    movgr2fr.d $fa1, $a1
-; LA64-NEXT:    fsub.d $fa0, $fa1, $fa0
-; LA64-NEXT:    lu12i.w $a1, 275200
-; LA64-NEXT:    bstrins.d $a0, $a1, 63, 32
-; LA64-NEXT:    movgr2fr.d $fa1, $a0
-; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
+; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    movgr2fr.d $fa0, $a0
+; LA64-NEXT:    ffint.d.l $fa0, $fa0
 ; LA64-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }
 
 define double @convert_u64_to_double(i64 %a) nounwind {
 ; LA32-LABEL: convert_u64_to_double:
 ; LA32:       # %bb.0:

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

 ; LA32D-LABEL: convert_i32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i32_to_float:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    addi.w $a0, $a0, 0
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i32_to_float:
 ; LA64D:       # %bb.0:
-; LA64D-NEXT:    addi.w $a0, $a0, 0
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64D-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @convert_i64_to_float(i64 %a) nounwind {

 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl %plt(__floatdisf)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i64_to_float:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    movgr2fr.w $fa0, $a0
-; LA64F-NEXT:    ffint.s.w $fa0, $fa0
+; LA64F-NEXT:    addi.d $sp, $sp, -16
+; LA64F-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64F-NEXT:    bl %plt(__floatdisf)
+; LA64F-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 16
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i64_to_float:
 ; LA64D:       # %bb.0:
-; LA64D-NEXT:    movgr2fr.w $fa0, $a0
-; LA64D-NEXT:    ffint.s.w $fa0, $fa0
+; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    ffint.s.l $fa0, $fa0
 ; LA64D-NEXT:    ret
   %1 = sitofp i64 %a to float
   ret float %1
 }
 
 define float @convert_u8_to_float(i8 zeroext %a) nounwind {
 ; LA32F-LABEL: convert_u8_to_float:
 ; LA32F:       # %bb.0:

 ; LA32D-NEXT:    fld.d $fa1, $sp, 8
 ; LA32D-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32D-NEXT:    fcvt.s.d $fa0, $fa0
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u32_to_float:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    bstrpick.d $a1, $a0, 31, 1
-; LA64F-NEXT:    andi $a2, $a0, 1
-; LA64F-NEXT:    or $a1, $a2, $a1
-; LA64F-NEXT:    movgr2fr.w $fa0, $a1
-; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    fadd.s $fa0, $fa0, $fa0
+; LA64F-NEXT:    addi.d $sp, $sp, -16
+; LA64F-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64F-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; LA64F-NEXT:    slti $a1, $a0, 0
-; LA64F-NEXT:    movgr2cf $fcc0, $a1
-; LA64F-NEXT:    movgr2fr.w $fa1, $a0
-; LA64F-NEXT:    ffint.s.w $fa1, $fa1
-; LA64F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA64F-NEXT:    bl %plt(__floatundisf)
+; LA64F-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 16
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u32_to_float:
 ; LA64D:       # %bb.0:
-; LA64D-NEXT:    bstrpick.d $a1, $a0, 31, 1
-; LA64D-NEXT:    andi $a2, $a0, 1
-; LA64D-NEXT:    or $a1, $a2, $a1
-; LA64D-NEXT:    movgr2fr.w $fa0, $a1
-; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64D-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; LA64D-NEXT:    slti $a1, $a0, 0
-; LA64D-NEXT:    movgr2cf $fcc0, $a1
-; LA64D-NEXT:    movgr2fr.w $fa1, $a0
-; LA64D-NEXT:    ffint.s.w $fa1, $fa1
-; LA64D-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    ffint.s.l $fa0, $fa0
 ; LA64D-NEXT:    ret
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @convert_u64_to_float(i64 %a) nounwind {
 ; LA32F-LABEL: convert_u64_to_float:
 ; LA32F:       # %bb.0:

 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl %plt(__floatundisf)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u64_to_float:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    srli.d $a1, $a0, 1
-; LA64F-NEXT:    andi $a2, $a0, 1
-; LA64F-NEXT:    or $a1, $a2, $a1
-; LA64F-NEXT:    movgr2fr.w $fa0, $a1
-; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    fadd.s $fa0, $fa0, $fa0
-; LA64F-NEXT:    slti $a1, $a0, 0
-; LA64F-NEXT:    movgr2cf $fcc0, $a1
-; LA64F-NEXT:    movgr2fr.w $fa1, $a0
-; LA64F-NEXT:    ffint.s.w $fa1, $fa1
-; LA64F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA64F-NEXT:    addi.d $sp, $sp, -16
+; LA64F-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64F-NEXT:    bl %plt(__floatundisf)
+; LA64F-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 16
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u64_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    srli.d $a1, $a0, 1
 ; LA64D-NEXT:    andi $a2, $a0, 1
 ; LA64D-NEXT:    or $a1, $a2, $a1
-; LA64D-NEXT:    movgr2fr.w $fa0, $a1
-; LA64D-NEXT:    ffint.s.w $fa0, $fa0
+; LA64D-NEXT:    movgr2fr.d $fa0, $a1
+; LA64D-NEXT:    ffint.s.l $fa0, $fa0
 ; LA64D-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64D-NEXT:    slti $a1, $a0, 0
 ; LA64D-NEXT:    movgr2cf $fcc0, $a1
-; LA64D-NEXT:    movgr2fr.w $fa1, $a0
-; LA64D-NEXT:    ffint.s.w $fa1, $fa1
+; LA64D-NEXT:    movgr2fr.d $fa1, $a0
+; LA64D-NEXT:    ffint.s.l $fa1, $fa1
 ; LA64D-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
 ; LA64D-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define i32 @bitcast_float_to_i32(float %a) nounwind {
 ; LA32F-LABEL: bitcast_float_to_i32: