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Differential D136422

[ARM] Fix the type for v4f16 duplane
ClosedPublic

Authored by dmgreen on Oct 21 2022, 12:20 AM.

Details

Reviewers
samtebbs
lenary
SjoerdMeijer
labrinea
Commits
rGfb76d2ce6c4e: [ARM] Fix the type for v4f16 duplane
Summary

This was previously using the 32bit variant of the instruction, instead of the 16bit as intended.

Fixes #58512

Diff Detail

Event Timeline

dmgreen created this revision.Oct 21 2022, 12:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 12:20 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Oct 21 2022, 12:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 12:20 AM
Harbormaster completed remote builds in B193436: Diff 469484.Oct 21 2022, 12:20 AM
SjoerdMeijer accepted this revision.Oct 21 2022, 12:48 AM

Yeah, this looks a lot better.

This revision is now accepted and ready to land.Oct 21 2022, 12:48 AM
This revision was landed with ongoing or failed builds.Oct 21 2022, 2:10 AM
Closed by commit rGfb76d2ce6c4e: [ARM] Fix the type for v4f16 duplane (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGfb76d2ce6c4e: [ARM] Fix the type for v4f16 duplane.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
test/
CodeGen/
ARM/
2 lines

Diff 469514

llvm/lib/Target/ARM/ARMInstrNEON.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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} }
def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> { def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
bits<1> lane; bits<1> lane;
let Inst{19} = lane{0}; let Inst{19} = lane{0};
} }
let Predicates = [HasNEON] in { let Predicates = [HasNEON] in {
def : Pat<(v4f16 (ARMvduplane (v4f16 DPR:$Vm), imm:$lane)), def : Pat<(v4f16 (ARMvduplane (v4f16 DPR:$Vm), imm:$lane)),
(VDUPLN32d DPR:$Vm, imm:$lane)>; (VDUPLN16d DPR:$Vm, imm:$lane)>;
def : Pat<(v2f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)), def : Pat<(v2f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)),
(VDUPLN32d DPR:$Vm, imm:$lane)>; (VDUPLN32d DPR:$Vm, imm:$lane)>;
def : Pat<(v4f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)), def : Pat<(v4f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)),
(VDUPLN32q DPR:$Vm, imm:$lane)>; (VDUPLN32q DPR:$Vm, imm:$lane)>;
def : Pat<(v16i8 (ARMvduplane (v16i8 QPR:$src), imm:$lane)), def : Pat<(v16i8 (ARMvduplane (v16i8 QPR:$src), imm:$lane)),
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llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

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%vecinit = insertelement <8 x half> undef, half %1, i32 0 %vecinit = insertelement <8 x half> undef, half %1, i32 0
%vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer %vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer
ret <8 x half> %vecinit8 ret <8 x half> %vecinit8
} }
define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> %a) { define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> %a) {
; CHECK-LABEL: test_vdup_lane_f16: ; CHECK-LABEL: test_vdup_lane_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdup.32 d0, d0[3] ; CHECK-NEXT: vdup.16 d0, d0[3]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
ret <4 x half> %shuffle ret <4 x half> %shuffle
} }
define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> %a) { define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> %a) {
; CHECK-LABEL: test_vdupq_lane_f16: ; CHECK-LABEL: test_vdupq_lane_f16:
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