[ARM] Support fp16/bf16 using w constraint

[lenary]

Summary

fp16 and bf16 values can be used in GCC's inline assembly using the "w"
constraint, which means "VFP floating-point registers d0-d31" - fp16 and
bf16 values are stored in S registers (which alias the D registers).

This change ensures that LLVM is compatible with GCC for programs that
use fp16 and the 'w' constraint.

[lenary]

This is a follow-up to https://reviews.llvm.org/D134553 where we noticed that the "w" constraint support was similarly missing, like the "t" constraint, for fp16. https://gcc.godbolt.org/z/vfzzf8ajz shows GCC working in this case.

[DavidSpickett]

LGTM, thanks.

llvm/lib/Target/ARM/ARMISelLowering.cpp

case 'h': // High regs or no regs.
       break;
     case 'r':
       if (Subtarget->isThumb1Only())
         return RCPair(0U, &ARM::tGPRRegClass);
       return RCPair(0U, &ARM::GPRRegClass);
     case 'w':
       if (VT == MVT::Other)
         break;
+      if (VT == MVT::f16 || VT == MVT::bf16)
+        return RCPair(0U, &ARM::HPRRegClass);
       if (VT == MVT::f32)
         return RCPair(0U, &ARM::SPRRegClass);
       if (VT.getSizeInBits() == 64)
         return RCPair(0U, &ARM::DPRRegClass);
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, &ARM::QPRRegClass);
       break;
     case 'x':

llvm/test/CodeGen/ARM/inlineasm-fp-half.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm -mattr=+armv8.2-a,+fp-armv8,+fullfp16,+bf16,-neon %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumb -mattr=+armv8.2-a,+fp-armv8,+fullfp16,+bf16,-neon %s -o - | FileCheck %s
 
 
-define arm_aapcscc half @f(half %x) nounwind {
-; CHECK-LABEL: f:
+define arm_aapcscc half @f_t(half %x) nounwind {
+; CHECK-LABEL: f_t:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.f16 s0, r0
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    vsqrt.f16 s0, s0
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = tail call half asm "vsqrt.f16 $0, $1", "=t,t"(half %x)
   ret half %0
 }
 
-define arm_aapcscc bfloat @h(bfloat %x) nounwind {
-; CHECK-LABEL: h:
+define arm_aapcscc half @f_w(half %x) nounwind {
+; CHECK-LABEL: f_w:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.f16 s0, r0
+; CHECK-NEXT:    @APP
+; CHECK-NEXT:    vsqrt.f16 s0, s0
+; CHECK-NEXT:    @NO_APP
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call half asm "vsqrt.f16 $0, $1", "=w,w"(half %x)
+  ret half %0
+}
+
+define arm_aapcscc bfloat @h_t(bfloat %x) nounwind {
+; CHECK-LABEL: h_t:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.f16 s0, r0
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    vmov.f32 s0, s0
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = tail call bfloat asm "vmov.f32 $0, $1", "=t,t"(bfloat %x)
   ret bfloat %0
 }
+
+define arm_aapcscc bfloat @h_w(bfloat %x) nounwind {
+; CHECK-LABEL: h_w:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.f16 s0, r0
+; CHECK-NEXT:    @APP
+; CHECK-NEXT:    vmov.f32 s0, s0
+; CHECK-NEXT:    @NO_APP
+; CHECK-NEXT:    vmov.f16 r0, s0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call bfloat asm "vmov.f32 $0, $1", "=w,w"(bfloat %x)
+  ret bfloat %0
+}