[LoongArch] Add earlyclobber of destination register to atomic instructions

[gonglingqin]

Summary

If the AM* atomic memory access instruction has the same register number as
rd and rj, the execution will trigger an Instruction Non-defined Exception.
If the AM* atomic memory access instruction has the same register number as
rd and rk, the execution result is uncertain.

Reference: https://github.com/loongson/LoongArch-Documentation

[xry111]

Why didn't we notice this before? :(

[gonglingqin]

In D135641#3848541, @xry111 wrote:

Why didn't we notice this before? :(

It's really easy to ignore this problem until the executable starts running:)

[xen0n]

In D135641#3848541, @xry111 wrote:

Why didn't we notice this before? :(

Of course it's because RISCV AMO doesn't have this implementation feature/detail/quirk/wart (pick one suitable for you) ;-)

[xry111]

In D135641#3848627, @xen0n wrote:

In D135641#3848541, @xry111 wrote:

Why didn't we notice this before? :(

Of course it's because RISCV AMO doesn't have this implementation feature/detail/quirk/wart (pick one suitable for you) ;-)

I mean I had spent some time to find a way for describing our "feature" (or whatever) last year, and found "earlyclobber": https://github.com/xry111/llvm-project/blob/d4c6b92/llvm/lib/Target/LoongArch/LoongArchInstrInfoA.td#L42

So basically "why didn't I notice it before" :(.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 class STORE_2RI12<bits<10> op, string opstr>
     : Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12_addlike:$imm12), opstr,
                "$rd, $rj, $imm12">;
 class STORE_2RI14<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14), opstr,
                "$rd, $rj, $imm14">;
 } // mayStore = 1
 
-let mayLoad = 1, mayStore = 1 in
+let mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
 class AM_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPR:$rj), opstr, "$rd, $rk, $rj">;
 
 let mayLoad = 1 in
 class LLBase<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
                "$rd, $rj, $imm14">;
 

llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll

 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB2_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_xchg_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amswap_db.w $a0, $a1, $a0
+; LA64-NEXT:    amswap_db.w $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw xchg ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_xchg_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_exchange_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_xchg_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amswap_db.d $a0, $a1, $a0
+; LA64-NEXT:    amswap_db.d $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw xchg ptr %a, i64 %b acquire
   ret i64 %1
 }
 
 define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-LABEL: atomicrmw_add_i8_acquire:
 ; LA32:       # %bb.0:

 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB6_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_add_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amadd_db.w $a0, $a1, $a0
+; LA64-NEXT:    amadd_db.w $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw add ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_add_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_fetch_add_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_add_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amadd_db.d $a0, $a1, $a0
+; LA64-NEXT:    amadd_db.d $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw add ptr %a, i64 %b acquire
   ret i64 %1
 }
 
 define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-LABEL: atomicrmw_sub_i8_acquire:
 ; LA32:       # %bb.0:

 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB10_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_sub_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    sub.w $a1, $zero, $a1
-; LA64-NEXT:    amadd_db.w $a0, $a1, $a0
+; LA64-NEXT:    sub.w $a2, $zero, $a1
+; LA64-NEXT:    amadd_db.w $a1, $a2, $a0
+; LA64-NEXT:    move $a0, $a1
 ; LA64-NEXT:    ret
   %1 = atomicrmw sub ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_sub_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_fetch_sub_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_sub_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    sub.d $a1, $zero, $a1
-; LA64-NEXT:    amadd_db.d $a0, $a1, $a0
+; LA64-NEXT:    sub.d $a2, $zero, $a1
+; LA64-NEXT:    amadd_db.d $a1, $a2, $a0
+; LA64-NEXT:    move $a0, $a1
 ; LA64-NEXT:    ret
   %1 = atomicrmw sub ptr %a, i64 %b acquire
   ret i64 %1
 }
 
 define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-LABEL: atomicrmw_nand_i8_acquire:
 ; LA32:       # %bb.0:

 ; LA64-NEXT:    slli.d $a2, $a0, 3
 ; LA64-NEXT:    ori $a3, $zero, 255
 ; LA64-NEXT:    sll.w $a3, $a3, $a2
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    sll.w $a1, $a1, $a2
 ; LA64-NEXT:    orn $a1, $a1, $a3
 ; LA64-NEXT:    addi.w $a3, $zero, -4
 ; LA64-NEXT:    and $a0, $a0, $a3
-; LA64-NEXT:    amand_db.w $a0, $a1, $a0
-; LA64-NEXT:    srl.w $a0, $a0, $a2
+; LA64-NEXT:    amand_db.w $a3, $a1, $a0
+; LA64-NEXT:    srl.w $a0, $a3, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i8 %b acquire
   ret i8 %1
 }
 
 define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
 ; LA32-LABEL: atomicrmw_and_i16_acquire:
 ; LA32:       # %bb.0:

 ; LA64-NEXT:    ori $a2, $a2, 4095
 ; LA64-NEXT:    slli.d $a3, $a0, 3
 ; LA64-NEXT:    sll.w $a2, $a2, $a3
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    sll.w $a1, $a1, $a3
 ; LA64-NEXT:    orn $a1, $a1, $a2
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a0, $a0, $a2
-; LA64-NEXT:    amand_db.w $a0, $a1, $a0
-; LA64-NEXT:    srl.w $a0, $a0, $a3
+; LA64-NEXT:    amand_db.w $a2, $a1, $a0
+; LA64-NEXT:    srl.w $a0, $a2, $a3
 ; LA64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i16 %b acquire
   ret i16 %1
 }
 
 define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32-LABEL: atomicrmw_and_i32_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    and $a3, $a2, $a0
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB18_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_and_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amand_db.w $a0, $a1, $a0
+; LA64-NEXT:    amand_db.w $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_and_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_fetch_and_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_and_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amand_db.d $a0, $a1, $a0
+; LA64-NEXT:    amand_db.d $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw and ptr %a, i64 %b acquire
   ret i64 %1
 }
 
 define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-LABEL: atomicrmw_or_i8_acquire:
 ; LA32:       # %bb.0:

 ;
 ; LA64-LABEL: atomicrmw_or_i8_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a2, $a0, $a2
 ; LA64-NEXT:    slli.d $a0, $a0, 3
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
-; LA64-NEXT:    amor_db.w $a1, $a1, $a2
-; LA64-NEXT:    srl.w $a0, $a1, $a0
+; LA64-NEXT:    amor_db.w $a3, $a1, $a2
+; LA64-NEXT:    srl.w $a0, $a3, $a0
 ; LA64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i8 %b acquire
   ret i8 %1
 }
 
 define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
 ; LA32-LABEL: atomicrmw_or_i16_acquire:
 ; LA32:       # %bb.0:

 ;
 ; LA64-LABEL: atomicrmw_or_i16_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a2, $a0, $a2
 ; LA64-NEXT:    slli.d $a0, $a0, 3
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
-; LA64-NEXT:    amor_db.w $a1, $a1, $a2
-; LA64-NEXT:    srl.w $a0, $a1, $a0
+; LA64-NEXT:    amor_db.w $a3, $a1, $a2
+; LA64-NEXT:    srl.w $a0, $a3, $a0
 ; LA64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i16 %b acquire
   ret i16 %1
 }
 
 define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32-LABEL: atomicrmw_or_i32_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    or $a3, $a2, $a0
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB22_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_or_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amor_db.w $a0, $a1, $a0
+; LA64-NEXT:    amor_db.w $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_or_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_fetch_or_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_or_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amor_db.d $a0, $a1, $a0
+; LA64-NEXT:    amor_db.d $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw or ptr %a, i64 %b acquire
   ret i64 %1
 }
 
 define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
 ; LA32-LABEL: atomicrmw_xor_i8_acquire:
 ; LA32:       # %bb.0:

 ;
 ; LA64-LABEL: atomicrmw_xor_i8_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a2, $a0, $a2
 ; LA64-NEXT:    slli.d $a0, $a0, 3
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
-; LA64-NEXT:    amxor_db.w $a1, $a1, $a2
-; LA64-NEXT:    srl.w $a0, $a1, $a0
+; LA64-NEXT:    amxor_db.w $a3, $a1, $a2
+; LA64-NEXT:    srl.w $a0, $a3, $a0
 ; LA64-NEXT:    ret
   %1 = atomicrmw xor ptr %a, i8 %b acquire
   ret i8 %1
 }
 
 define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
 ; LA32-LABEL: atomicrmw_xor_i16_acquire:
 ; LA32:       # %bb.0:

 ;
 ; LA64-LABEL: atomicrmw_xor_i16_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a2, $a0, $a2
 ; LA64-NEXT:    slli.d $a0, $a0, 3
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
-; LA64-NEXT:    amxor_db.w $a1, $a1, $a2
-; LA64-NEXT:    srl.w $a0, $a1, $a0
+; LA64-NEXT:    amxor_db.w $a3, $a1, $a2
+; LA64-NEXT:    srl.w $a0, $a3, $a0
 ; LA64-NEXT:    ret
   %1 = atomicrmw xor ptr %a, i16 %b acquire
   ret i16 %1
 }
 
 define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32-LABEL: atomicrmw_xor_i32_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    xor $a3, $a2, $a0
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beq $a3, $zero, .LBB26_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_xor_i32_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amxor_db.w $a0, $a1, $a0
+; LA64-NEXT:    amxor_db.w $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw xor ptr %a, i32 %b acquire
   ret i32 %1
 }
 
 define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: atomicrmw_xor_i64_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    ori $a3, $zero, 2
 ; LA32-NEXT:    bl %plt(__atomic_fetch_xor_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_xor_i64_acquire:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    amxor_db.d $a0, $a1, $a0
+; LA64-NEXT:    amxor_db.d $a2, $a1, $a0
+; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw xor ptr %a, i64 %b acquire
   ret i64 %1
 }