This is an archive of the discontinued LLVM Phabricator instance.

Differential D135380

[GlobalISel] Combine (X op Y) == X --> Y == 0
ClosedPublic

Authored by paquette on Oct 6 2022, 11:13 AM.

Details

Reviewers
aemerson
arsenm
Commits
rG036a13065b7a: [GlobalISel] Combine (X op Y) == X --> Y == 0
Summary

This matches patterns of the form

(X op Y) == X

And transforms them to

Y == 0

where appropriate.

Example: https://godbolt.org/z/hfW811c7W

Diff Detail

Event Timeline

paquette created this revision.Oct 6 2022, 11:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 6 2022, 11:13 AM
Herald added subscribers: hiraditya, rovka. · View Herald Transcript
paquette requested review of this revision.Oct 6 2022, 11:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 6 2022, 11:13 AM
Herald added a subscriber: wdng. · View Herald Transcript
paquette added a parent revision: D135378: [GlobalISel] Add a m_SpecificReg matcher.Oct 6 2022, 11:13 AM
arsenm added inline comments.Oct 6 2022, 12:49 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6075

Can you really get away without checking the mi_match result?

6087–6088

Should there be commutative variants of the matchers like in the IR version?

Harbormaster completed remote builds in B190770: Diff 465795.Oct 6 2022, 12:49 PM
paquette added inline comments.Oct 6 2022, 1:05 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6087–6088

Yeah, something for G_ICMP on eq/ne would be useful. The binops already commute.

tschuett added a subscriber: tschuett.Oct 6 2022, 1:09 PM
tschuett added inline comments.
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6075

There is no [[nodiscard]] on mi_match?

paquette added inline comments.Oct 6 2022, 1:57 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6075

I didn't get a warning, but maybe other compilers would warn?

(I should add an assert that MI is a G_ICMP at the top though)

paquette added inline comments.Oct 6 2022, 2:08 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6087–6088

I think for a commutative matcher to make an impact here we'd need to be able to write like

if (!mi_match(Dst, MRI,
              m_GICmp(m_Pred(Pred), m_Reg(X),
                      m_any_of(m_GAdd(m_SpecificReg(X), m_Reg(Y)),
                               m_GSub(m_SpecificReg(X), m_Reg(Y)),
                               m_GXor(m_SpecificReg(X), m_Reg(Y))))) ||
    !ICmpInst::isEquality(Pred))
  return false;

But I don't think that it's guaranteed that m_Reg(X) will be evaluated before m_SpecificReg(X)?

paquette mentioned this in D135415: [GlobalISel] Add commutative matchers for compares..Oct 6 2022, 5:00 PM
paquette updated this revision to Diff 465939.Oct 6 2022, 5:24 PM

Update to use D135415

Harbormaster completed remote builds in B190858: Diff 465939.Oct 6 2022, 5:24 PM
paquette edited parent revisions, added: D135415: [GlobalISel] Add commutative matchers for compares.; removed: D135378: [GlobalISel] Add a m_SpecificReg matcher.Oct 6 2022, 5:24 PM
arsenm added inline comments.Oct 7 2022, 7:12 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6083

Not using the _c_ versions?

paquette updated this revision to Diff 466241.Oct 7 2022, 8:23 PM

Use shiny new commutative matcher

Harbormaster completed remote builds in B191062: Diff 466241.Oct 7 2022, 8:24 PM
arsenm added inline comments.Oct 7 2022, 9:11 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6079

I'm not seeing why sub needs to be handled as a separate case

paquette added inline comments.Oct 7 2022, 9:18 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
6079

The Y = X == OpLHS ? OpRHS : X == OpRHS ? OpLHS : Register(); part would be wrong for sub because sub is noncommutative.

arsenm accepted this revision.Oct 7 2022, 9:54 PM
This revision is now accepted and ready to land.Oct 7 2022, 9:54 PM
This revision was landed with ongoing or failed builds.Oct 11 2022, 9:53 AM
Closed by commit rG036a13065b7a: [GlobalISel] Combine (X op Y) == X --> Y == 0 (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG036a13065b7a: [GlobalISel] Combine (X op Y) == X --> Y == 0.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
9 lines
Target/
GlobalISel/
8 lines
lib/
CodeGen/
GlobalISel/
33 lines
test/
CodeGen/
AArch64/
GlobalISel/
863 lines

Diff 466845

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 762 Lines • ▼ Show 20 Linespublic:
/// x - (y + x) -> 0 - y /// x - (y + x) -> 0 - y
/// x - (x + z) -> 0 - z /// x - (x + z) -> 0 - z
bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo); bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo);
/// \returns true if it is possible to simplify a select instruction \p MI /// \returns true if it is possible to simplify a select instruction \p MI
/// to a min/max instruction of some sort. /// to a min/max instruction of some sort.
bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo); bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo);
/// Transform:
/// (X + Y) == X -> Y == 0
/// (X - Y) == X -> Y == 0
/// (X ^ Y) == X -> Y == 0
/// (X + Y) != X -> Y != 0
/// (X - Y) != X -> Y != 0
/// (X ^ Y) != X -> Y != 0
bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo);
private: private:
/// Given a non-indexed load or store instruction \p MI, find an offset that /// Given a non-indexed load or store instruction \p MI, find an offset that
/// can be usefully and legally folded into it as a post-indexing operation. /// can be usefully and legally folded into it as a post-indexing operation.
/// ///
/// \returns true if a candidate is found. /// \returns true if a candidate is found.
bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base, bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
Register &Offset); Register &Offset);
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 730 Lines • ▼ Show 20 Linesdef icmp_to_true_false_known_bits : GICombineRule<
(apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>; (apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>;
def icmp_to_lhs_known_bits : GICombineRule< def icmp_to_lhs_known_bits : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_ICMP):$root, (match (wip_match_opcode G_ICMP):$root,
[{ return Helper.matchICmpToLHSKnownBits(*${root}, ${info}); }]), [{ return Helper.matchICmpToLHSKnownBits(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def redundant_binop_in_equality : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_ICMP):$root,
[{ return Helper.matchRedundantBinOpInEquality(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def and_or_disjoint_mask : GICombineRule< def and_or_disjoint_mask : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_AND):$root, (match (wip_match_opcode G_AND):$root,
[{ return Helper.matchAndOrDisjointMask(*${root}, ${info}); }]), [{ return Helper.matchAndOrDisjointMask(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFnNoErase(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFnNoErase(*${root}, ${info}); }])>;
def bitfield_extract_from_and : GICombineRule< def bitfield_extract_from_and : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Linesdef all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl, unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero, const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine, shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
truncstore_merge, div_rem_to_divrem, funnel_shift_combines, truncstore_merge, div_rem_to_divrem, funnel_shift_combines,
form_bitfield_extract, constant_fold, fabs_fneg_fold, form_bitfield_extract, constant_fold, fabs_fneg_fold,
intdiv_combines, mulh_combines, redundant_neg_operands, intdiv_combines, mulh_combines, redundant_neg_operands,
and_or_disjoint_mask, fma_combines, fold_binop_into_select, and_or_disjoint_mask, fma_combines, fold_binop_into_select,
sub_add_reg, select_to_minmax]>; sub_add_reg, select_to_minmax, redundant_binop_in_equality]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in // A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and // this group have been selected based on experiments to balance code size and
// compile time performance. // compile time performance.
def optnone_combines : GICombineGroup<[trivial_combines, def optnone_combines : GICombineGroup<[trivial_combines,
ptr_add_immed_chain, combines_for_extload, ptr_add_immed_chain, combines_for_extload,
not_cmp_fold, opt_brcond_by_inverting_cond]>; not_cmp_fold, opt_brcond_by_inverting_cond]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show All 21 Lines
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterBankInfo.h" #include "llvm/CodeGen/RegisterBankInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DataLayout.h" #include "llvm/IR/DataLayout.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include "llvm/Support/DivisionByConstantInfo.h" #include "llvm/Support/DivisionByConstantInfo.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include <cmath> #include <cmath>
#include <tuple> #include <tuple>
#define DEBUG_TYPE "gi-combiner" #define DEBUG_TYPE "gi-combiner"
▲ Show 20 Lines • Show All 6,017 Lines • ▼ Show 20 Linesbool CombinerHelper::matchSimplifySelectToMinMax(MachineInstr &MI,
if (mi_match(Cond, MRI, m_OneNonDBGUse(m_GTrunc(m_Reg(MaybeTrunc))))) if (mi_match(Cond, MRI, m_OneNonDBGUse(m_GTrunc(m_Reg(MaybeTrunc)))))
Cond = MaybeTrunc; Cond = MaybeTrunc;
Register Dst = MI.getOperand(0).getReg(); Register Dst = MI.getOperand(0).getReg();
Register TrueVal = MI.getOperand(2).getReg(); Register TrueVal = MI.getOperand(2).getReg();
Register FalseVal = MI.getOperand(3).getReg(); Register FalseVal = MI.getOperand(3).getReg();
return matchFPSelectToMinMax(Dst, Cond, TrueVal, FalseVal, MatchInfo); return matchFPSelectToMinMax(Dst, Cond, TrueVal, FalseVal, MatchInfo);
} }
bool CombinerHelper::matchRedundantBinOpInEquality(MachineInstr &MI,
BuildFnTy &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_ICMP);
// (X + Y) == X --> Y == 0
// (X + Y) != X --> Y != 0
// (X - Y) == X --> Y == 0
// (X - Y) != X --> Y != 0
// (X ^ Y) == X --> Y == 0
// (X ^ Y) != X --> Y != 0
Register Dst = MI.getOperand(0).getReg();
CmpInst::Predicate Pred;
Register X, Y, OpLHS, OpRHS;
arsenmUnsubmitted
Not Done
ReplyInline Actions

Can you really get away without checking the mi_match result?

arsenm: Can you really get away without checking the mi_match result?
tschuettUnsubmitted
Not Done
ReplyInline Actions

There is no [[nodiscard]] on mi_match?

tschuett: There is no `[[nodiscard]]` on `mi_match`?
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

I didn't get a warning, but maybe other compilers would warn?

(I should add an assert that MI is a G_ICMP at the top though)

paquette: I didn't get a warning, but maybe other compilers would warn? (I should add an assert that…
bool MatchedSub = mi_match(
Dst, MRI,
m_c_GICmp(m_Pred(Pred), m_Reg(X), m_GSub(m_Reg(OpLHS), m_Reg(Y))));
if (MatchedSub && X != OpLHS)
arsenmUnsubmitted
Not Done
ReplyInline Actions

I'm not seeing why sub needs to be handled as a separate case

arsenm: I'm not seeing why sub needs to be handled as a separate case
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

The Y = X == OpLHS ? OpRHS : X == OpRHS ? OpLHS : Register(); part would be wrong for sub because sub is noncommutative.

paquette: The `Y = X == OpLHS ? OpRHS : X == OpRHS ? OpLHS : Register();` part would be wrong for sub…
return false;
if (!MatchedSub) {
if (!mi_match(Dst, MRI,
m_c_GICmp(m_Pred(Pred), m_Reg(X),
arsenmUnsubmitted
Not Done
ReplyInline Actions

Not using the _c_ versions?

arsenm: Not using the _c_ versions?
m_any_of(m_GAdd(m_Reg(OpLHS), m_Reg(OpRHS)),
m_GXor(m_Reg(OpLHS), m_Reg(OpRHS))))))
return false;
Y = X == OpLHS ? OpRHS : X == OpRHS ? OpLHS : Register();
}
arsenmUnsubmitted
Not Done
ReplyInline Actions

Should there be commutative variants of the matchers like in the IR version?

arsenm: Should there be commutative variants of the matchers like in the IR version?
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

Yeah, something for G_ICMP on eq/ne would be useful. The binops already commute.

paquette: Yeah, something for G_ICMP on eq/ne would be useful. The binops already commute.
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

I think for a commutative matcher to make an impact here we'd need to be able to write like

if (!mi_match(Dst, MRI,
              m_GICmp(m_Pred(Pred), m_Reg(X),
                      m_any_of(m_GAdd(m_SpecificReg(X), m_Reg(Y)),
                               m_GSub(m_SpecificReg(X), m_Reg(Y)),
                               m_GXor(m_SpecificReg(X), m_Reg(Y))))) ||
    !ICmpInst::isEquality(Pred))
  return false;

But I don't think that it's guaranteed that m_Reg(X) will be evaluated before m_SpecificReg(X)?

paquette: I think for a commutative matcher to make an impact here we'd need to be able to write like…
MatchInfo = [=](MachineIRBuilder &B) {
auto Zero = B.buildConstant(MRI.getType(Y), 0);
B.buildICmp(Pred, Dst, Y, Zero);
};
return CmpInst::isEquality(Pred) && Y.isValid();
}
bool CombinerHelper::tryCombine(MachineInstr &MI) { bool CombinerHelper::tryCombine(MachineInstr &MI) {
if (tryCombineCopy(MI)) if (tryCombineCopy(MI))
return true; return true;
if (tryCombineExtendingLoads(MI)) if (tryCombineExtendingLoads(MI))
return true; return true;
if (tryCombineIndexedLoadStore(MI)) if (tryCombineIndexedLoadStore(MI))
return true; return true;
return false; return false;
} }

llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
# Test:
# (X + Y) == X --> Y == 0
# (X - Y) == X --> Y == 0
# (X ^ Y) == X --> Y == 0
# (X + Y) != X --> Y != 0
# (X - Y) != X --> Y != 0
# (X ^ Y) != X --> Y != 0
#
# And all commuted cases.
...
---
name: add_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %y, %x
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %y, %x
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: dont_combine_sub_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: dont_combine_sub_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %op:_(s32) = G_SUB %y, %x
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: dont_combine_sub_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: dont_combine_sub_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: %op:_(<4 x s32>) = G_SUB %y, %x
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: dont_combine_not_equality
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: dont_combine_not_equality
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %op:_(s32) = G_ADD %x, %y
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(slt), %op(s32), %x
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(slt), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: dont_combine_unique_operands
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: dont_combine_unique_operands
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %z:_(s32) = COPY $w2
; CHECK-NEXT: %op:_(s32) = G_ADD %x, %y
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %z
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%z:_(s32) = COPY $w2
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %z
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0