[PowerPC] Fix invalid cast for vector shuffles when lowering to the xxsplti32dx instruction.

[amyk]

Summary

When lowering vector shuffles into the xxsplti32dx instruction on Power10, we canonicalize the
right operand to be a BUILD_VECTOR and as a result, get the commuted vector shuffle node.

However, a vector shuffle will not always be returned as the result for a commuted vector shuffle.
In such a scenario, this patch updates the original cast of a shuffle into a dyn_cast<> and checks if
the shuffle is a valid vector shuffle node prior to obtaining the commuted shuffle mask.

This patch also adds a new test case that demonstrates this scenario (primarily seen on 32-bit), and
was originally a crash prior to this fix.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll

35–60

These register spills are not seen with any other target in the test case. Is this maybe an artifact of the test case, or something else? What happens on Linux 64 BE?

[nemanjai]

llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll

35–60

Seems unrelated to this patch but nonetheless it is bad. @amyk can you please pre-commit the test case?

[amyk]

Rebase the patch to add 32-bit run lines in pre-commit test case (rG22e4203df813a8051b40adb3e2872e30fdbe1bbe)

[amyk]

llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll

35–60

@ZarkoCA @nemanjai Good catch! Thanks, both of you.

So, I've pre-committed the test case with 64-bit Linux (LE and BE) and AIX lines initially. I could not add the 32-bit run lines since they crash (and this patch aims to fix the 32-bit crash).

As we can see with the 64-bit CHECKs, the spills aren't present anymore and they don't seem to be related to my patch, so maybe there was something causing it before that got fixed?

[ZarkoCA]

Thanks for fixing this and for pre-comitting the test case.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::lowerToXXSPLTI32DX(ShuffleVectorSDNode *SVN,
 
   // Check that we have a four byte shuffle.
   if (!isNByteElemShuffleMask(SVN, 4, 1))
     return SDValue();
 
   // Canonicalize the RHS being a BUILD_VECTOR when lowering to xxsplti32dx.
   if (RHS->getOpcode() != ISD::BUILD_VECTOR) {
     std::swap(LHS, RHS);
-    VecShuffle = DAG.getCommutedVectorShuffle(*SVN);
-    ShuffleMask = cast<ShuffleVectorSDNode>(VecShuffle)->getMask();
+    VecShuffle = peekThroughBitcasts(DAG.getCommutedVectorShuffle(*SVN));
+    ShuffleVectorSDNode *CommutedSV = dyn_cast<ShuffleVectorSDNode>(VecShuffle);
+    if (!CommutedSV)
+      return SDValue();
+    ShuffleMask = CommutedSV->getMask();
   }
 
   // Ensure that the RHS is a vector of constants.
   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
   if (!BVN)
     return SDValue();
 
   // Check if RHS is a splat of 4-bytes (or smaller).

llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-LINUX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-LINUX-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-LINUX-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-AIX-32
 
 declare hidden i32 @call1()
 define hidden void @function1() {
 ; CHECK-LINUX-LABEL: function1:
 ; CHECK-LINUX:       # %bb.0: # %entry
 ; CHECK-LINUX-NEXT:    mflr r0
 ; CHECK-LINUX-NEXT:    std r0, 16(r1)
 ; CHECK-LINUX-NEXT:    stdu r1, -32(r1)
 ; CHECK-LINUX-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-LINUX-NEXT:    .cfi_offset lr, 16
 ; CHECK-LINUX-NEXT:    bl call1@notoc
 ; CHECK-LINUX-NEXT:    addi r1, r1, 32
 ; CHECK-LINUX-NEXT:    ld r0, 16(r1)
 ; CHECK-LINUX-NEXT:    mtlr r0
 ; CHECK-LINUX-NEXT:    blr
 ;
 ; CHECK-LINUX-BE-LABEL: function1:
 ; CHECK-LINUX-BE:       # %bb.0: # %entry
 ; CHECK-LINUX-BE-NEXT:    mflr r0
 ; CHECK-LINUX-BE-NEXT:    std r0, 16(r1)
 ; CHECK-LINUX-BE-NEXT:    stdu r1, -112(r1)
 ; CHECK-LINUX-BE-NEXT:    .cfi_def_cfa_offset 112
 ; CHECK-LINUX-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-LINUX-BE-NEXT:    bl call1
 ; CHECK-LINUX-BE-NEXT:    nop
 ; CHECK-LINUX-BE-NEXT:    addi r1, r1, 112
 ; CHECK-LINUX-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-LINUX-BE-NEXT:    mtlr r0
 ; CHECK-LINUX-BE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: function1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mflr r0
 ; CHECK-AIX-NEXT:    std r0, 16(r1)
 ; CHECK-AIX-NEXT:    stdu r1, -112(r1)
 ; CHECK-AIX-NEXT:    bl .call1[PR]
 ; CHECK-AIX-NEXT:    nop
 ; CHECK-AIX-NEXT:    addi r1, r1, 112
 ; CHECK-AIX-NEXT:    ld r0, 16(r1)
 ; CHECK-AIX-NEXT:    mtlr r0
 ; CHECK-AIX-NEXT:    blr
+;
+; CHECK-LINUX-32-LABEL: function1:
+; CHECK-LINUX-32:       # %bb.0: # %entry
+; CHECK-LINUX-32-NEXT:    mflr r0
+; CHECK-LINUX-32-NEXT:    stw r0, 4(r1)
+; CHECK-LINUX-32-NEXT:    stwu r1, -48(r1)
+; CHECK-LINUX-32-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-LINUX-32-NEXT:    .cfi_offset lr, 4
+; CHECK-LINUX-32-NEXT:    bl call1
+; CHECK-LINUX-32-NEXT:    li r4, 0
+; CHECK-LINUX-32-NEXT:    stw r3, 16(r1)
+; CHECK-LINUX-32-NEXT:    stw r4, 32(r1)
+; CHECK-LINUX-32-NEXT:    lwz r0, 52(r1)
+; CHECK-LINUX-32-NEXT:    addi r1, r1, 48
+; CHECK-LINUX-32-NEXT:    mtlr r0
+; CHECK-LINUX-32-NEXT:    blr
+;
+; CHECK-AIX-32-LABEL: function1:
+; CHECK-AIX-32:       # %bb.0: # %entry
+; CHECK-AIX-32-NEXT:    mflr r0
+; CHECK-AIX-32-NEXT:    stw r0, 8(r1)
+; CHECK-AIX-32-NEXT:    stwu r1, -96(r1)
+; CHECK-AIX-32-NEXT:    bl .call1[PR]
+; CHECK-AIX-32-NEXT:    nop
+; CHECK-AIX-32-NEXT:    li r4, 0
+; CHECK-AIX-32-NEXT:    stw r3, 64(r1)
+; CHECK-AIX-32-NEXT:    stw r4, 80(r1)
+; CHECK-AIX-32-NEXT:    addi r1, r1, 96
+; CHECK-AIX-32-NEXT:    lwz r0, 8(r1)
+; CHECK-AIX-32-NEXT:    mtlr r0
+; CHECK-AIX-32-NEXT:    blr
 entry:
   %tailcall1 = tail call i32 @call1()
   %0 = insertelement <4 x i32> poison, i32 %tailcall1, i64 1
   %1 = insertelement <4 x i32> %0, i32 0, i64 2
   %2 = insertelement <4 x i32> %1, i32 0, i64 3
   %3 = trunc <4 x i32> %2 to <4 x i8>
   %4 = icmp eq <4 x i8> %3, zeroinitializer
   %5 = shufflevector <4 x i1> %4, <4 x i1> poison, <2 x i32> <i32 3, i32 undef>