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Differential D135010

[GlobalISel] Combine `(x + y) - y -> x` and friends
ClosedPublic

Authored by paquette on Sep 30 2022, 9:55 PM.

Details

Reviewers
aemerson
arsenm
jroelofs
Commits
rG970cb99e0a8c: [GlobalISel] Combine `(x + y) - y -> x` and friends
Summary

This adds a combine that handles

(x + y) - y -> x
(x + y) - x -> y
x - (y + x) -> 0 - y
x - (x + z) -> 0 - z

On AArch64, we get added benefit for 0 - y because it can be selected to a neg instruction.

Diff Detail

Event Timeline

paquette created this revision.Sep 30 2022, 9:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 30 2022, 9:55 PM
Herald added subscribers: hiraditya, kristof.beyls, rovka. · View Herald Transcript
paquette requested review of this revision.Sep 30 2022, 9:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 30 2022, 9:55 PM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B189827: Diff 464469.Sep 30 2022, 9:55 PM
arsenm added inline comments.Oct 1 2022, 12:51 PM
llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
275

Should also add vector cases

paquette updated this revision to Diff 464517.Oct 1 2022, 1:30 PM

add vector stuff

Harbormaster completed remote builds in B189860: Diff 464517.Oct 1 2022, 1:30 PM
arsenm accepted this revision.Oct 1 2022, 1:55 PM
This revision is now accepted and ready to land.Oct 1 2022, 1:55 PM
This revision was landed with ongoing or failed builds.Oct 3 2022, 10:16 AM
Closed by commit rG970cb99e0a8c: [GlobalISel] Combine `(x + y) - y -> x` and friends (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG970cb99e0a8c: [GlobalISel] Combine `(x + y) - y -> x` and friends.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
7 lines
Target/
GlobalISel/
14 lines
lib/
CodeGen/
GlobalISel/
44 lines
test/
CodeGen/
AArch64/
GlobalISel/
364 lines

Diff 464725

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 750 Lines • ▼ Show 20 Linespublic:
/// Transform G_ADD(x, G_SUB(y, x)) to y. /// Transform G_ADD(x, G_SUB(y, x)) to y.
/// Transform G_ADD(G_SUB(y, x), x) to y. /// Transform G_ADD(G_SUB(y, x), x) to y.
bool matchAddSubSameReg(MachineInstr &MI, Register &Src); bool matchAddSubSameReg(MachineInstr &MI, Register &Src);
bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo); bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo);
bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo); bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo);
/// Transform:
/// (x + y) - y -> x
/// (x + y) - x -> y
/// x - (y + x) -> 0 - y
/// x - (x + z) -> 0 - z
bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo);
/// \returns true if it is possible to simplify a select instruction \p MI /// \returns true if it is possible to simplify a select instruction \p MI
/// to a min/max instruction of some sort. /// to a min/max instruction of some sort.
bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo); bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo);
private: private:
/// Given a non-indexed load or store instruction \p MI, find an offset that /// Given a non-indexed load or store instruction \p MI, find an offset that
/// can be usefully and legally folded into it as a post-indexing operation. /// can be usefully and legally folded into it as a post-indexing operation.
/// ///
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 944 Lines • ▼ Show 20 Linesdef buildvector_identity_fold : GICombineRule<
(apply [{ Helper.replaceSingleDefInstWithReg(*${build_vector}, ${matchinfo}); }])>; (apply [{ Helper.replaceSingleDefInstWithReg(*${build_vector}, ${matchinfo}); }])>;
def trunc_buildvector_fold : GICombineRule< def trunc_buildvector_fold : GICombineRule<
(defs root:$op, register_matchinfo:$matchinfo), (defs root:$op, register_matchinfo:$matchinfo),
(match (wip_match_opcode G_TRUNC):$op, (match (wip_match_opcode G_TRUNC):$op,
[{ return Helper.matchTruncBuildVectorFold(*${op}, ${matchinfo}); }]), [{ return Helper.matchTruncBuildVectorFold(*${op}, ${matchinfo}); }]),
(apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${matchinfo}); }])>; (apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${matchinfo}); }])>;
// Transform:
// (x + y) - y -> x
// (x + y) - x -> y
// x - (y + x) -> 0 - y
// x - (x + z) -> 0 - z
def sub_add_reg: GICombineRule <
(defs root:$root, build_fn_matchinfo:$matchinfo),
(match (wip_match_opcode G_SUB):$root,
[{ return Helper.matchSubAddSameReg(*${root}, ${matchinfo}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
def select_to_minmax: GICombineRule< def select_to_minmax: GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_SELECT):$root, (match (wip_match_opcode G_SELECT):$root,
[{ return Helper.matchSimplifySelectToMinMax(*${root}, ${info}); }]), [{ return Helper.matchSimplifySelectToMinMax(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
// FIXME: These should use the custom predicate feature once it lands. // FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero, def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesdef all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
not_cmp_fold, opt_brcond_by_inverting_cond, not_cmp_fold, opt_brcond_by_inverting_cond,
unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl, unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero, const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine, shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
truncstore_merge, div_rem_to_divrem, funnel_shift_combines, truncstore_merge, div_rem_to_divrem, funnel_shift_combines,
form_bitfield_extract, constant_fold, fabs_fneg_fold, form_bitfield_extract, constant_fold, fabs_fneg_fold,
intdiv_combines, mulh_combines, redundant_neg_operands, intdiv_combines, mulh_combines, redundant_neg_operands,
and_or_disjoint_mask, fma_combines, fold_binop_into_select]>; and_or_disjoint_mask, fma_combines, fold_binop_into_select,
sub_add_reg]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in // A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and // this group have been selected based on experiments to balance code size and
// compile time performance. // compile time performance.
def optnone_combines : GICombineGroup<[trivial_combines, def optnone_combines : GICombineGroup<[trivial_combines,
ptr_add_immed_chain, combines_for_extload, ptr_add_immed_chain, combines_for_extload,
not_cmp_fold, opt_brcond_by_inverting_cond]>; not_cmp_fold, opt_brcond_by_inverting_cond]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 4,819 Lines • ▼ Show 20 Lines MatchInfo = [&](MachineIRBuilder &B) {
Observer.changingInstr(MI); Observer.changingInstr(MI);
MI.setDesc(B.getTII().get(NewOpcode)); MI.setDesc(B.getTII().get(NewOpcode));
MI.removeOperand(4); MI.removeOperand(4);
Observer.changedInstr(MI); Observer.changedInstr(MI);
}; };
return true; return true;
} }
bool CombinerHelper::matchSubAddSameReg(MachineInstr &MI,
BuildFnTy &MatchInfo) {
assert(MI.getOpcode() == TargetOpcode::G_SUB);
Register Dst = MI.getOperand(0).getReg();
// (x + y) - z -> x (if y == z)
// (x + y) - z -> y (if x == z)
Register X, Y, Z;
if (mi_match(Dst, MRI, m_GSub(m_GAdd(m_Reg(X), m_Reg(Y)), m_Reg(Z)))) {
Register ReplaceReg;
int64_t CstX, CstY;
if (Y == Z || (mi_match(Y, MRI, m_ICstOrSplat(CstY)) &&
mi_match(Z, MRI, m_SpecificICstOrSplat(CstY))))
ReplaceReg = X;
else if (X == Z || (mi_match(X, MRI, m_ICstOrSplat(CstX)) &&
mi_match(Z, MRI, m_SpecificICstOrSplat(CstX))))
ReplaceReg = Y;
if (ReplaceReg) {
MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, ReplaceReg); };
return true;
}
}
// x - (y + z) -> 0 - y (if x == z)
// x - (y + z) -> 0 - z (if x == y)
if (mi_match(Dst, MRI, m_GSub(m_Reg(X), m_GAdd(m_Reg(Y), m_Reg(Z))))) {
Register ReplaceReg;
int64_t CstX;
if (X == Z || (mi_match(X, MRI, m_ICstOrSplat(CstX)) &&
mi_match(Z, MRI, m_SpecificICstOrSplat(CstX))))
ReplaceReg = Y;
else if (X == Y || (mi_match(X, MRI, m_ICstOrSplat(CstX)) &&
mi_match(Y, MRI, m_SpecificICstOrSplat(CstX))))
ReplaceReg = Z;
if (ReplaceReg) {
MatchInfo = [=](MachineIRBuilder &B) {
auto Zero = B.buildConstant(MRI.getType(Dst), 0);
B.buildSub(Dst, Zero, ReplaceReg);
};
return true;
}
}
return false;
}
MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) { MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_UDIV); assert(MI.getOpcode() == TargetOpcode::G_UDIV);
auto &UDiv = cast<GenericMachineInstr>(MI); auto &UDiv = cast<GenericMachineInstr>(MI);
Register Dst = UDiv.getReg(0); Register Dst = UDiv.getReg(0);
Register LHS = UDiv.getReg(1); Register LHS = UDiv.getReg(1);
Register RHS = UDiv.getReg(2); Register RHS = UDiv.getReg(2);
LLT Ty = MRI.getType(Dst); LLT Ty = MRI.getType(Dst);
LLT ScalarTy = Ty.getScalarType(); LLT ScalarTy = Ty.getScalarType();
▲ Show 20 Lines • Show All 1,181 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: simplify_to_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; (x + y) - y -> x
; CHECK-LABEL: name: simplify_to_x
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY %x(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x, %y
%sub:_(s32) = G_SUB %add, %y
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_y
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; (x + y) - x -> y
; CHECK-LABEL: name: simplify_to_y
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY %y(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x, %y
%sub:_(s32) = G_SUB %add, %x
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_constant_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; (x + 1) - 1 -> x
; CHECK-LABEL: name: simplify_to_constant_x
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY %x(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y1:_(s32) = G_CONSTANT i32 1
%y2:_(s32) = G_CONSTANT i32 1
%add:_(s32) = G_ADD %x, %y1
%sub:_(s32) = G_SUB %add, %y2
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_constant_y
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; (x + y) - x -> y
; CHECK-LABEL: name: simplify_to_constant_y
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY %y(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x1:_(s32) = G_CONSTANT i32 1
%x2:_(s32) = G_CONSTANT i32 1
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x1, %y
%sub:_(s32) = G_SUB %add, %x2
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: vector_simplify_to_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; (x + y) - y -> x
; CHECK-LABEL: name: vector_simplify_to_x
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: $d0 = COPY %x(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<2 x s32>) = COPY $d0
%y:_(<2 x s32>) = COPY $d1
%add:_(<2 x s32>) = G_ADD %x, %y
%sub:_(<2 x s32>) = G_SUB %add, %y
$d0 = COPY %sub(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: splat_simplify_to_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; (x + 1) - 1 -> x
; CHECK-LABEL: name: splat_simplify_to_x
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: $d0 = COPY %x(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<2 x s32>) = COPY $d0
%cst:_(s32) = G_CONSTANT i32 1
%y1:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%y2:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%add:_(<2 x s32>) = G_ADD %x, %y1
%sub:_(<2 x s32>) = G_SUB %add, %y2
$d0 = COPY %sub(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: unique_registers_no_fold
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: unique_registers_no_fold
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %z:_(s32) = COPY $w2
; CHECK-NEXT: %add:_(s32) = G_ADD %y, %x
; CHECK-NEXT: %sub:_(s32) = G_SUB %add, %z
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%z:_(s32) = COPY $w2
%add:_(s32) = G_ADD %y, %x
%sub:_(s32) = G_SUB %add, %z
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: unique_constants_no_fold
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; (x + y) - x -> y
; CHECK-LABEL: name: unique_constants_no_fold
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x1:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %x2:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %add:_(s32) = G_ADD %x1, %y
; CHECK-NEXT: %sub:_(s32) = G_SUB %add, %x2
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x1:_(s32) = G_CONSTANT i32 1
%x2:_(s32) = G_CONSTANT i32 2
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x1, %y
%sub:_(s32) = G_SUB %add, %x2
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_neg_y
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; x - (y + x) -> 0 - y
; CHECK-LABEL: name: simplify_to_neg_y
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %sub:_(s32) = G_SUB [[C]], %y
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x, %y
%sub:_(s32) = G_SUB %x, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_neg_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; y - (y + x) -> 0 - x
; CHECK-LABEL: name: simplify_to_neg_x
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %sub:_(s32) = G_SUB [[C]], %x
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x, %y
%sub:_(s32) = G_SUB %y, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_neg_y_constant
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; x - (y + x) -> 0 - y
; CHECK-LABEL: name: simplify_to_neg_y_constant
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %sub:_(s32) = G_SUB [[C]], %y
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x1:_(s32) = G_CONSTANT i32 1
%x2:_(s32) = G_CONSTANT i32 1
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x1, %y
%sub:_(s32) = G_SUB %x2, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: simplify_to_neg_x_constant
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; y - (y + x) -> 0 - x
; CHECK-LABEL: name: simplify_to_neg_x_constant
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %sub:_(s32) = G_SUB [[C]], %x
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y1:_(s32) = G_CONSTANT i32 1
%y2:_(s32) = G_CONSTANT i32 1
%add:_(s32) = G_ADD %x, %y1
%sub:_(s32) = G_SUB %y2, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: vector_simplify_to_neg_x
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; y - (y + x) -> 0 - x
; CHECK-LABEL: name: vector_simplify_to_neg_x
arsenmUnsubmitted
Not Done
ReplyInline Actions

Should also add vector cases

arsenm: Should also add vector cases
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK-NEXT: %sub:_(<2 x s32>) = G_SUB [[BUILD_VECTOR]], %x
; CHECK-NEXT: $d0 = COPY %sub(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<2 x s32>) = COPY $d0
%y:_(<2 x s32>) = COPY $d1
%add:_(<2 x s32>) = G_ADD %x, %y
%sub:_(<2 x s32>) = G_SUB %y, %add
$d0 = COPY %sub(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: vector_simplify_to_neg_y_constant
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; x - (y + x) -> 0 - y
; CHECK-LABEL: name: vector_simplify_to_neg_y_constant
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<2 x s32>) = COPY $d1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK-NEXT: %sub:_(<2 x s32>) = G_SUB [[BUILD_VECTOR]], %y
; CHECK-NEXT: $d0 = COPY %sub(<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%cst:_(s32) = G_CONSTANT i32 1
%x1:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%x2:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst
%y:_(<2 x s32>) = COPY $d1
%add:_(<2 x s32>) = G_ADD %x1, %y
%sub:_(<2 x s32>) = G_SUB %x2, %add
$d0 = COPY %sub(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: unique_registers_neg_no_fold
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; y - (y + x) -> 0 - x
; CHECK-LABEL: name: unique_registers_neg_no_fold
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %z:_(s32) = COPY $w2
; CHECK-NEXT: %add:_(s32) = G_ADD %x, %y
; CHECK-NEXT: %sub:_(s32) = G_SUB %z, %add
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%z:_(s32) = COPY $w2
%add:_(s32) = G_ADD %x, %y
%sub:_(s32) = G_SUB %z, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0
...
---
name: wrong_constant_neg_no_fold
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; x - (y + x) -> 0 - y
; CHECK-LABEL: name: wrong_constant_neg_no_fold
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x1:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %x2:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %add:_(s32) = G_ADD %x1, %y
; CHECK-NEXT: %sub:_(s32) = G_SUB %x2, %add
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x1:_(s32) = G_CONSTANT i32 1
%x2:_(s32) = G_CONSTANT i32 2
%y:_(s32) = COPY $w1
%add:_(s32) = G_ADD %x1, %y
%sub:_(s32) = G_SUB %x2, %add
$w0 = COPY %sub(s32)
RET_ReallyLR implicit $w0