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Start replacing vector_extract/vector_insert with extractelt/insertelt
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Authored by arsenm on Oct 5 2015, 9:03 AM.

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Reviewers

jmolloy
resistor
hfinkel

Summary

These are redundant pairs of nodes defined for
INSERT_VECTOR_ELEMENT/EXTRACT_VECTOR_ELEMENT.
insertelement/extractelement are slightly closer to the corresponding
C++ node name, and has stricter type checking so prefer it.

Update targets to only use these nodes where it is trivial to do so.
AArch64, ARM, and Mips all have various type errors on simple replacement,
so they will need work to fix.

Example from AArch64:

def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),

(i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;

Which is trying to do sext_inreg i8, i8.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 36522.Oct 5 2015, 9:03 AM

arsenm retitled this revision from to Start replacing vector_extract/vector_insert with extractelt/insertelt.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

Herald added subscribers: jyknight, arsenm, aemerson, jholewinski. · View Herald TranscriptOct 5 2015, 9:03 AM

ping

jmolloy added a reviewer: jmolloy.Nov 4 2015, 12:57 PM

arsenm added a reviewer: resistor.Nov 10 2015, 11:45 AM

ping

Please add a comment to include/llvm/Target/TargetSelectionDAG.td above the definitions of vector_extract and vector_insert stating that the use of extractelt and insertelt is preferred when applicable.

Otherwise, LGTM.

This revision is now accepted and ready to land.Dec 9 2015, 8:50 PM

r255359

Revision Contents

Path

Size

lib/

Target/

AArch64/

AArch64InstrInfo.td

10 lines

AMDGPU/

AMDGPUInstructions.td

4 lines

SIInstructions.td

8 lines

NVPTX/

NVPTXVector.td

58 lines

PowerPC/

PPCInstrQPX.td

20 lines

PPCInstrVSX.td

8 lines

Sparc/

SparcInstrInfo.td

4 lines

X86/

X86InstrAVX512.td

8 lines

X86InstrFragmentsSIMD.td

8 lines

X86InstrMMX.td

2 lines

X86InstrSSE.td

70 lines

Diff 36522

lib/Target/AArch64/AArch64InstrInfo.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 3,427 Lines • ▼ Show 20 Lines	defm : Neon_mulacc_widen_patterns<
SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;		SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
defm : Neon_mulacc_widen_patterns<		defm : Neon_mulacc_widen_patterns<
TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,		TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;		UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;

// Patterns for 64-bit pmull		// Patterns for 64-bit pmull
def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),		def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
(PMULLv1i64 V64:$Rn, V64:$Rm)>;		(PMULLv1i64 V64:$Rn, V64:$Rm)>;
def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),		def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)),
(vector_extract (v2i64 V128:$Rm), (i64 1))),		(extractelt (v2i64 V128:$Rm), (i64 1))),
(PMULLv2i64 V128:$Rn, V128:$Rm)>;		(PMULLv2i64 V128:$Rn, V128:$Rm)>;

// CodeGen patterns for addhn and subhn instructions, which can actually be		// CodeGen patterns for addhn and subhn instructions, which can actually be
// written in LLVM IR without too much difficulty.		// written in LLVM IR without too much difficulty.

// ADDHN		// ADDHN
def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),		def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
(ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;		(ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines
defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;		defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;

defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;		defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;		defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;		defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;

multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,		multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
SDNodeXForm IdxXFORM> {		SDNodeXForm IdxXFORM> {
def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),		def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
imm:$idx))))),		imm:$idx))))),
(DUP V128:$Rn, (IdxXFORM imm:$idx))>;		(DUP V128:$Rn, (IdxXFORM imm:$idx))>;

def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),		def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
imm:$idx))))),		imm:$idx))))),
(DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;		(DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
}		}

defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;		defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;		defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;		defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;

defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;		defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
▲ Show 20 Lines • Show All 2,181 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUInstructions.td

	Show First 20 Lines • Show All 508 Lines • ▼ Show 20 Lines

	/* Other helper patterns */			/* Other helper patterns */
	/* --------------------- */			/* --------------------- */

	/* Extract element pattern */			/* Extract element pattern */
	class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,			class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
	SubRegIndex sub_reg>			SubRegIndex sub_reg>
	: Pat<			: Pat<
	(sub_type (vector_extract vec_type:$src, sub_idx)),			(sub_type (extractelt vec_type:$src, sub_idx)),
	(EXTRACT_SUBREG $src, sub_reg)			(EXTRACT_SUBREG $src, sub_reg)
	>;			>;

	/* Insert element pattern */			/* Insert element pattern */
	class Insert_Element <ValueType elem_type, ValueType vec_type,			class Insert_Element <ValueType elem_type, ValueType vec_type,
	int sub_idx, SubRegIndex sub_reg>			int sub_idx, SubRegIndex sub_reg>
	: Pat <			: Pat <
	(vector_insert vec_type:$vec, elem_type:$elem, sub_idx),			(insertelt vec_type:$vec, elem_type:$elem, sub_idx),
	(INSERT_SUBREG $vec, $elem, sub_reg)			(INSERT_SUBREG $vec, $elem, sub_reg)
	>;			>;

	// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer			// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
	// can handle COPY instructions.			// can handle COPY instructions.
	// bitconvert pattern			// bitconvert pattern
	class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <			class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
	(dt (bitconvert (st rc:$src0))),			(dt (bitconvert (st rc:$src0))),
	▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIInstructions.td

	Show First 20 Lines • Show All 3,021 Lines • ▼ Show 20 Lines
	/******** ====================== ********/			/******** ====================== ********/
	/******** Indirect adressing ********/			/******** Indirect adressing ********/
	/******** ====================== ********/			/******** ====================== ********/

	multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {			multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {

	// 1. Extract with offset			// 1. Extract with offset
	def : Pat<			def : Pat<
	(eltvt (vector_extract vt:$vec, (add i32:$idx, imm:$off))),			(eltvt (extractelt vt:$vec, (add i32:$idx, imm:$off))),
	(SI_INDIRECT_SRC $vec, $idx, imm:$off)			(SI_INDIRECT_SRC $vec, $idx, imm:$off)
	>;			>;

	// 2. Extract without offset			// 2. Extract without offset
	def : Pat<			def : Pat<
	(eltvt (vector_extract vt:$vec, i32:$idx)),			(eltvt (extractelt vt:$vec, i32:$idx)),
	(SI_INDIRECT_SRC $vec, $idx, 0)			(SI_INDIRECT_SRC $vec, $idx, 0)
	>;			>;

	// 3. Insert with offset			// 3. Insert with offset
	def : Pat<			def : Pat<
	(vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),			(insertelt vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
	(IndDst $vec, $idx, imm:$off, $val)			(IndDst $vec, $idx, imm:$off, $val)
	>;			>;

	// 4. Insert without offset			// 4. Insert without offset
	def : Pat<			def : Pat<
	(vector_insert vt:$vec, eltvt:$val, i32:$idx),			(insertelt vt:$vec, eltvt:$val, i32:$idx),
	(IndDst $vec, $idx, 0, $val)			(IndDst $vec, $idx, 0, $val)
	>;			>;
	}			}

	defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;			defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
	defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;			defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
	defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;			defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
	defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;			defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
	▲ Show 20 Lines • Show All 218 Lines • Show Last 20 Lines

lib/Target/NVPTX/NVPTXVector.td

Show All 20 Lines	class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
NVPTXInst scalarInst=sInst;		NVPTXInst scalarInst=sInst;
}		}

let isAsCheapAsAMove=1, VecInstType=isVecExtract.Value in {		let isAsCheapAsAMove=1, VecInstType=isVecExtract.Value in {
// Extract v2i16		// Extract v2i16
def V2i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),		def V2i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),
(ins V2I16Regs:$src, i8imm:$c),		(ins V2I16Regs:$src, i8imm:$c),
"mov.u16 \t$dst, $src${c:vecelem};",		"mov.u16 \t$dst, $src${c:vecelem};",
[(set Int16Regs:$dst, (vector_extract		[(set Int16Regs:$dst, (extractelt
(v2i16 V2I16Regs:$src), imm:$c))],		(v2i16 V2I16Regs:$src), imm:$c))],
IMOV16rr>;		IMOV16rr>;

// Extract v4i16		// Extract v4i16
def V4i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),		def V4i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),
(ins V4I16Regs:$src, i8imm:$c),		(ins V4I16Regs:$src, i8imm:$c),
"mov.u16 \t$dst, $src${c:vecelem};",		"mov.u16 \t$dst, $src${c:vecelem};",
[(set Int16Regs:$dst, (vector_extract		[(set Int16Regs:$dst, (extractelt
(v4i16 V4I16Regs:$src), imm:$c))],		(v4i16 V4I16Regs:$src), imm:$c))],
IMOV16rr>;		IMOV16rr>;

// Extract v2i8		// Extract v2i8
def V2i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),		def V2i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),
(ins V2I8Regs:$src, i8imm:$c),		(ins V2I8Regs:$src, i8imm:$c),
"mov.u16 \t$dst, $src${c:vecelem};",		"mov.u16 \t$dst, $src${c:vecelem};",
[(set Int8Regs:$dst, (vector_extract		[(set Int8Regs:$dst, (extractelt
(v2i8 V2I8Regs:$src), imm:$c))],		(v2i8 V2I8Regs:$src), imm:$c))],
IMOV8rr>;		IMOV8rr>;

// Extract v4i8		// Extract v4i8
def V4i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),		def V4i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),
(ins V4I8Regs:$src, i8imm:$c),		(ins V4I8Regs:$src, i8imm:$c),
"mov.u16 \t$dst, $src${c:vecelem};",		"mov.u16 \t$dst, $src${c:vecelem};",
[(set Int8Regs:$dst, (vector_extract		[(set Int8Regs:$dst, (extractelt
(v4i8 V4I8Regs:$src), imm:$c))],		(v4i8 V4I8Regs:$src), imm:$c))],
IMOV8rr>;		IMOV8rr>;

// Extract v2i32		// Extract v2i32
def V2i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),		def V2i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),
(ins V2I32Regs:$src, i8imm:$c),		(ins V2I32Regs:$src, i8imm:$c),
"mov.u32 \t$dst, $src${c:vecelem};",		"mov.u32 \t$dst, $src${c:vecelem};",
[(set Int32Regs:$dst, (vector_extract		[(set Int32Regs:$dst, (extractelt
(v2i32 V2I32Regs:$src), imm:$c))],		(v2i32 V2I32Regs:$src), imm:$c))],
IMOV32rr>;		IMOV32rr>;

// Extract v2f32		// Extract v2f32
def V2f32Extract : NVPTXVecInst<(outs Float32Regs:$dst),		def V2f32Extract : NVPTXVecInst<(outs Float32Regs:$dst),
(ins V2F32Regs:$src, i8imm:$c),		(ins V2F32Regs:$src, i8imm:$c),
"mov.f32 \t$dst, $src${c:vecelem};",		"mov.f32 \t$dst, $src${c:vecelem};",
[(set Float32Regs:$dst, (vector_extract		[(set Float32Regs:$dst, (extractelt
(v2f32 V2F32Regs:$src), imm:$c))],		(v2f32 V2F32Regs:$src), imm:$c))],
FMOV32rr>;		FMOV32rr>;

// Extract v2i64		// Extract v2i64
def V2i64Extract : NVPTXVecInst<(outs Int64Regs:$dst),		def V2i64Extract : NVPTXVecInst<(outs Int64Regs:$dst),
(ins V2I64Regs:$src, i8imm:$c),		(ins V2I64Regs:$src, i8imm:$c),
"mov.u64 \t$dst, $src${c:vecelem};",		"mov.u64 \t$dst, $src${c:vecelem};",
[(set Int64Regs:$dst, (vector_extract		[(set Int64Regs:$dst, (extractelt
(v2i64 V2I64Regs:$src), imm:$c))],		(v2i64 V2I64Regs:$src), imm:$c))],
IMOV64rr>;		IMOV64rr>;

// Extract v2f64		// Extract v2f64
def V2f64Extract : NVPTXVecInst<(outs Float64Regs:$dst),		def V2f64Extract : NVPTXVecInst<(outs Float64Regs:$dst),
(ins V2F64Regs:$src, i8imm:$c),		(ins V2F64Regs:$src, i8imm:$c),
"mov.f64 \t$dst, $src${c:vecelem};",		"mov.f64 \t$dst, $src${c:vecelem};",
[(set Float64Regs:$dst, (vector_extract		[(set Float64Regs:$dst, (extractelt
(v2f64 V2F64Regs:$src), imm:$c))],		(v2f64 V2F64Regs:$src), imm:$c))],
FMOV64rr>;		FMOV64rr>;

// Extract v4i32		// Extract v4i32
def V4i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),		def V4i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),
(ins V4I32Regs:$src, i8imm:$c),		(ins V4I32Regs:$src, i8imm:$c),
"mov.u32 \t$dst, $src${c:vecelem};",		"mov.u32 \t$dst, $src${c:vecelem};",
[(set Int32Regs:$dst, (vector_extract		[(set Int32Regs:$dst, (extractelt
(v4i32 V4I32Regs:$src), imm:$c))],		(v4i32 V4I32Regs:$src), imm:$c))],
IMOV32rr>;		IMOV32rr>;

// Extract v4f32		// Extract v4f32
def V4f32Extract : NVPTXVecInst<(outs Float32Regs:$dst),		def V4f32Extract : NVPTXVecInst<(outs Float32Regs:$dst),
(ins V4F32Regs:$src, i8imm:$c),		(ins V4F32Regs:$src, i8imm:$c),
"mov.f32 \t$dst, $src${c:vecelem};",		"mov.f32 \t$dst, $src${c:vecelem};",
[(set Float32Regs:$dst, (vector_extract		[(set Float32Regs:$dst, (extractelt
(v4f32 V4F32Regs:$src), imm:$c))],		(v4f32 V4F32Regs:$src), imm:$c))],
FMOV32rr>;		FMOV32rr>;
}		}

let isAsCheapAsAMove=1, VecInstType=isVecInsert.Value in {		let isAsCheapAsAMove=1, VecInstType=isVecInsert.Value in {
// Insert v2i8		// Insert v2i8
def V2i8Insert : NVPTXVecInst<(outs V2I8Regs:$dst),		def V2i8Insert : NVPTXVecInst<(outs V2I8Regs:$dst),
(ins V2I8Regs:$src, Int8Regs:$val, i8imm:$c),		(ins V2I8Regs:$src, Int8Regs:$val, i8imm:$c),
"mov.v2.u16 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.u16 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u16 \t$dst${c:vecelem}, $val;",		"\n\tmov.u16 \t$dst${c:vecelem}, $val;",
[(set V2I8Regs:$dst,		[(set V2I8Regs:$dst,
(vector_insert V2I8Regs:$src, Int8Regs:$val, imm:$c))],		(insertelt V2I8Regs:$src, Int8Regs:$val, imm:$c))], IMOV8rr>;
IMOV8rr>;

// Insert v4i8		// Insert v4i8
def V4i8Insert : NVPTXVecInst<(outs V4I8Regs:$dst),		def V4i8Insert : NVPTXVecInst<(outs V4I8Regs:$dst),
(ins V4I8Regs:$src, Int8Regs:$val, i8imm:$c),		(ins V4I8Regs:$src, Int8Regs:$val, i8imm:$c),
"mov.v4.u16 \t${dst:vecfull}, ${src:vecfull};"		"mov.v4.u16 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u16 \t$dst${c:vecelem}, $val;",		"\n\tmov.u16 \t$dst${c:vecelem}, $val;",
[(set V4I8Regs:$dst,		[(set V4I8Regs:$dst,
(vector_insert V4I8Regs:$src, Int8Regs:$val, imm:$c))],		(insertelt V4I8Regs:$src, Int8Regs:$val, imm:$c))], IMOV8rr>;
IMOV8rr>;

// Insert v2i16		// Insert v2i16
def V2i16Insert : NVPTXVecInst<(outs V2I16Regs:$dst),		def V2i16Insert : NVPTXVecInst<(outs V2I16Regs:$dst),
(ins V2I16Regs:$src, Int16Regs:$val, i8imm:$c),		(ins V2I16Regs:$src, Int16Regs:$val, i8imm:$c),
"mov.v2.u16 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.u16 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u16 \t$dst${c:vecelem}, $val;",		"\n\tmov.u16 \t$dst${c:vecelem}, $val;",
[(set V2I16Regs:$dst,		[(set V2I16Regs:$dst,
(vector_insert V2I16Regs:$src, Int16Regs:$val, imm:$c))],		(insertelt V2I16Regs:$src, Int16Regs:$val, imm:$c))],
IMOV16rr>;		IMOV16rr>;

// Insert v4i16		// Insert v4i16
def V4i16Insert : NVPTXVecInst<(outs V4I16Regs:$dst),		def V4i16Insert : NVPTXVecInst<(outs V4I16Regs:$dst),
(ins V4I16Regs:$src, Int16Regs:$val, i8imm:$c),		(ins V4I16Regs:$src, Int16Regs:$val, i8imm:$c),
"mov.v4.u16 \t${dst:vecfull}, ${src:vecfull};"		"mov.v4.u16 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u16 \t$dst${c:vecelem}, $val;",		"\n\tmov.u16 \t$dst${c:vecelem}, $val;",
[(set V4I16Regs:$dst,		[(set V4I16Regs:$dst,
(vector_insert V4I16Regs:$src, Int16Regs:$val, imm:$c))],		(insertelt V4I16Regs:$src, Int16Regs:$val, imm:$c))],
IMOV16rr>;		IMOV16rr>;

// Insert v2i32		// Insert v2i32
def V2i32Insert : NVPTXVecInst<(outs V2I32Regs:$dst),		def V2i32Insert : NVPTXVecInst<(outs V2I32Regs:$dst),
(ins V2I32Regs:$src, Int32Regs:$val, i8imm:$c),		(ins V2I32Regs:$src, Int32Regs:$val, i8imm:$c),
"mov.v2.u32 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.u32 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u32 \t$dst${c:vecelem}, $val;",		"\n\tmov.u32 \t$dst${c:vecelem}, $val;",
[(set V2I32Regs:$dst,		[(set V2I32Regs:$dst,
(vector_insert V2I32Regs:$src, Int32Regs:$val, imm:$c))],		(insertelt V2I32Regs:$src, Int32Regs:$val, imm:$c))],
IMOV32rr>;		IMOV32rr>;

// Insert v2f32		// Insert v2f32
def V2f32Insert : NVPTXVecInst<(outs V2F32Regs:$dst),		def V2f32Insert : NVPTXVecInst<(outs V2F32Regs:$dst),
(ins V2F32Regs:$src, Float32Regs:$val, i8imm:$c),		(ins V2F32Regs:$src, Float32Regs:$val, i8imm:$c),
"mov.v2.f32 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.f32 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.f32 \t$dst${c:vecelem}, $val;",		"\n\tmov.f32 \t$dst${c:vecelem}, $val;",
[(set V2F32Regs:$dst,		[(set V2F32Regs:$dst,
(vector_insert V2F32Regs:$src, Float32Regs:$val, imm:$c))],		(insertelt V2F32Regs:$src, Float32Regs:$val, imm:$c))],
FMOV32rr>;		FMOV32rr>;

// Insert v2i64		// Insert v2i64
def V2i64Insert : NVPTXVecInst<(outs V2I64Regs:$dst),		def V2i64Insert : NVPTXVecInst<(outs V2I64Regs:$dst),
(ins V2I64Regs:$src, Int64Regs:$val, i8imm:$c),		(ins V2I64Regs:$src, Int64Regs:$val, i8imm:$c),
"mov.v2.u64 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.u64 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u64 \t$dst${c:vecelem}, $val;",		"\n\tmov.u64 \t$dst${c:vecelem}, $val;",
[(set V2I64Regs:$dst,		[(set V2I64Regs:$dst,
(vector_insert V2I64Regs:$src, Int64Regs:$val, imm:$c))],		(insertelt V2I64Regs:$src, Int64Regs:$val, imm:$c))],
IMOV64rr>;		IMOV64rr>;

// Insert v2f64		// Insert v2f64
def V2f64Insert : NVPTXVecInst<(outs V2F64Regs:$dst),		def V2f64Insert : NVPTXVecInst<(outs V2F64Regs:$dst),
(ins V2F64Regs:$src, Float64Regs:$val, i8imm:$c),		(ins V2F64Regs:$src, Float64Regs:$val, i8imm:$c),
"mov.v2.f64 \t${dst:vecfull}, ${src:vecfull};"		"mov.v2.f64 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.f64 \t$dst${c:vecelem}, $val;",		"\n\tmov.f64 \t$dst${c:vecelem}, $val;",
[(set V2F64Regs:$dst,		[(set V2F64Regs:$dst,
(vector_insert V2F64Regs:$src, Float64Regs:$val, imm:$c))],		(insertelt V2F64Regs:$src, Float64Regs:$val, imm:$c))],
FMOV64rr>;		FMOV64rr>;

// Insert v4i32		// Insert v4i32
def V4i32Insert : NVPTXVecInst<(outs V4I32Regs:$dst),		def V4i32Insert : NVPTXVecInst<(outs V4I32Regs:$dst),
(ins V4I32Regs:$src, Int32Regs:$val, i8imm:$c),		(ins V4I32Regs:$src, Int32Regs:$val, i8imm:$c),
"mov.v4.u32 \t${dst:vecfull}, ${src:vecfull};"		"mov.v4.u32 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.u32 \t$dst${c:vecelem}, $val;",		"\n\tmov.u32 \t$dst${c:vecelem}, $val;",
[(set V4I32Regs:$dst,		[(set V4I32Regs:$dst,
(vector_insert V4I32Regs:$src, Int32Regs:$val, imm:$c))],		(insertelt V4I32Regs:$src, Int32Regs:$val, imm:$c))],
IMOV32rr>;		IMOV32rr>;

// Insert v4f32		// Insert v4f32
def V4f32Insert : NVPTXVecInst<(outs V4F32Regs:$dst),		def V4f32Insert : NVPTXVecInst<(outs V4F32Regs:$dst),
(ins V4F32Regs:$src, Float32Regs:$val, i8imm:$c),		(ins V4F32Regs:$src, Float32Regs:$val, i8imm:$c),
"mov.v4.f32 \t${dst:vecfull}, ${src:vecfull};"		"mov.v4.f32 \t${dst:vecfull}, ${src:vecfull};"
"\n\tmov.f32 \t$dst${c:vecelem}, $val;",		"\n\tmov.f32 \t$dst${c:vecelem}, $val;",
[(set V4F32Regs:$dst,		[(set V4F32Regs:$dst,
(vector_insert V4F32Regs:$src, Float32Regs:$val, imm:$c))],		(insertelt V4F32Regs:$src, Float32Regs:$val, imm:$c))],
FMOV32rr>;		FMOV32rr>;
}		}

class BinOpAsmString<string c> {		class BinOpAsmString<string c> {
string s = c;		string s = c;
}		}

class V4AsmStr<string opcode> : BinOpAsmString<		class V4AsmStr<string opcode> : BinOpAsmString<
!strconcat(!strconcat(!strconcat(!strconcat(		!strconcat(!strconcat(!strconcat(!strconcat(
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lib/Target/PowerPC/PPCInstrQPX.td

	Show First 20 Lines • Show All 833 Lines • ▼ Show 20 Lines
	// Additional QPX Patterns			// Additional QPX Patterns
	//			//

	def : Pat<(v4f64 (scalar_to_vector f64:$A)),			def : Pat<(v4f64 (scalar_to_vector f64:$A)),
	(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), $A, sub_64)>;			(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), $A, sub_64)>;
	def : Pat<(v4f32 (scalar_to_vector f32:$A)),			def : Pat<(v4f32 (scalar_to_vector f32:$A)),
	(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $A, sub_64)>;			(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $A, sub_64)>;

	def : Pat<(f64 (vector_extract v4f64:$S, 0)),			def : Pat<(f64 (extractelt v4f64:$S, 0)),
	(EXTRACT_SUBREG $S, sub_64)>;			(EXTRACT_SUBREG $S, sub_64)>;
	def : Pat<(f32 (vector_extract v4f32:$S, 0)),			def : Pat<(f32 (extractelt v4f32:$S, 0)),
	(EXTRACT_SUBREG $S, sub_64)>;			(EXTRACT_SUBREG $S, sub_64)>;

	def : Pat<(f64 (vector_extract v4f64:$S, 1)),			def : Pat<(f64 (extractelt v4f64:$S, 1)),
	(EXTRACT_SUBREG (QVESPLATI $S, 1), sub_64)>;			(EXTRACT_SUBREG (QVESPLATI $S, 1), sub_64)>;
	def : Pat<(f64 (vector_extract v4f64:$S, 2)),			def : Pat<(f64 (extractelt v4f64:$S, 2)),
	(EXTRACT_SUBREG (QVESPLATI $S, 2), sub_64)>;			(EXTRACT_SUBREG (QVESPLATI $S, 2), sub_64)>;
	def : Pat<(f64 (vector_extract v4f64:$S, 3)),			def : Pat<(f64 (extractelt v4f64:$S, 3)),
	(EXTRACT_SUBREG (QVESPLATI $S, 3), sub_64)>;			(EXTRACT_SUBREG (QVESPLATI $S, 3), sub_64)>;

	def : Pat<(f32 (vector_extract v4f32:$S, 1)),			def : Pat<(f32 (extractelt v4f32:$S, 1)),
	(EXTRACT_SUBREG (QVESPLATIs $S, 1), sub_64)>;			(EXTRACT_SUBREG (QVESPLATIs $S, 1), sub_64)>;
	def : Pat<(f32 (vector_extract v4f32:$S, 2)),			def : Pat<(f32 (extractelt v4f32:$S, 2)),
	(EXTRACT_SUBREG (QVESPLATIs $S, 2), sub_64)>;			(EXTRACT_SUBREG (QVESPLATIs $S, 2), sub_64)>;
	def : Pat<(f32 (vector_extract v4f32:$S, 3)),			def : Pat<(f32 (extractelt v4f32:$S, 3)),
	(EXTRACT_SUBREG (QVESPLATIs $S, 3), sub_64)>;			(EXTRACT_SUBREG (QVESPLATIs $S, 3), sub_64)>;

	def : Pat<(f64 (vector_extract v4f64:$S, i64:$F)),			def : Pat<(f64 (extractelt v4f64:$S, i64:$F)),
	(EXTRACT_SUBREG (QVFPERM $S, $S,			(EXTRACT_SUBREG (QVFPERM $S, $S,
	(QVLPCLSXint (RLDICR $F, 2,			(QVLPCLSXint (RLDICR $F, 2,
	/* 63-2 = */ 61))),			/* 63-2 = */ 61))),
	sub_64)>;			sub_64)>;
	def : Pat<(f32 (vector_extract v4f32:$S, i64:$F)),			def : Pat<(f32 (extractelt v4f32:$S, i64:$F)),
	(EXTRACT_SUBREG (QVFPERMs $S, $S,			(EXTRACT_SUBREG (QVFPERMs $S, $S,
	(QVLPCLSXint (RLDICR $F, 2,			(QVLPCLSXint (RLDICR $F, 2,
	/* 63-2 = */ 61))),			/* 63-2 = */ 61))),
	sub_64)>;			sub_64)>;

	def : Pat<(int_ppc_qpx_qvfperm v4f64:$A, v4f64:$B, v4f64:$C),			def : Pat<(int_ppc_qpx_qvfperm v4f64:$A, v4f64:$B, v4f64:$C),
	(QVFPERM $A, $B, $C)>;			(QVFPERM $A, $B, $C)>;

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lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 829 Lines • ▼ Show 20 Lines	def : InstAlias<"xxswapd $XT, $XB",
(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;		(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;

let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.		let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.

let Predicates = [IsBigEndian] in {		let Predicates = [IsBigEndian] in {
def : Pat<(v2f64 (scalar_to_vector f64:$A)),		def : Pat<(v2f64 (scalar_to_vector f64:$A)),
(v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;		(v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;

def : Pat<(f64 (vector_extract v2f64:$S, 0)),		def : Pat<(f64 (extractelt v2f64:$S, 0)),
(f64 (EXTRACT_SUBREG $S, sub_64))>;		(f64 (EXTRACT_SUBREG $S, sub_64))>;
def : Pat<(f64 (vector_extract v2f64:$S, 1)),		def : Pat<(f64 (extractelt v2f64:$S, 1)),
(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;		(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
}		}

let Predicates = [IsLittleEndian] in {		let Predicates = [IsLittleEndian] in {
def : Pat<(v2f64 (scalar_to_vector f64:$A)),		def : Pat<(v2f64 (scalar_to_vector f64:$A)),
(v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),		(v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
(SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;		(SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;

def : Pat<(f64 (vector_extract v2f64:$S, 0)),		def : Pat<(f64 (extractelt v2f64:$S, 0)),
(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;		(f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
def : Pat<(f64 (vector_extract v2f64:$S, 1)),		def : Pat<(f64 (extractelt v2f64:$S, 1)),
(f64 (EXTRACT_SUBREG $S, sub_64))>;		(f64 (EXTRACT_SUBREG $S, sub_64))>;
}		}

// Additional fnmsub patterns: -ac + b == -(ac - b)		// Additional fnmsub patterns: -ac + b == -(ac - b)
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),		def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
(XSNMSUBADP $B, $C, $A)>;		(XSNMSUBADP $B, $C, $A)>;
def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),		def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
(XSNMSUBADP $B, $C, $A)>;		(XSNMSUBADP $B, $C, $A)>;
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lib/Target/Sparc/SparcInstrInfo.td

	Show First 20 Lines • Show All 1,395 Lines • ▼ Show 20 Lines
	def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;			def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
	def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;			def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;

	// atomic_store_32 val, addr -> store val, addr			// atomic_store_32 val, addr -> store val, addr
	def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;			def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
	def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;			def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;

	// extract_vector			// extract_vector
	def : Pat<(vector_extract (v2i32 IntPair:$Rn), 0),			def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
	(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;			(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
	def : Pat<(vector_extract (v2i32 IntPair:$Rn), 1),			def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
	(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;			(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;

	// build_vector			// build_vector
	def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),			def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
	(INSERT_SUBREG			(INSERT_SUBREG
	(INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),			(INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
	(i32 IntRegs:$a2), sub_odd)>;			(i32 IntRegs:$a2), sub_odd)>;


	include "SparcInstr64Bit.td"			include "SparcInstr64Bit.td"
	include "SparcInstrVIS.td"			include "SparcInstrVIS.td"
	include "SparcInstrAliases.td"			include "SparcInstrAliases.td"

lib/Target/X86/X86InstrAVX512.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 2,795 Lines • ▼ Show 20 Lines	def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],		[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;		IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
}		}

// Move doubleword from xmm register to r/m32		// Move doubleword from xmm register to r/m32
//		//
def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),		def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
"vmovd\t{$src, $dst\|$dst, $src}",		"vmovd\t{$src, $dst\|$dst, $src}",
[(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),		[(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
(iPTR 0)))], IIC_SSE_MOVD_ToGP>,		(iPTR 0)))], IIC_SSE_MOVD_ToGP>,
EVEX, VEX_LIG;		EVEX, VEX_LIG;
def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),		def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
(ins i32mem:$dst, VR128X:$src),		(ins i32mem:$dst, VR128X:$src),
"vmovd\t{$src, $dst\|$dst, $src}",		"vmovd\t{$src, $dst\|$dst, $src}",
[(store (i32 (vector_extract (v4i32 VR128X:$src),		[(store (i32 (extractelt (v4i32 VR128X:$src),
(iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,		(iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;		EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;

// Move quadword from xmm1 register to r/m64		// Move quadword from xmm1 register to r/m64
//		//
def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),		def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
"vmovq\t{$src, $dst\|$dst, $src}",		"vmovq\t{$src, $dst\|$dst, $src}",
[(set GR64:$dst, (extractelt (v2i64 VR128X:$src),		[(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines	def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
(VMOVSDZrr (v2f64 (V_SET0)),		(VMOVSDZrr (v2f64 (V_SET0)),
(EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;		(EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;

def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),		def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
(SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),		(SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
(EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;		(EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;

// Extract and store.		// Extract and store.
def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),		def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;		(VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),		def : Pat<(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;		(VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;

// Shuffle with VMOVSS		// Shuffle with VMOVSS
def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),		def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
(VMOVSSZrr (v4i32 VR128X:$src1),		(VMOVSSZrr (v4i32 VR128X:$src1),
(COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;		(COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),		def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
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lib/Target/X86/X86InstrFragmentsSIMD.td

	Show First 20 Lines • Show All 553 Lines • ▼ Show 20 Lines
	def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;			def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
	def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;			def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;

	// These are needed to match a scalar load that is used in a vector-only			// These are needed to match a scalar load that is used in a vector-only
	// math instruction such as the FP logical ops: andps, andnps, orps, xorps.			// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
	// The memory operand is required to be a 128-bit load, so it must be converted			// The memory operand is required to be a 128-bit load, so it must be converted
	// from a vector to a scalar.			// from a vector to a scalar.
	def loadf32_128 : PatFrag<(ops node:$ptr),			def loadf32_128 : PatFrag<(ops node:$ptr),
	(f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;			(f32 (extractelt (loadv4f32 node:$ptr), (iPTR 0)))>;
	def loadf64_128 : PatFrag<(ops node:$ptr),			def loadf64_128 : PatFrag<(ops node:$ptr),
	(f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;			(f64 (extractelt (loadv2f64 node:$ptr), (iPTR 0)))>;

	// Like 'store', but always requires 128-bit vector alignment.			// Like 'store', but always requires 128-bit vector alignment.
	def alignedstore : PatFrag<(ops node:$val, node:$ptr),			def alignedstore : PatFrag<(ops node:$val, node:$ptr),
	(store node:$val, node:$ptr), [{			(store node:$val, node:$ptr), [{
	return cast<StoreSDNode>(N)->getAlignment() >= 16;			return cast<StoreSDNode>(N)->getAlignment() >= 16;
	}]>;			}]>;

	// Like 'store', but always requires 256-bit vector alignment.			// Like 'store', but always requires 256-bit vector alignment.
	▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
	def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;			def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
	def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;			def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;

	// These are needed to match a scalar memop that is used in a vector-only			// These are needed to match a scalar memop that is used in a vector-only
	// math instruction such as the FP logical ops: andps, andnps, orps, xorps.			// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
	// The memory operand is required to be a 128-bit load, so it must be converted			// The memory operand is required to be a 128-bit load, so it must be converted
	// from a vector to a scalar.			// from a vector to a scalar.
	def memopfsf32_128 : PatFrag<(ops node:$ptr),			def memopfsf32_128 : PatFrag<(ops node:$ptr),
	(f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;			(f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
	def memopfsf64_128 : PatFrag<(ops node:$ptr),			def memopfsf64_128 : PatFrag<(ops node:$ptr),
	(f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;			(f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;


	// SSSE3 uses MMX registers for some instructions. They aren't aligned on a			// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
	// 16-byte boundary.			// 16-byte boundary.
	// FIXME: 8 byte alignment for mmx reads is not required			// FIXME: 8 byte alignment for mmx reads is not required
	def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{			def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
	return cast<LoadSDNode>(N)->getAlignment() >= 8;			return cast<LoadSDNode>(N)->getAlignment() >= 8;
	}]>;			}]>;
	▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

lib/Target/X86/X86InstrMMX.td

Show First 20 Lines • Show All 298 Lines • ▼ Show 20 Lines	def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
[(store (x86mmx VR64:$src), addr:$dst)],		[(store (x86mmx VR64:$src), addr:$dst)],
IIC_MMX_MOVQ_RM>;		IIC_MMX_MOVQ_RM>;

let SchedRW = [WriteMove] in {		let SchedRW = [WriteMove] in {
def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),		def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
(ins VR128:$src), "movdq2q\t{$src, $dst\|$dst, $src}",		(ins VR128:$src), "movdq2q\t{$src, $dst\|$dst, $src}",
[(set VR64:$dst,		[(set VR64:$dst,
(x86mmx (bitconvert		(x86mmx (bitconvert
(i64 (vector_extract (v2i64 VR128:$src),		(i64 (extractelt (v2i64 VR128:$src),
(iPTR 0))))))],		(iPTR 0))))))],
IIC_MMX_MOVQ_RR>;		IIC_MMX_MOVQ_RR>;

def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),		def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
(ins VR64:$src), "movq2dq\t{$src, $dst\|$dst, $src}",		(ins VR64:$src), "movq2dq\t{$src, $dst\|$dst, $src}",
[(set VR128:$dst,		[(set VR128:$dst,
(v2i64		(v2i64
(scalar_to_vector		(scalar_to_vector
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lib/Target/X86/X86InstrSSE.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Lines	def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Sched<[WriteVecLogicLd, ReadAfterLd]>;		Sched<[WriteVecLogicLd, ReadAfterLd]>;
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Non-instruction patterns		// Non-instruction patterns
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

// A vector extract of the first f32/f64 position is a subregister copy		// A vector extract of the first f32/f64 position is a subregister copy
def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),		def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
(COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;		(COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),		def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
(COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;		(COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;

// A 128-bit subvector extract from the first 256-bit vector position		// A 128-bit subvector extract from the first 256-bit vector position
// is a subregister copy that needs no instruction.		// is a subregister copy that needs no instruction.
def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),		def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
(v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;		(v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),		def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
(v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;		(v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
▲ Show 20 Lines • Show All 301 Lines • ▼ Show 20 Lines	def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
(v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),		(v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
(SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,		def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
(v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),		(v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
(SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
}		}

// Extract and store.		// Extract and store.
def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),		def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;		(VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),		def : Pat<(store (f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;		(VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;

// Shuffle with VMOVSS		// Shuffle with VMOVSS
def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),		def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
(VMOVSSrr (v4i32 VR128:$src1),		(VMOVSSrr (v4i32 VR128:$src1),
(COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;		(COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),		def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines	def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),		def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),		def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
}		}

// Extract and store.		// Extract and store.
def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),		def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;		(MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;

// Shuffle with MOVSS		// Shuffle with MOVSS
def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),		def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
(MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;		(MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),		def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
(MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;		(MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
Show All 17 Lines	def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),		def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
def : Pat<(v2f64 (X86vzload addr:$src)),		def : Pat<(v2f64 (X86vzload addr:$src)),
(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;		(COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
}		}

// Extract and store.		// Extract and store.
def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),		def : Pat<(store (f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
addr:$dst),		addr:$dst),
(MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;		(MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;

// Shuffle with MOVSD		// Shuffle with MOVSD
def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),		def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
(MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;		(MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),		def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
(MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;		(MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
▲ Show 20 Lines • Show All 403 Lines • ▼ Show 20 Lines
let AddedComplexity = 20 in {		let AddedComplexity = 20 in {
defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",		defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
IIC_SSE_MOV_LH>;		IIC_SSE_MOV_LH>;
}		}

let SchedRW = [WriteStore] in {		let SchedRW = [WriteStore] in {
def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movlps\t{$src, $dst\|$dst, $src}",		"movlps\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),		[(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOV_LH>, VEX;		IIC_SSE_MOV_LH>, VEX;
def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movlpd\t{$src, $dst\|$dst, $src}",		"movlpd\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract (v2f64 VR128:$src),		[(store (f64 (extractelt (v2f64 VR128:$src),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOV_LH>, VEX;		IIC_SSE_MOV_LH>, VEX;
def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movlps\t{$src, $dst\|$dst, $src}",		"movlps\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),		[(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOV_LH>;		IIC_SSE_MOV_LH>;
def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movlpd\t{$src, $dst\|$dst, $src}",		"movlpd\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract (v2f64 VR128:$src),		[(store (f64 (extractelt (v2f64 VR128:$src),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOV_LH>;		IIC_SSE_MOV_LH>;
} // SchedRW		} // SchedRW

let Predicates = [HasAVX] in {		let Predicates = [HasAVX] in {
// Shuffle with VMOVLPS		// Shuffle with VMOVLPS
def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),		def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
(VMOVLPSrm VR128:$src1, addr:$src2)>;		(VMOVLPSrm VR128:$src1, addr:$src2)>;
Show All 21 Lines	def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
(VMOVLPDmr addr:$src1, VR128:$src2)>;		(VMOVLPDmr addr:$src1, VR128:$src2)>;
def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),		def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
addr:$src1),		addr:$src1),
(VMOVLPDmr addr:$src1, VR128:$src2)>;		(VMOVLPDmr addr:$src1, VR128:$src2)>;
}		}

let Predicates = [UseSSE1] in {		let Predicates = [UseSSE1] in {
// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS		// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),		def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32 VR128:$src2)),
(iPTR 0))), addr:$src1),		(iPTR 0))), addr:$src1),
(MOVLPSmr addr:$src1, VR128:$src2)>;		(MOVLPSmr addr:$src1, VR128:$src2)>;

// Shuffle with MOVLPS		// Shuffle with MOVLPS
def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),		def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
(MOVLPSrm VR128:$src1, addr:$src2)>;		(MOVLPSrm VR128:$src1, addr:$src2)>;
def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),		def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
(MOVLPSrm VR128:$src1, addr:$src2)>;		(MOVLPSrm VR128:$src1, addr:$src2)>;
Show All 39 Lines	defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
IIC_SSE_MOV_LH>;		IIC_SSE_MOV_LH>;
}		}

let SchedRW = [WriteStore] in {		let SchedRW = [WriteStore] in {
// v2f64 extract element 1 is always custom lowered to unpack high to low		// v2f64 extract element 1 is always custom lowered to unpack high to low
// and extract element 0 so the non-store version isn't too horrible.		// and extract element 0 so the non-store version isn't too horrible.
def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst\|$dst, $src}",		"movhps\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract		[(store (f64 (extractelt
(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),		(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(bc_v2f64 (v4f32 VR128:$src))),		(bc_v2f64 (v4f32 VR128:$src))),
(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;		(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst\|$dst, $src}",		"movhpd\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract		[(store (f64 (extractelt
(v2f64 (X86Unpckh VR128:$src, VR128:$src)),		(v2f64 (X86Unpckh VR128:$src, VR128:$src)),
(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;		(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst\|$dst, $src}",		"movhps\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract		[(store (f64 (extractelt
(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),		(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(bc_v2f64 (v4f32 VR128:$src))),		(bc_v2f64 (v4f32 VR128:$src))),
(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;		(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),		def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst\|$dst, $src}",		"movhpd\t{$src, $dst\|$dst, $src}",
[(store (f64 (vector_extract		[(store (f64 (extractelt
(v2f64 (X86Unpckh VR128:$src, VR128:$src)),		(v2f64 (X86Unpckh VR128:$src, VR128:$src)),
(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;		(iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
} // SchedRW		} // SchedRW

let Predicates = [HasAVX] in {		let Predicates = [HasAVX] in {
// VMOVHPS patterns		// VMOVHPS patterns
def : Pat<(X86Movlhps VR128:$src1,		def : Pat<(X86Movlhps VR128:$src1,
(bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),		(bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
Show All 12 Lines	def : Pat<(v2f64 (X86Unpckl VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))),		(scalar_to_vector (loadf64 addr:$src2)))),
(VMOVHPDrm VR128:$src1, addr:$src2)>;		(VMOVHPDrm VR128:$src1, addr:$src2)>;
// Also handle an i64 load because that may get selected as a faster way to		// Also handle an i64 load because that may get selected as a faster way to
// load the data.		// load the data.
def : Pat<(v2f64 (X86Unpckl VR128:$src1,		def : Pat<(v2f64 (X86Unpckl VR128:$src1,
(bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),		(bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
(VMOVHPDrm VR128:$src1, addr:$src2)>;		(VMOVHPDrm VR128:$src1, addr:$src2)>;

def : Pat<(store (f64 (vector_extract		def : Pat<(store (f64 (extractelt
(v2f64 (X86VPermilpi VR128:$src, (i8 1))),		(v2f64 (X86VPermilpi VR128:$src, (i8 1))),
(iPTR 0))), addr:$dst),		(iPTR 0))), addr:$dst),
(VMOVHPDmr addr:$dst, VR128:$src)>;		(VMOVHPDmr addr:$dst, VR128:$src)>;
}		}

let Predicates = [UseSSE1] in {		let Predicates = [UseSSE1] in {
// MOVHPS patterns		// MOVHPS patterns
def : Pat<(X86Movlhps VR128:$src1,		def : Pat<(X86Movlhps VR128:$src1,
Show All 15 Lines	def : Pat<(v2f64 (X86Unpckl VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))),		(scalar_to_vector (loadf64 addr:$src2)))),
(MOVHPDrm VR128:$src1, addr:$src2)>;		(MOVHPDrm VR128:$src1, addr:$src2)>;
// Also handle an i64 load because that may get selected as a faster way to		// Also handle an i64 load because that may get selected as a faster way to
// load the data.		// load the data.
def : Pat<(v2f64 (X86Unpckl VR128:$src1,		def : Pat<(v2f64 (X86Unpckl VR128:$src1,
(bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),		(bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
(MOVHPDrm VR128:$src1, addr:$src2)>;		(MOVHPDrm VR128:$src1, addr:$src2)>;

def : Pat<(store (f64 (vector_extract		def : Pat<(store (f64 (extractelt
(v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),		(v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
(iPTR 0))), addr:$dst),		(iPTR 0))), addr:$dst),
(MOVHPDmr addr:$dst, VR128:$src)>;		(MOVHPDmr addr:$dst, VR128:$src)>;
}		}

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions		// SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 1,795 Lines • ▼ Show 20 Lines
// addss %xmm1, %xmm0		// addss %xmm1, %xmm0

// TODO: Some canonicalization in lowering would simplify the number of		// TODO: Some canonicalization in lowering would simplify the number of
// patterns we have to try to match.		// patterns we have to try to match.
multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {		multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
let Predicates = [UseSSE1] in {		let Predicates = [UseSSE1] in {
// extracted scalar math op with insert via movss		// extracted scalar math op with insert via movss
def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector		def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
(Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),		(Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
FR32:$src))))),		FR32:$src))))),
(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,		(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
(COPY_TO_REGCLASS FR32:$src, VR128))>;		(COPY_TO_REGCLASS FR32:$src, VR128))>;

// vector math op with insert via movss		// vector math op with insert via movss
def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),		def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),		(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;		(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
}		}

// With SSE 4.1, blendi is preferred to movsd, so match that too.		// With SSE 4.1, blendi is preferred to movsd, so match that too.
let Predicates = [UseSSE41] in {		let Predicates = [UseSSE41] in {
// extracted scalar math op with insert via blend		// extracted scalar math op with insert via blend
def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector		def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
(Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),		(Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
FR32:$src))), (i8 1))),		FR32:$src))), (i8 1))),
(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,		(!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
(COPY_TO_REGCLASS FR32:$src, VR128))>;		(COPY_TO_REGCLASS FR32:$src, VR128))>;

// vector math op with insert via blend		// vector math op with insert via blend
def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),		def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),		(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
(!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;		(!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;

}		}

// Repeat everything for AVX, except for the movss + scalar combo...		// Repeat everything for AVX, except for the movss + scalar combo...
// because that one shouldn't occur with AVX codegen?		// because that one shouldn't occur with AVX codegen?
let Predicates = [HasAVX] in {		let Predicates = [HasAVX] in {
// extracted scalar math op with insert via blend		// extracted scalar math op with insert via blend
def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector		def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
(Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),		(Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
FR32:$src))), (i8 1))),		FR32:$src))), (i8 1))),
(!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,		(!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
(COPY_TO_REGCLASS FR32:$src, VR128))>;		(COPY_TO_REGCLASS FR32:$src, VR128))>;

// vector math op with insert via movss		// vector math op with insert via movss
def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),		def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),		(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
(!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;		(!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
Show All 9 Lines
defm : scalar_math_f32_patterns<fsub, "SUB">;		defm : scalar_math_f32_patterns<fsub, "SUB">;
defm : scalar_math_f32_patterns<fmul, "MUL">;		defm : scalar_math_f32_patterns<fmul, "MUL">;
defm : scalar_math_f32_patterns<fdiv, "DIV">;		defm : scalar_math_f32_patterns<fdiv, "DIV">;

multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {		multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
let Predicates = [UseSSE2] in {		let Predicates = [UseSSE2] in {
// extracted scalar math op with insert via movsd		// extracted scalar math op with insert via movsd
def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector		def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
(Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),		(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
FR64:$src))))),		FR64:$src))))),
(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,		(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
(COPY_TO_REGCLASS FR64:$src, VR128))>;		(COPY_TO_REGCLASS FR64:$src, VR128))>;

// vector math op with insert via movsd		// vector math op with insert via movsd
def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),		def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),		(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;		(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
}		}

// With SSE 4.1, blendi is preferred to movsd, so match those too.		// With SSE 4.1, blendi is preferred to movsd, so match those too.
let Predicates = [UseSSE41] in {		let Predicates = [UseSSE41] in {
// extracted scalar math op with insert via blend		// extracted scalar math op with insert via blend
def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector		def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
(Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),		(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
FR64:$src))), (i8 1))),		FR64:$src))), (i8 1))),
(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,		(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
(COPY_TO_REGCLASS FR64:$src, VR128))>;		(COPY_TO_REGCLASS FR64:$src, VR128))>;

// vector math op with insert via blend		// vector math op with insert via blend
def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),		def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),		(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;		(!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
}		}

// Repeat everything for AVX.		// Repeat everything for AVX.
let Predicates = [HasAVX] in {		let Predicates = [HasAVX] in {
// extracted scalar math op with insert via movsd		// extracted scalar math op with insert via movsd
def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector		def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
(Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),		(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
FR64:$src))))),		FR64:$src))))),
(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,		(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
(COPY_TO_REGCLASS FR64:$src, VR128))>;		(COPY_TO_REGCLASS FR64:$src, VR128))>;

// extracted scalar math op with insert via blend		// extracted scalar math op with insert via blend
def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector		def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
(Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),		(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
FR64:$src))), (i8 1))),		FR64:$src))), (i8 1))),
(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,		(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
(COPY_TO_REGCLASS FR64:$src, VR128))>;		(COPY_TO_REGCLASS FR64:$src, VR128))>;

// vector math op with insert via movsd		// vector math op with insert via movsd
def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),		def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),		(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;		(!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
▲ Show 20 Lines • Show All 1,480 Lines • ▼ Show 20 Lines	def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;		IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
}		}

//===---------------------------------------------------------------------===//		//===---------------------------------------------------------------------===//
// Move Packed Doubleword Int to Packed Double Int		// Move Packed Doubleword Int to Packed Double Int
//		//
def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),		def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
"movd\t{$src, $dst\|$dst, $src}",		"movd\t{$src, $dst\|$dst, $src}",
[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),		[(set GR32:$dst, (extractelt (v4i32 VR128:$src),
(iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,		(iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
Sched<[WriteMove]>;		Sched<[WriteMove]>;
def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),		def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
(ins i32mem:$dst, VR128:$src),		(ins i32mem:$dst, VR128:$src),
"movd\t{$src, $dst\|$dst, $src}",		"movd\t{$src, $dst\|$dst, $src}",
[(store (i32 (vector_extract (v4i32 VR128:$src),		[(store (i32 (extractelt (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,		(iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
VEX, Sched<[WriteStore]>;		VEX, Sched<[WriteStore]>;
def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),		def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
"movd\t{$src, $dst\|$dst, $src}",		"movd\t{$src, $dst\|$dst, $src}",
[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),		[(set GR32:$dst, (extractelt (v4i32 VR128:$src),
(iPTR 0)))], IIC_SSE_MOVD_ToGP>,		(iPTR 0)))], IIC_SSE_MOVD_ToGP>,
Sched<[WriteMove]>;		Sched<[WriteMove]>;
def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),		def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
"movd\t{$src, $dst\|$dst, $src}",		"movd\t{$src, $dst\|$dst, $src}",
[(store (i32 (vector_extract (v4i32 VR128:$src),		[(store (i32 (extractelt (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOVDQ>, Sched<[WriteStore]>;		IIC_SSE_MOVDQ>, Sched<[WriteStore]>;

def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),		def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
(SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;

def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),		def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
(SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;

def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),		def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
(SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;

def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),		def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
(SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;		(SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;

//===---------------------------------------------------------------------===//		//===---------------------------------------------------------------------===//
// Move Packed Doubleword Int first element to Doubleword Int		// Move Packed Doubleword Int first element to Doubleword Int
//		//
let SchedRW = [WriteMove] in {		let SchedRW = [WriteMove] in {
def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),		def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
"movq\t{$src, $dst\|$dst, $src}",		"movq\t{$src, $dst\|$dst, $src}",
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),		[(set GR64:$dst, (extractelt (v2i64 VR128:$src),
(iPTR 0)))],		(iPTR 0)))],
IIC_SSE_MOVD_ToGP>,		IIC_SSE_MOVD_ToGP>,
VEX;		VEX;

def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),		def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
"mov{d\|q}\t{$src, $dst\|$dst, $src}",		"mov{d\|q}\t{$src, $dst\|$dst, $src}",
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),		[(set GR64:$dst, (extractelt (v2i64 VR128:$src),
(iPTR 0)))],		(iPTR 0)))],
IIC_SSE_MOVD_ToGP>;		IIC_SSE_MOVD_ToGP>;
} //SchedRW		} //SchedRW

let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in		let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),		def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
(ins VR128:$src), "movq\t{$src, $dst\|$dst, $src}",		(ins VR128:$src), "movq\t{$src, $dst\|$dst, $src}",
[], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;		[], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
} // ExeDomain, SchedRW		} // ExeDomain, SchedRW

//===---------------------------------------------------------------------===//		//===---------------------------------------------------------------------===//
// Move Packed Quadword Int to Quadword Int		// Move Packed Quadword Int to Quadword Int
//		//
let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {		let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),		def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
"movq\t{$src, $dst\|$dst, $src}",		"movq\t{$src, $dst\|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),		[(store (i64 (extractelt (v2i64 VR128:$src),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOVDQ>, VEX;		IIC_SSE_MOVDQ>, VEX;
def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),		def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
"movq\t{$src, $dst\|$dst, $src}",		"movq\t{$src, $dst\|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),		[(store (i64 (extractelt (v2i64 VR128:$src),
(iPTR 0))), addr:$dst)],		(iPTR 0))), addr:$dst)],
IIC_SSE_MOVDQ>;		IIC_SSE_MOVDQ>;
} // ExeDomain, SchedRW		} // ExeDomain, SchedRW

// For disassembler only		// For disassembler only
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,		let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
SchedRW = [WriteVecLogic] in {		SchedRW = [WriteVecLogic] in {
def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),		def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
▲ Show 20 Lines • Show All 3,234 Lines • ▼ Show 20 Lines	let Predicates = [HasF16C] in {
defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;		defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;

// Pattern match vcvtph2ps of a scalar i64 load.		// Pattern match vcvtph2ps of a scalar i64 load.
def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),		def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
(VCVTPH2PSrm addr:$src)>;		(VCVTPH2PSrm addr:$src)>;
def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),		def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
(VCVTPH2PSrm addr:$src)>;		(VCVTPH2PSrm addr:$src)>;

def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16		def : Pat<(store (f64 (extractelt (bc_v2f64 (v8i16
(int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),		(int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
addr:$dst),		addr:$dst),
(VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;		(VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16		def : Pat<(store (i64 (extractelt (bc_v2i64 (v8i16
(int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),		(int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
addr:$dst),		addr:$dst),
(VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;		(VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),		def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
addr:$dst),		addr:$dst),
(VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;		(VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
}		}

▲ Show 20 Lines • Show All 602 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

Start replacing vector_extract/vector_insert with extractelt/inserteltClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 36522

lib/Target/AArch64/AArch64InstrInfo.td

lib/Target/AMDGPU/AMDGPUInstructions.td

lib/Target/AMDGPU/SIInstructions.td

lib/Target/NVPTX/NVPTXVector.td

lib/Target/PowerPC/PPCInstrQPX.td

lib/Target/PowerPC/PPCInstrVSX.td

lib/Target/Sparc/SparcInstrInfo.td

lib/Target/X86/X86InstrAVX512.td

lib/Target/X86/X86InstrFragmentsSIMD.td

lib/Target/X86/X86InstrMMX.td

lib/Target/X86/X86InstrSSE.td

Start replacing vector_extract/vector_insert with extractelt/insertelt
ClosedPublic