[AVR] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

It renames a few fields to have consistent names, as well as renaming
operands to match the field names.

The encoder behavior is unchanged by this cleanup, but a few
instructions were previously being disassembled incorrectly, and have
been corrected by this change. All of the affected instructions were
missing disassembly tests, which are now added.

[MaskRay]

Thanks!

llvm/test/MC/AVR/inst-rjmp.s

36

This can use INST-COUNT-8:

llvm/test/MC/AVR/inst-sbrs.s

2

< %s => %s

[benshi001]

this is non functional change, it would be better to retitled to [NFC][AVR] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

this is non functional change, it would be better to retitled to [NFC][AVR] Fix useDeprecatedPositionallyEncodedOperands errors.

It is not; it fixes bugs in the disassembler as noted in the change description.

[benshi001]

Thanks.

[jyknight]

llvm/test/MC/AVR/inst-rjmp.s

36

I'd rather not, just for clarity.

llvm/test/MC/AVR/inst-sbrs.s

2

Any particular reason? Most such tests (e.g. the line above) seem to use < %s currently.

llvm/lib/Target/AVR/AVR.td

 include "AVRRegisterInfo.td"
 
 //===---------------------------------------------------------------------===//
 // Instruction Descriptions
 //===---------------------------------------------------------------------===//
 
 include "AVRInstrInfo.td"
 
-def AVRInstrInfo : InstrInfo {
-  let useDeprecatedPositionallyEncodedOperands = true;
-}
+def AVRInstrInfo : InstrInfo;
 
 //===---------------------------------------------------------------------===//
 // Calling Conventions
 //===---------------------------------------------------------------------===//
 
 include "AVRCallingConv.td"
 
 //===---------------------------------------------------------------------===//

llvm/lib/Target/AVR/AVRInstrFormats.td

 // Register instruction: <|opcode|fffd|dddd|ffff|>
 // opcode = 4 bits.
 // f = secondary opcode = 7 bits
 // d = destination = 5 bits
 // (Accepts all registers)
 //===----------------------------------------------------------------------===//
 class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
           list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> d;
+  bits<5> rd;
 
   let Inst{15 - 12} = opcode;
   let Inst{11 - 9} = f{6 - 4};
-  let Inst{8 - 4} = d;
+  let Inst{8 - 4} = rd;
   let Inst{3 - 0} = f{3 - 0};
 
   let DecoderMethod = "decodeFRd";
 }
 
 //===----------------------------------------------------------------------===//
 // [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq>
 // t = type (1 for STD, 0 for LDD)

 // [E]LPM Rd, Z[+]
 // <|1001|000d|dddd|01ep>
 // d = destination register
 // e = is elpm
 // p = is postincrement
 //===---------------------------------------------------------------------===//
 class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> reg;
+  bits<5> rd;
 
   let Inst{15 - 12} = 0b1001;
 
   let Inst{11 - 9} = 0b000;
-  let Inst{8} = reg{4};
+  let Inst{8} = rd{4};
 
-  let Inst{7 - 4} = reg{3 - 0};
+  let Inst{7 - 4} = rd{3 - 0};
 
   let Inst{3 - 2} = 0b01;
   let Inst{1} = e;
   let Inst{0} = p;
 
   let DecoderMethod = "decodeFLPMX";
 }
 
 //===----------------------------------------------------------------------===//
 // MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|>
 // d = destination = 4 bits
 // r = source = 4 bits
 // (Only accepts even registers)
 //===----------------------------------------------------------------------===//
 class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> d;
-  bits<5> r;
+  bits<5> rd;
+  bits<5> rr;
 
   let Inst{15 - 8} = 0b00000001;
-  let Inst{7 - 4} = d{4 - 1};
-  let Inst{3 - 0} = r{4 - 1};
+  let Inst{7 - 4} = rd{4 - 1};
+  let Inst{3 - 0} = rr{4 - 1};
 
   let DecoderMethod = "decodeFMOVWRdRr";
 }
 
 //===----------------------------------------------------------------------===//
 // MULSrr special encoding: <|0000|0010|dddd|rrrr|>
 // d = multiplicand = 4 bits
 // r = multiplier = 4 bits
class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
 
   let DecoderMethod = "decodeFFMULRdRr";
 }
 
 //===----------------------------------------------------------------------===//
 // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
 // f = secondary opcode = 1 bit
 // k = constant data = 6 bits
-// d = destination = 4 bits
+// d = destination = 2 bits
 // (Only accepts r25:24 r27:26 r29:28 r31:30)
 //===----------------------------------------------------------------------===//
 class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> dst; // accept 5 bits but only encode bits 1 and 2
+  bits<5> rd; // accept 5 bits but only encode bits 1 and 2
   bits<6> k;
 
   let Inst{15 - 9} = 0b1001011;
   let Inst{8} = f;
   let Inst{7 - 6} = k{5 - 4};
-  let Inst{5 - 4} = dst{2 - 1};
+  let Inst{5 - 4} = rd{2 - 1};
   let Inst{3 - 0} = k{3 - 0};
 
   let DecoderMethod = "decodeFWRdK";
 }
 
 //===----------------------------------------------------------------------===//
 // In I/O instruction: <|1011|0AAd|dddd|AAAA|>
 // A = I/O location address = 6 bits
 // d = destination = 5 bits
 // (Accepts all registers)
 //===----------------------------------------------------------------------===//
 class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> d;
+  bits<5> rd;
   bits<6> A;
 
   let Inst{15 - 11} = 0b10110;
   let Inst{10 - 9} = A{5 - 4};
-  let Inst{8 - 4} = d;
+  let Inst{8 - 4} = rd;
   let Inst{3 - 0} = A{3 - 0};
 
   let DecoderMethod = "decodeFIORdA";
 }
 
 //===----------------------------------------------------------------------===//
 // Out I/O instruction: <|1011|1AAr|rrrr|AAAA|>
 // A = I/O location address = 6 bits
 // d = destination = 5 bits
 // (Accepts all registers)
 //===----------------------------------------------------------------------===//
 class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
   bits<6> A;
-  bits<5> r;
+  bits<5> rr;
 
   let Inst{15 - 11} = 0b10111;
   let Inst{10 - 9} = A{5 - 4};
-  let Inst{8 - 4} = r;
+  let Inst{8 - 4} = rr;
   let Inst{3 - 0} = A{3 - 0};
 
   let DecoderMethod = "decodeFIOARr";
 }
 
 //===----------------------------------------------------------------------===//
 // I/O bit instruction.
 // <|1001|10tt|AAAA|Abbb>
 // t = type (1 for SBI, 0 for CBI)
 // A = I/O location address (5 bits)
 // b = bit number
 //===----------------------------------------------------------------------===//
 class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> A;
+  bits<5> addr;
   bits<3> b;
 
   let Inst{15 - 12} = 0b1001;
 
   let Inst{11 - 10} = 0b10;
   let Inst{9 - 8} = t;
 
-  let Inst{7 - 4} = A{4 - 1};
+  let Inst{7 - 4} = addr{4 - 1};
 
-  let Inst{3} = A{0};
+  let Inst{3} = addr{0};
   let Inst{2 - 0} = b{2 - 0};
 
   let DecoderMethod = "decodeFIOBIT";
 }
 
 //===----------------------------------------------------------------------===//
 // BST/BLD instruction.
 // <|1111|1ttd|dddd|0bbb>

llvm/lib/Target/AVR/AVRInstrInfo.td

 //===----------------------------------------------------------------------===//
 
 let isCommutable = 1, Defs = [R1, R0, SREG] in {
   // MUL Rd, Rr
   // Multiplies Rd by Rr and places the result into R1:R0.
   let usesCustomInserter = 1 in {
     def MULRdRr : FRdRr<0b1001, 0b11, (outs),
                         (ins GPR8
-                         : $lhs, GPR8
-                         : $rhs),
-                        "mul\t$lhs, $rhs",
-                        [/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
+                         : $rd, GPR8
+                         : $rr),
+                        "mul\t$rd, $rr",
+                        [/*(set R1, R0, (smullohi i8:$rd, i8:$rr))*/]>,
                   Requires<[SupportsMultiplication]>;
 
     def MULSRdRr : FMUL2RdRr<0, (outs),
                              (ins LD8
-                              : $lhs, LD8
-                              : $rhs),
-                             "muls\t$lhs, $rhs", []>,
+                              : $rd, LD8
+                              : $rr),
+                             "muls\t$rd, $rr", []>,
                    Requires<[SupportsMultiplication]>;
   }
 
   def MULSURdRr : FMUL2RdRr<1, (outs),
                             (ins LD8lo
-                             : $lhs, LD8lo
-                             : $rhs),
-                            "mulsu\t$lhs, $rhs", []>,
+                             : $rd, LD8lo
+                             : $rr),
+                            "mulsu\t$rd, $rr", []>,
                   Requires<[SupportsMultiplication]>;
 
   def FMUL : FFMULRdRr<0b01, (outs),
                        (ins LD8lo
-                        : $lhs, LD8lo
-                        : $rhs),
-                       "fmul\t$lhs, $rhs", []>,
+                        : $rd, LD8lo
+                        : $rr),
+                       "fmul\t$rd, $rr", []>,
              Requires<[SupportsMultiplication]>;
 
   def FMULS : FFMULRdRr<0b10, (outs),
                         (ins LD8lo
-                         : $lhs, LD8lo
-                         : $rhs),
-                        "fmuls\t$lhs, $rhs", []>,
+                         : $rd, LD8lo
+                         : $rr),
+                        "fmuls\t$rd, $rr", []>,
               Requires<[SupportsMultiplication]>;
 
   def FMULSU : FFMULRdRr<0b11, (outs),
                          (ins LD8lo
-                          : $lhs, LD8lo
-                          : $rhs),
-                         "fmulsu\t$lhs, $rhs", []>,
+                          : $rd, LD8lo
+                          : $rr),
+                         "fmulsu\t$rd, $rr", []>,
                Requires<[SupportsMultiplication]>;
 }
 
 let Defs =
     [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1,
      R0] in def DESK : FDES<(outs),
                             (ins i8imm
                              : $k),
def : InstAlias<"sbr\t$rd, $k",
                 /* Disable display, so we don't override ORI */ 0>;
 
 //===----------------------------------------------------------------------===//
 // Jump instructions
 //===----------------------------------------------------------------------===//
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
   def RJMPk : FBRk<0, (outs),
                    (ins brtarget_13
-                    : $target),
-                   "rjmp\t$target", [(br bb
-                                      : $target)]>;
+                    : $k),
+                   "rjmp\t$k", [(br bb
+                                 : $k)]>;
 
   let isIndirectBranch = 1,
       Uses = [R31R30] in def IJMP
       : F16<0b1001010000001001, (outs), (ins), "ijmp", []>,
       Requires<[HasIJMPCALL]>;
 
   let isIndirectBranch = 1,
       Uses = [R31R30] in def EIJMP

 // Register conditional skipping/branching operations.
 //===----------------------------------------------------------------------===//
 let isBranch = 1, isTerminator = 1 in {
   // Conditional skipping on GPR register bits, and
   // conditional skipping on IO register bits.
   let isBarrier = 1 in {
     def SBRCRrB : FRdB<0b10, (outs),
                        (ins GPR8
-                        : $rr, i8imm
+                        : $rd, i8imm
                         : $b),
-                       "sbrc\t$rr, $b", []>;
+                       "sbrc\t$rd, $b", []>;
 
     def SBRSRrB : FRdB<0b11, (outs),
                        (ins GPR8
-                        : $rr, i8imm
+                        : $rd, i8imm
                         : $b),
-                       "sbrs\t$rr, $b", []>;
+                       "sbrs\t$rd, $b", []>;
 
     def SBICAb : FIOBIT<0b01, (outs),
                         (ins imm_port5
-                         : $a, i8imm
+                         : $addr, i8imm
                          : $b),
-                        "sbic\t$a, $b", []>;
+                        "sbic\t$addr, $b", []>;
 
     def SBISAb : FIOBIT<0b11, (outs),
                         (ins imm_port5
-                         : $a, i8imm
+                         : $addr, i8imm
                          : $b),
-                        "sbis\t$a, $b", []>;
+                        "sbis\t$addr, $b", []>;
   }
 
   // Relative branches on status flag bits.
   let Uses = [SREG] in {
     // BRBS s, k
     // Branch if `s` flag in status register is set.
     def BRBSsk : FSK<0, (outs),
                      (ins i8imm

 //===----------------------------------------------------------------------===//
 // PC-relative conditional branches
 //===----------------------------------------------------------------------===//
 // Based on status register. We cannot simplify these into instruction aliases
 // because we also need to be able to specify a pattern to match for ISel.
 let isBranch = 1, isTerminator = 1, Uses = [SREG] in {
   def BREQk : FBRsk<0, 0b001, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "breq\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_EQ)]>;
+                     : $k),
+                    "breq\t$k", [(AVRbrcond bb
+                                  : $k, AVR_COND_EQ)]>;
 
   def BRNEk : FBRsk<1, 0b001, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brne\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_NE)]>;
+                     : $k),
+                    "brne\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_NE)]>;
 
   def BRSHk : FBRsk<1, 0b000, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brsh\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_SH)]>;
+                     : $k),
+                    "brsh\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_SH)]>;
 
   def BRLOk : FBRsk<0, 0b000, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brlo\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_LO)]>;
+                     : $k),
+                    "brlo\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_LO)]>;
 
   def BRMIk : FBRsk<0, 0b010, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brmi\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_MI)]>;
+                     : $k),
+                    "brmi\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_MI)]>;
 
   def BRPLk : FBRsk<1, 0b010, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brpl\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_PL)]>;
+                     : $k),
+                    "brpl\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_PL)]>;
 
   def BRGEk : FBRsk<1, 0b100, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brge\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_GE)]>;
+                     : $k),
+                    "brge\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_GE)]>;
 
   def BRLTk : FBRsk<0, 0b100, (outs),
                     (ins relbrtarget_7
-                     : $target),
-                    "brlt\t$target", [(AVRbrcond bb
-                                       : $target, AVR_COND_LT)]>;
+                     : $k),
+                    "brlt\t$k", [(AVRbrcond bb
+                                 : $k, AVR_COND_LT)]>;
 }
 
 //===----------------------------------------------------------------------===//
 // Data transfer instructions
 //===----------------------------------------------------------------------===//
 // 8 and 16-bit register move instructions.
 let hasSideEffects = 0 in {
   def MOVRdRr : FRdRr<0b0010, 0b11,
                       (outs GPR8
                        : $rd),
                       (ins GPR8
                        : $rr),
                       "mov\t$rd, $rr", []>;
 
   def MOVWRdRr : FMOVWRdRr<(outs DREGS
-                            : $dst),
+                            : $rd),
                            (ins DREGS
-                            : $src),
-                           "movw\t$dst, $src", []>,
+                            : $rr),
+                           "movw\t$rd, $rr", []>,
                  Requires<[HasMOVW]>;
 }
 
 // Load immediate values into registers.
 let isReMaterializable = 1 in {
   def LDIRdK : FRdK<0b1110,
                     (outs LD8
                      : $rd),
let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,
     hasSideEffects = 0 in {
   let Defs = [R0],
       Uses = [R31R30] in def LPM
       : F16<0b1001010111001000, (outs), (ins), "lpm", []>,
       Requires<[HasLPM]>;
 
   def LPMRdZ : FLPMX<0, 0,
                      (outs GPR8
-                      : $dst),
+                      : $rd),
                      (ins ZREG
                       : $z),
-                     "lpm\t$dst, $z", []>,
+                     "lpm\t$rd, $z", []>,
                Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
   let Defs = [R31R30] in {
     def LPMRdZPi : FLPMX<0, 1,
                          (outs GPR8
-                          : $dst),
+                          : $rd),
                          (ins ZREG
                           : $z),
-                         "lpm\t$dst, $z+", []>,
+                         "lpm\t$rd, $z+", []>,
                    Requires<[HasLPMX]>;
 
     def LPMWRdZ : Pseudo<(outs DREGS
                           : $dst),
                          (ins ZREG
                           : $z),
                          "lpmw\t$dst, $z", []>,
                   Requires<[HasLPMX]>;

 
 // Extended load program memory operations.
 let mayLoad = 1, hasSideEffects = 0 in {
   let Defs = [R0],
       Uses = [R31R30] in def ELPM
       : F16<0b1001010111011000, (outs), (ins), "elpm", []>,
       Requires<[HasELPM]>;
 
-  def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$dst), (ins ZREG:$z),
-                      "elpm\t$dst, $z", []>,
+  def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$rd), (ins ZREG:$z),
+                      "elpm\t$rd, $z", []>,
                 Requires<[HasELPMX]>;
 
   let Defs = [R31R30] in {
-    def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$dst), (ins ZREG:$z),
-                          "elpm\t$dst, $z+", []>,
+    def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$rd), (ins ZREG:$z),
+                          "elpm\t$rd, $z+", []>,
                     Requires<[HasELPMX]>;
   }
 
   // These pseudos are combination of the OUT and ELPM instructions.
   let Defs = [R31R30], hasSideEffects = 1 in {
     def ELPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p),
                           "elpmb\t$dst, $z, $p", []>,
                    Requires<[HasELPMX]>;
let Defs = [R31R30] in def SPMZPi : F16<0b1001010111111000, (outs),
                                            : $z),
                                           "spm $z+", []>,
       Requires<[HasSPMX]>;
 }
 
 // Read data from IO location operations.
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def INRdA : FIORdA<(outs GPR8
-                      : $dst),
+                      : $rd),
                      (ins imm_port6
-                      : $src),
-                     "in\t$dst, $src", [(set i8
-                                         : $dst, (load ioaddr8
-                                                  : $src))]>;
+                      : $A),
+                     "in\t$rd, $A", [(set i8
+                                         : $rd, (load ioaddr8
+                                                  : $A))]>;
 
   def INWRdA : Pseudo<(outs DREGS
                        : $dst),
                       (ins imm_port6
                        : $src),
                       "inw\t$dst, $src", [(set i16
                                            : $dst, (load ioaddr16
                                                     : $src))]>;
 }
 
 // Write data to IO location operations.
 def OUTARr : FIOARr<(outs),
                     (ins imm_port6
-                     : $dst, GPR8
-                     : $src),
-                    "out\t$dst, $src", [(store i8
-                                         : $src, ioaddr8
-                                         : $dst)]>;
+                     : $A, GPR8
+                     : $rr),
+                    "out\t$A, $rr", [(store i8
+                                         : $rr, ioaddr8
+                                         : $A)]>;
 
 def OUTWARr : Pseudo<(outs),
                      (ins imm_port6
                       : $dst, DREGS
                       : $src),
                      "outw\t$dst, $src", [(store i16
                                            : $src, ioaddr16
                                            : $dst)]>;
 
 // Stack push/pop operations.
 let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
   // Stack push operations.
   let mayStore = 1 in {
     def PUSHRr : FRd<0b1001, 0b0011111, (outs),
                      (ins GPR8
-                      : $reg),
-                     "push\t$reg", []>,
+                      : $rd),
+                     "push\t$rd", []>,
                  Requires<[HasSRAM]>;
 
     def PUSHWRr : Pseudo<(outs),
                          (ins DREGS
                           : $reg),
                          "pushw\t$reg", []>,
                   Requires<[HasSRAM]>;
   }
 
   // Stack pop operations.
   let mayLoad = 1 in {
     def POPRd : FRd<0b1001, 0b0001111,
                     (outs GPR8
-                     : $reg),
-                    (ins), "pop\t$reg", []>,
+                     : $rd),
+                    (ins), "pop\t$rd", []>,
                 Requires<[HasSRAM]>;
 
     def POPWRd : Pseudo<(outs DREGS
                          : $reg),
                         (ins), "popw\t$reg", []>,
                  Requires<[HasSRAM]>;
   }
 }
"$src = $rd" in def SWAPRd : FRd<0b1001, 0b0100010,
                                                             : $src))]>;
 
 // IO register bit set/clear operations.
 //: TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi
 // instead of in+ori+out which requires one more instr.
 def SBIAb : FIOBIT<0b10, (outs),
                    (ins imm_port5
                     : $addr, i8imm
-                    : $bit),
-                   "sbi\t$addr, $bit", [(store(or(i8(load lowioaddr8
+                    : $b),
+                   "sbi\t$addr, $b", [(store(or(i8(load lowioaddr8
                                                      : $addr)),
                                                iobitpos8
-                                               : $bit),
+                                               : $b),
                                          lowioaddr8
                                          : $addr)]>;
 
 def CBIAb : FIOBIT<0b00, (outs),
                    (ins imm_port5
                     : $addr, i8imm
-                    : $bit),
-                   "cbi\t$addr, $bit", [(store(and(i8(load lowioaddr8
+                    : $b),
+                   "cbi\t$addr, $b", [(store(and(i8(load lowioaddr8
                                                       : $addr)),
                                                iobitposn8
-                                               : $bit),
+                                               : $b),
                                          lowioaddr8
                                          : $addr)]>;
 
 // Status register bit load/store operations.
 let Defs = [SREG] in def BST : FRdB<0b01, (outs),
                                     (ins GPR8
                                      : $rd, i8imm
                                      : $b),

llvm/test/MC/AVR/inst-family-cond-branch.s

 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s \
+; RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INST %s
 
 
 foo:
   ; BREQ
   breq .-18
   breq .-12
   brbs 1, .-18
   brbs 1, baz
 
 ; CHECK: breq    .Ltmp0-18               ; encoding: [0bAAAAA001,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp0-18, kind: fixup_7_pcrel
 ; CHECK: breq    .Ltmp1-12               ; encoding: [0bAAAAA001,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp1-12, kind: fixup_7_pcrel
 ; CHECK: brbs    1, .Ltmp2-18            ; encoding: [0bAAAAA001,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp2-18, kind: fixup_7_pcrel
 ; CHECK: brbs    1, baz                  ; encoding: [0bAAAAA001,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: baz, kind: fixup_7_pcrel
 
+; INST-LABEL: <foo>:
+; INST: breq .+0
+; INST: breq .+0
+; INST: breq .+0
+; INST: breq .+0
+
   ; BRNE
   brne .+10
   brne .+2
   brbc 1, .+10
   brbc 1, bar
 
 ; CHECK: brne    .Ltmp3+10               ; encoding: [0bAAAAA001,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp3+10, kind: fixup_7_pcrel
 ; CHECK: brne    .Ltmp4+2                ; encoding: [0bAAAAA001,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp4+2, kind: fixup_7_pcrel
 ; CHECK: brbc    1, .Ltmp5+10            ; encoding: [0bAAAAA001,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp5+10, kind: fixup_7_pcrel
 ; CHECK: brbc    1, bar                  ; encoding: [0bAAAAA001,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: bar, kind: fixup_7_pcrel
 
+; INST: brne .+0
+; INST: brne .+0
+; INST: brne .+0
+; INST: brne .+0
+
 bar:
   ; BRCS
   brcs .+8
   brcs .+4
   brbs 0, .+8
   brbs 0, end
 
 ; CHECK: brcs    .Ltmp6+8                ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp6+8, kind: fixup_7_pcrel
 ; CHECK: brcs    .Ltmp7+4                ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp7+4, kind: fixup_7_pcrel
 ; CHECK: brcs    .Ltmp8+8                ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp8+8, kind: fixup_7_pcrel
 ; CHECK: brcs    end                     ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST-LABEL: <bar>:
+; INST: brlo .+0
+; INST: brlo .+0
+; INST: brlo .+0
+; INST: brlo .+0
+
   ; BRCC
   brcc .+66
   brcc .-22
   brbc 0, .+66
   brbc 0, baz
 
 ; CHECK: brcc    .Ltmp9+66               ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp9+66, kind: fixup_7_pcrel
 ; CHECK: brcc    .Ltmp10-22              ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp10-22, kind: fixup_7_pcrel
 ; CHECK: brcc    .Ltmp11+66              ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp11+66, kind: fixup_7_pcrel
 ; CHECK: brcc    baz                     ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: baz, kind: fixup_7_pcrel
 
-  ; BRSH
+; INST: brsh .+0
+; INST: brsh .+0
+; INST: brsh .+0
+; INST: brsh .+0
+
   brsh .+32
   brsh .+70
   brsh car
 
 ; CHECK: brsh    .Ltmp12+32              ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp12+32, kind: fixup_7_pcrel
 ; CHECK: brsh    .Ltmp13+70              ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp13+70, kind: fixup_7_pcrel
 ; CHECK: brsh    car                     ; encoding: [0bAAAAA000,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: car, kind: fixup_7_pcrel
 
+; INST: brsh .+0
+; INST: brsh .+0
+; INST: brsh .+0
+
 baz:
 
   ; BRLO
   brlo .+12
   brlo .+28
   brlo car
 
 ; CHECK: brlo    .Ltmp14+12              ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp14+12, kind: fixup_7_pcrel
 ; CHECK: brlo    .Ltmp15+28              ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp15+28, kind: fixup_7_pcrel
 ; CHECK: brlo    car                     ; encoding: [0bAAAAA000,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: car, kind: fixup_7_pcrel
 
+; INST-LABEL: <baz>:
+; INST: brlo .+0
+; INST: brlo .+0
+; INST: brlo .+0
+
   ; BRMI
   brmi .+66
   brmi .+58
   brmi car
 
 ; CHECK: brmi    .Ltmp16+66              ; encoding: [0bAAAAA010,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp16+66, kind: fixup_7_pcrel
 ; CHECK: brmi    .Ltmp17+58              ; encoding: [0bAAAAA010,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp17+58, kind: fixup_7_pcrel
 ; CHECK: brmi    car                     ; encoding: [0bAAAAA010,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: car, kind: fixup_7_pcrel
 
+; INST: brmi .+0
+; INST: brmi .+0
+; INST: brmi .+0
+
   ; BRPL
   brpl .-12
   brpl .+18
   brpl car
 
 ; CHECK: brpl    .Ltmp18-12              ; encoding: [0bAAAAA010,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp18-12, kind: fixup_7_pcrel
 ; CHECK: brpl    .Ltmp19+18              ; encoding: [0bAAAAA010,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp19+18, kind: fixup_7_pcrel
 ; CHECK: brpl    car                     ; encoding: [0bAAAAA010,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: car, kind: fixup_7_pcrel
 
-  ; BRGE
+; INST: brpl .+0
+; INST: brpl .+0
+; INST: brpl .+0
+
   brge .+50
   brge .+42
   brge car
 
 ; CHECK: brge    .Ltmp20+50              ; encoding: [0bAAAAA100,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp20+50, kind: fixup_7_pcrel
 ; CHECK: brge    .Ltmp21+42              ; encoding: [0bAAAAA100,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp21+42, kind: fixup_7_pcrel
 ; CHECK: brge    car                     ; encoding: [0bAAAAA100,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: car, kind: fixup_7_pcrel
 
+; INST: brge .+0
+; INST: brge .+0
+; INST: brge .+0
+
 car:
   ; BRLT
   brlt .+16
   brlt .+2
   brlt end
 
 ; CHECK: brlt    .Ltmp22+16              ; encoding: [0bAAAAA100,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp22+16, kind: fixup_7_pcrel
 ; CHECK: brlt    .Ltmp23+2               ; encoding: [0bAAAAA100,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp23+2, kind: fixup_7_pcrel
 ; CHECK: brlt    end                     ; encoding: [0bAAAAA100,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST-LABEL: <car>:
+; INST: brlt  .+0
+; INST: brlt  .+0
+; INST: brlt  .+0
+
   ; BRHS
   brhs .-66
   brhs .+14
   brhs just_another_label
 
 ; CHECK: brhs    .Ltmp24-66              ; encoding: [0bAAAAA101,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp24-66, kind: fixup_7_pcrel
 ; CHECK: brhs    .Ltmp25+14              ; encoding: [0bAAAAA101,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp25+14, kind: fixup_7_pcrel
 ; CHECK: brhs    just_another_label      ; encoding: [0bAAAAA101,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
 
+; INST: brhs  .+0
+; INST: brhs  .+0
+; INST: brhs  .+0
+
   ; BRHC
   brhc .+12
   brhc .+14
   brhc just_another_label
 
 ; CHECK: brhc    .Ltmp26+12              ; encoding: [0bAAAAA101,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp26+12, kind: fixup_7_pcrel
 ; CHECK: brhc    .Ltmp27+14              ; encoding: [0bAAAAA101,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp27+14, kind: fixup_7_pcrel
 ; CHECK: brhc    just_another_label      ; encoding: [0bAAAAA101,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
 
+; INST: brhc  .+0
+; INST: brhc  .+0
+; INST: brhc  .+0
+
   ; BRTS
   brts .+18
   brts .+22
   brts just_another_label
 
 ; CHECK: brts    .Ltmp28+18              ; encoding: [0bAAAAA110,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp28+18, kind: fixup_7_pcrel
 ; CHECK: brts    .Ltmp29+22              ; encoding: [0bAAAAA110,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp29+22, kind: fixup_7_pcrel
 ; CHECK: brts    just_another_label      ; encoding: [0bAAAAA110,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
 
+; INST: brts  .+0
+; INST: brts  .+0
+; INST: brts  .+0
+
 just_another_label:
   ; BRTC
   brtc .+52
   brtc .+50
   brtc end
 
 ; CHECK: brtc    .Ltmp30+52              ; encoding: [0bAAAAA110,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp30+52, kind: fixup_7_pcrel
 ; CHECK: brtc    .Ltmp31+50              ; encoding: [0bAAAAA110,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp31+50, kind: fixup_7_pcrel
 ; CHECK: brtc    end                     ; encoding: [0bAAAAA110,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST-LABEL: <just_another_label>:
+; INST: brtc  .+0
+; INST: brtc  .+0
+; INST: brtc  .+0
+
   ; BRVS
   brvs .+18
   brvs .+32
   brvs end
 
 ; CHECK: brvs    .Ltmp32+18              ; encoding: [0bAAAAA011,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp32+18, kind: fixup_7_pcrel
 ; CHECK: brvs    .Ltmp33+32              ; encoding: [0bAAAAA011,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp33+32, kind: fixup_7_pcrel
 ; CHECK: brvs    end                     ; encoding: [0bAAAAA011,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST: brvs  .+0
+; INST: brvs  .+0
+; INST: brvs  .+0
+
   ; BRVC
   brvc .-28
   brvc .-62
   brvc end
 
 ; CHECK: brvc    .Ltmp34-28              ; encoding: [0bAAAAA011,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp34-28, kind: fixup_7_pcrel
 ; CHECK: brvc    .Ltmp35-62              ; encoding: [0bAAAAA011,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp35-62, kind: fixup_7_pcrel
 ; CHECK: brvc    end                     ; encoding: [0bAAAAA011,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST: brvc  .+0
+; INST: brvc  .+0
+; INST: brvc  .+0
+
   ; BRIE
   brie .+20
   brie .+40
   brie end
 
 ; CHECK: brie    .Ltmp36+20              ; encoding: [0bAAAAA111,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp36+20, kind: fixup_7_pcrel
 ; CHECK: brie    .Ltmp37+40              ; encoding: [0bAAAAA111,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp37+40, kind: fixup_7_pcrel
 ; CHECK: brie    end                     ; encoding: [0bAAAAA111,0b111100AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST: brie  .+0
+; INST: brie  .+0
+; INST: brie  .+0
+
   ; BRID
   brid .+42
   brid .+62
   brid end
 
 ; CHECK: brid    .Ltmp38+42              ; encoding: [0bAAAAA111,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp38+42, kind: fixup_7_pcrel
 ; CHECK: brid    .Ltmp39+62              ; encoding: [0bAAAAA111,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp39+62, kind: fixup_7_pcrel
 ; CHECK: brid    end                     ; encoding: [0bAAAAA111,0b111101AA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_7_pcrel
 
+; INST: brid  .+0
+; INST: brid  .+0
+; INST: brid  .+0
+
 end:

llvm/test/MC/AVR/inst-mul.s

 ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s \
+; RUN:     | llvm-objdump -d --mattr=mul - | FileCheck --check-prefix=INST %s
 
 
 foo:
   mul r0,  r15
   mul r15, r0
   mul r16, r31
   mul r31, r16
 
 ; CHECK: mul r0,  r15               ; encoding: [0x0f,0x9c]
 ; CHECK: mul r15, r0                ; encoding: [0xf0,0x9c]
 ; CHECK: mul r16, r31               ; encoding: [0x0f,0x9f]
 ; CHECK: mul r31, r16               ; encoding: [0xf0,0x9f]
+
+; INST:  mul r0,  r15
+; INST:  mul r15, r0
+; INST:  mul r16, r31
+; INST:  mul r31, r16

llvm/test/MC/AVR/inst-rjmp.s

 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s \
+; RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INST %s
 
 
 foo:
 
   rjmp  .+2
   rjmp  .-2
   rjmp  foo
   rjmp  .+8

 ; CHECK: rjmp    end                     ; encoding: [A,0b1100AAAA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: end, kind: fixup_13_pcrel
 ; CHECK: rjmp    .Ltmp3+0                ; encoding: [A,0b1100AAAA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp3+0, kind: fixup_13_pcrel
 ; CHECK: rjmp    .Ltmp4-4                ; encoding: [A,0b1100AAAA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp4-4, kind: fixup_13_pcrel
 ; CHECK: rjmp    .Ltmp5-6                ; encoding: [A,0b1100AAAA]
 ; CHECK:                                 ;   fixup A - offset: 0, value: .Ltmp5-6, kind: fixup_13_pcrel
+
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0
+; INST: rjmp  .+0

llvm/test/MC/AVR/inst-sbrc.s

 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s \
+; RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INST %s
 
 
 foo:
 
   sbrc r2, 3
   sbrc r0, 7
 
 ; CHECK: sbrc r2, 3                  ; encoding: [0x23,0xfc]
 ; CHECK: sbrc r0, 7                  ; encoding: [0x07,0xfc]
 
+; INST: sbrc r2, 3
+; INST: sbrc r0, 7

llvm/test/MC/AVR/inst-sbrs.s

 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s \
+; RUN:     | llvm-objdump -d - | FileCheck --check-prefix=INST %s
 
 
 foo:
 
   sbrs r2, 3
   sbrs r0, 7
 
 ; CHECK: sbrs r2, 3                  ; encoding: [0x23,0xfe]
 ; CHECK: sbrs r0, 7                  ; encoding: [0x07,0xfe]
 
+; INST: sbrs r2, 3
+; INST: sbrs r0, 7