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Differential D134126

[sanitizer] Handle movmsk intrinsics
AcceptedPublic

Authored by vitalybuka on Sep 18 2022, 12:57 AM.

Details

Reviewers
eugenis
kda
kstoimenov
Summary

Instrumentation is just replaying the instruction for the shadow bits.

Diff Detail

Event Timeline

vitalybuka created this revision.Sep 18 2022, 12:57 AM
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vitalybuka requested review of this revision.Sep 18 2022, 12:57 AM
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Harbormaster completed remote builds in B187371: Diff 461052.Sep 18 2022, 12:57 AM
vitalybuka edited the summary of this revision. (Show Details)Sep 19 2022, 9:47 AM
vitalybuka added reviewers: eugenis, kda, kstoimenov.
vitalybuka added a comment.Sep 21 2022, 3:18 PM

ping

kda accepted this revision.Sep 21 2022, 4:05 PM
This revision is now accepted and ready to land.Sep 21 2022, 4:05 PM
RKSimon added a subscriber: RKSimon.Sep 22 2022, 1:20 AM
RKSimon added inline comments.
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
3874

What about the pmovmskb variants?

Revision Contents

PathSize
llvm/
lib/
Transforms/
Instrumentation/
21 lines
test/
Instrumentation/
MemorySanitizer/
22 lines
11 lines
11 lines

Diff 461052

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Show First 20 Lines • Show All 3,503 Lines • ▼ Show 20 Lines Shadow1 = IRB.CreateSExt(
IRB.CreateICmpNE(Shadow1, Constant::getNullValue(Shadow1->getType())), IRB.CreateICmpNE(Shadow1, Constant::getNullValue(Shadow1->getType())),
Shadow->getType()); Shadow->getType());
Shadow = IRB.CreateOr(Shadow, Shadow1); Shadow = IRB.CreateOr(Shadow, Shadow1);
setShadow(&I, Shadow); setShadow(&I, Shadow);
setOriginForNaryOp(I); setOriginForNaryOp(I);
} }
void handleMovmskIntrinsic(IntrinsicInst &I) {
IRBuilder<> IRB(&I);
// Do the same operation for the shadow as the first argument.
Value *ShadowIn =
IRB.CreateBitCast(getShadow(&I, 0), I.getArgOperand(0)->getType());
IntrinsicInst *ShadowInst = cast<IntrinsicInst>(IRB.Insert(I.clone()));
ShadowInst->setArgOperand(0, ShadowIn);
Value *Shadow = IRB.CreateBitCast(ShadowInst, getShadowTy(&I));
setShadow(&I, Shadow);
setOriginForNaryOp(I);
}
void handleVtestIntrinsic(IntrinsicInst &I) { void handleVtestIntrinsic(IntrinsicInst &I) {
IRBuilder<> IRB(&I); IRBuilder<> IRB(&I);
Value* Shadow0 = getShadow(&I, 0); Value* Shadow0 = getShadow(&I, 0);
Value* Shadow1 = getShadow(&I, 1); Value* Shadow1 = getShadow(&I, 1);
Value* Or = IRB.CreateOr(Shadow0, Shadow1); Value* Or = IRB.CreateOr(Shadow0, Shadow1);
Value* NZ = IRB.CreateICmpNE(Or, Constant::getNullValue(Or->getType())); Value* NZ = IRB.CreateICmpNE(Or, Constant::getNullValue(Or->getType()));
Value* Scalar = convertShadowToScalar(NZ, IRB); Value* Scalar = convertShadowToScalar(NZ, IRB);
Value* Shadow = IRB.CreateZExt(Scalar, getShadowTy(&I)); Value* Shadow = IRB.CreateZExt(Scalar, getShadowTy(&I));
▲ Show 20 Lines • Show All 329 Lines • ▼ Show 20 Lines void visitIntrinsicInst(IntrinsicInst &I) {
case Intrinsic::x86_avx_ptestnzc_256: case Intrinsic::x86_avx_ptestnzc_256:
case Intrinsic::x86_avx_ptestz_256: case Intrinsic::x86_avx_ptestz_256:
case Intrinsic::x86_sse41_ptestc: case Intrinsic::x86_sse41_ptestc:
case Intrinsic::x86_sse41_ptestnzc: case Intrinsic::x86_sse41_ptestnzc:
case Intrinsic::x86_sse41_ptestz: case Intrinsic::x86_sse41_ptestz:
handleVtestIntrinsic(I); handleVtestIntrinsic(I);
break; break;
case Intrinsic::x86_avx_movmsk_pd_256:
case Intrinsic::x86_avx_movmsk_ps_256:
case Intrinsic::x86_sse_movmsk_ps:
case Intrinsic::x86_sse2_movmsk_pd:
RKSimonUnsubmitted
Not Done
ReplyInline Actions

What about the pmovmskb variants?

RKSimon: What about the pmovmskb variants?
handleMovmskIntrinsic(I);
break;
case Intrinsic::fshl: case Intrinsic::fshl:
case Intrinsic::fshr: case Intrinsic::fshr:
handleFunnelShift(I); handleFunnelShift(I);
break; break;
case Intrinsic::is_constant: case Intrinsic::is_constant:
// The result of llvm.is.constant() is always defined. // The result of llvm.is.constant() is always defined.
setShadow(&I, getCleanShadow(&I)); setShadow(&I, getCleanShadow(&I));
▲ Show 20 Lines • Show All 1,813 Lines • Show Last 20 Lines

llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll

Show First 20 Lines • Show All 763 Lines • ▼ Show 20 Lines
} }
declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone
define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) #0 { define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) #0 {
; CHECK-LABEL: @test_x86_avx_movmsk_pd_256( ; CHECK-LABEL: @test_x86_avx_movmsk_pd_256(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to <4 x double>
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> [[TMP2]])
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
; CHECK: 3:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]
; CHECK-NEXT: unreachable
; CHECK: 4:
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> [[A0:%.*]])
; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 ; CHECK-NEXT: store i32 [[TMP3]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; <i32> [#uses=1] %res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; <i32> [#uses=1]
ret i32 %res ret i32 %res
} }
declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) #0 { define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) #0 {
; CHECK-LABEL: @test_x86_avx_movmsk_ps_256( ; CHECK-LABEL: @test_x86_avx_movmsk_ps_256(
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to <8 x float>
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> [[TMP2]])
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
; CHECK: 3:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]
; CHECK-NEXT: unreachable
; CHECK: 4:
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> [[A0:%.*]])
; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 ; CHECK-NEXT: store i32 [[TMP3]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; <i32> [#uses=1] %res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; <i32> [#uses=1]
ret i32 %res ret i32 %res
} }
declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
▲ Show 20 Lines • Show All 607 Lines • Show Last 20 Lines

llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll

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} }
declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) #0 { define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) #0 {
; CHECK-LABEL: @test_x86_sse_movmsk_ps( ; CHECK-LABEL: @test_x86_sse_movmsk_ps(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to <4 x float>
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[TMP2]])
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
; CHECK: 3:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]
; CHECK-NEXT: unreachable
; CHECK: 4:
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[A0:%.*]])
; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 ; CHECK-NEXT: store i32 [[TMP3]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1] %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; <i32> [#uses=1]
ret i32 %res ret i32 %res
} }
declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll

Show First 20 Lines • Show All 631 Lines • ▼ Show 20 Lines
} }
declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 { define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 {
; CHECK-LABEL: @test_x86_sse2_movmsk_pd( ; CHECK-LABEL: @test_x86_sse2_movmsk_pd(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8
; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <2 x double>
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[TMP2]])
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
; CHECK: 3:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
; CHECK-NEXT: unreachable
; CHECK: 4:
; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]])
; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 ; CHECK-NEXT: store i32 [[TMP3]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8
; CHECK-NEXT: ret i32 [[RES]] ; CHECK-NEXT: ret i32 [[RES]]
; ;
%res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1] %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]
ret i32 %res ret i32 %res
} }
declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
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