[AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

It renames a couple of fields to match their operands, as well as
introducing sub-operand names where required.

This change _only_ fixes the 'R600' half of the target, not the
'AMDGPU' half. Fixing the AMDGPU half will be a significantly more
difficult change (which I've not yet attempted.)

[arsenm]

llvm/lib/Target/AMDGPU/R600Instructions.td

652–653

Why did this need to be renamed?

[jyknight]

llvm/lib/Target/AMDGPU/R600Instructions.td

652–653

To match the "addr" in the (ins i32imm:$addr) operand.

llvm/lib/Target/AMDGPU/R600.td

 //===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
 def R600InstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
-  let noNamedPositionallyEncodedOperands = 1;
-  let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 def R600 : Target {
   let InstructionSet = R600InstrInfo;
   let AllowRegisterRenaming = 1;
 }
 
 let Namespace = "R600" in {

llvm/lib/Target/AMDGPU/R600Instructions.td

 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;
 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;
 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
 
 def FETCH_CLAUSE : R600WrapperInst <(outs),
 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
   field bits<8> Inst;
-  bits<8> num;
-  let Inst = num;
+  bits<8> addr;
+  let Inst = addr;
   let isCodeGenOnly = 1;
 }
 
 def ALU_CLAUSE : R600WrapperInst <(outs),
 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
   field bits<8> Inst;
-  bits<8> num;
-  let Inst = num;
+  bits<8> addr;
+  let Inst = addr;
   let isCodeGenOnly = 1;
 }
 
 def LITERALS : R600WrapperInst <(outs),
 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
   let isCodeGenOnly = 1;
 
   field bits<64> Inst;
def CONST_COPY : Instruction {
   let AsmString = "CONST_COPY";
   let hasSideEffects = 0;
   let isAsCheapAsAMove = 1;
   let Itinerary = NullALU;
 }
 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
 
 def TEX_VTX_CONSTBUF :
-  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "VTX_READ_eg $dst, $ptr",
-      [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$buffer_id)))]>,
+  InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "VTX_READ_eg $dst_gpr, $src",
+      [(set v4i32:$dst_gpr, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$src, (i32 imm:$buffer_id)))]>,
   VTX_WORD1_GPR, VTX_WORD0_eg {
 
   let VC_INST = 0;
   let FETCH_TYPE = 2;
   let FETCH_WHOLE_QUAD = 0;
   let SRC_REL = 0;
   let SRC_SEL_X = 0;
   let DST_REL = 0;

 
 // VTX_WORD3 (Padding)
 //
 // Inst{127-96} = 0;
   let VTXInst = 1;
 }
 
 def TEX_VTX_TEXBUF:
-  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
+  InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst_gpr, $src">,
 VTX_WORD1_GPR, VTX_WORD0_eg {
 
 let VC_INST = 0;
 let FETCH_TYPE = 2;
 let FETCH_WHOLE_QUAD = 0;
 let SRC_REL = 0;
 let SRC_SEL_X = 0;
 let DST_REL = 0;