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Differential D133091

[msan] Fix debug info with getNextNode
ClosedPublic

Authored by vitalybuka on Aug 31 2022, 10:24 PM.

Details

Reviewers
kda
kstoimenov
eugenis
Commits
rGad3a77df2d3c: [msan] Fix debug info with getNextNode
Summary

When we want to add instrumentation after
an instruction, instrumentation still should
keep debug info of the instruction.

Diff Detail

Event Timeline

vitalybuka created this revision.Aug 31 2022, 10:24 PM
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vitalybuka requested review of this revision.Aug 31 2022, 10:24 PM
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vitalybuka added reviewers: kda, kstoimenov, eugenis.Aug 31 2022, 10:26 PM
Harbormaster completed remote builds in B184514: Diff 457176.Aug 31 2022, 11:06 PM
vitalybuka updated this revision to Diff 457183.Aug 31 2022, 11:18 PM

remove SetCurrentDebugLocation

Harbormaster completed remote builds in B184521: Diff 457183.Sep 1 2022, 12:04 AM
kda accepted this revision.Sep 1 2022, 12:39 PM
This revision is now accepted and ready to land.Sep 1 2022, 12:39 PM
kstoimenov accepted this revision.Sep 1 2022, 12:54 PM
This revision was landed with ongoing or failed builds.Sep 1 2022, 8:14 PM
Closed by commit rGad3a77df2d3c: [msan] Fix debug info with getNextNode (authored by vitalybuka). · Explain Why
This revision was automatically updated to reflect the committed changes.
vitalybuka added a commit: rGad3a77df2d3c: [msan] Fix debug info with getNextNode.

Revision Contents

PathSize
llvm/
lib/
Transforms/
Instrumentation/
28 lines
test/
Instrumentation/
MemorySanitizer/
98 lines

Diff 457490

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Show First 20 Lines • Show All 1,046 Lines • ▼ Show 20 Lines
static unsigned TypeSizeToSizeIndex(unsigned TypeSize) { static unsigned TypeSizeToSizeIndex(unsigned TypeSize) {
if (TypeSize <= 8) if (TypeSize <= 8)
return 0; return 0;
return Log2_32_Ceil((TypeSize + 7) / 8); return Log2_32_Ceil((TypeSize + 7) / 8);
} }
namespace { namespace {
/// Helper class to attach debug information of the given instruction onto new
/// instructions inserted after.
class NextNodeIRBuilder : public IRBuilder<> {
public:
explicit NextNodeIRBuilder(Instruction *IP) : IRBuilder<>(IP->getNextNode()) {
SetCurrentDebugLocation(IP->getDebugLoc());
}
};
/// This class does all the work for a given function. Store and Load /// This class does all the work for a given function. Store and Load
/// instructions store and load corresponding shadow and origin /// instructions store and load corresponding shadow and origin
/// values. Most instructions propagate shadow from arguments to their /// values. Most instructions propagate shadow from arguments to their
/// return values. Certain instructions (most importantly, BranchInst) /// return values. Certain instructions (most importantly, BranchInst)
/// test their argument shadow and print reports (with a runtime call) if it's /// test their argument shadow and print reports (with a runtime call) if it's
/// non-zero. /// non-zero.
struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> { struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
Function &F; Function &F;
▲ Show 20 Lines • Show All 908 Lines • ▼ Show 20 Lines#endif
/// Instrument LoadInst /// Instrument LoadInst
/// ///
/// Loads the corresponding shadow and (optionally) origin. /// Loads the corresponding shadow and (optionally) origin.
/// Optionally, checks that the load address is fully defined. /// Optionally, checks that the load address is fully defined.
void visitLoadInst(LoadInst &I) { void visitLoadInst(LoadInst &I) {
assert(I.getType()->isSized() && "Load type must have size"); assert(I.getType()->isSized() && "Load type must have size");
assert(!I.getMetadata(LLVMContext::MD_nosanitize)); assert(!I.getMetadata(LLVMContext::MD_nosanitize));
IRBuilder<> IRB(I.getNextNode()); NextNodeIRBuilder IRB(&I);
Type *ShadowTy = getShadowTy(&I); Type *ShadowTy = getShadowTy(&I);
Value *Addr = I.getPointerOperand(); Value *Addr = I.getPointerOperand();
Value *ShadowPtr = nullptr, *OriginPtr = nullptr; Value *ShadowPtr = nullptr, *OriginPtr = nullptr;
const Align Alignment = I.getAlign(); const Align Alignment = I.getAlign();
if (PropagateShadow) { if (PropagateShadow) {
std::tie(ShadowPtr, OriginPtr) = std::tie(ShadowPtr, OriginPtr) =
getShadowOriginPtr(Addr, IRB, ShadowTy, Alignment, /*isStore*/ false); getShadowOriginPtr(Addr, IRB, ShadowTy, Alignment, /*isStore*/ false);
setShadow(&I, setShadow(&I,
▲ Show 20 Lines • Show All 1,655 Lines • ▼ Show 20 Lines void visitLibAtomicLoad(CallBase &CB) {
Value *DstPtr = CB.getArgOperand(2); Value *DstPtr = CB.getArgOperand(2);
Value *Ordering = CB.getArgOperand(3); Value *Ordering = CB.getArgOperand(3);
// Convert the call to have at least Acquire ordering to make sure // Convert the call to have at least Acquire ordering to make sure
// the shadow operations aren't reordered before it. // the shadow operations aren't reordered before it.
Value *NewOrdering = Value *NewOrdering =
IRB.CreateExtractElement(makeAddAcquireOrderingTable(IRB), Ordering); IRB.CreateExtractElement(makeAddAcquireOrderingTable(IRB), Ordering);
CB.setArgOperand(3, NewOrdering); CB.setArgOperand(3, NewOrdering);
IRBuilder<> NextIRB(CB.getNextNode()); NextNodeIRBuilder NextIRB(&CB);
NextIRB.SetCurrentDebugLocation(CB.getDebugLoc());
Value *SrcShadowPtr, *SrcOriginPtr; Value *SrcShadowPtr, *SrcOriginPtr;
std::tie(SrcShadowPtr, SrcOriginPtr) = std::tie(SrcShadowPtr, SrcOriginPtr) =
getShadowOriginPtr(SrcPtr, NextIRB, NextIRB.getInt8Ty(), Align(1), getShadowOriginPtr(SrcPtr, NextIRB, NextIRB.getInt8Ty(), Align(1),
/*isStore*/ false); /*isStore*/ false);
Value *DstShadowPtr = Value *DstShadowPtr =
getShadowOriginPtr(DstPtr, NextIRB, NextIRB.getInt8Ty(), Align(1), getShadowOriginPtr(DstPtr, NextIRB, NextIRB.getInt8Ty(), Align(1),
/*isStore*/ true) /*isStore*/ true)
.first; .first;
▲ Show 20 Lines • Show All 338 Lines • ▼ Show 20 Lines if (PoisonStack) {
IRB.CreateCall(MS.MsanUnpoisonAllocaFn, IRB.CreateCall(MS.MsanUnpoisonAllocaFn,
{IRB.CreatePointerCast(&I, IRB.getInt8PtrTy()), Len}); {IRB.CreatePointerCast(&I, IRB.getInt8PtrTy()), Len});
} }
} }
void instrumentAlloca(AllocaInst &I, Instruction *InsPoint = nullptr) { void instrumentAlloca(AllocaInst &I, Instruction *InsPoint = nullptr) {
if (!InsPoint) if (!InsPoint)
InsPoint = &I; InsPoint = &I;
IRBuilder<> IRB(InsPoint->getNextNode()); NextNodeIRBuilder IRB(InsPoint);
IRB.SetCurrentDebugLocation(InsPoint->getDebugLoc());
const DataLayout &DL = F.getParent()->getDataLayout(); const DataLayout &DL = F.getParent()->getDataLayout();
uint64_t TypeSize = DL.getTypeAllocSize(I.getAllocatedType()); uint64_t TypeSize = DL.getTypeAllocSize(I.getAllocatedType());
Value *Len = ConstantInt::get(MS.IntptrTy, TypeSize); Value *Len = ConstantInt::get(MS.IntptrTy, TypeSize);
if (I.isArrayAllocation()) if (I.isArrayAllocation())
Len = IRB.CreateMul(Len, Len = IRB.CreateMul(Len,
IRB.CreateZExtOrTrunc(I.getArraySize(), MS.IntptrTy)); IRB.CreateZExtOrTrunc(I.getArraySize(), MS.IntptrTy));
if (MS.CompileKernel) if (MS.CompileKernel)
▲ Show 20 Lines • Show All 460 Lines • ▼ Show 20 Lines if (!VAStartInstrumentationList.empty()) {
Align(8), CopySize); Align(8), CopySize);
} }
} }
// Instrument va_start. // Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents. // Copy va_list shadow from the backup copy of the TLS contents.
for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) { for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) {
CallInst *OrigInst = VAStartInstrumentationList[i]; CallInst *OrigInst = VAStartInstrumentationList[i];
IRBuilder<> IRB(OrigInst->getNextNode()); NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0); Value *VAListTag = OrigInst->getArgOperand(0);
Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C); Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C);
Value *RegSaveAreaPtrPtr = IRB.CreateIntToPtr( Value *RegSaveAreaPtrPtr = IRB.CreateIntToPtr(
IRB.CreateAdd(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy), IRB.CreateAdd(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy),
ConstantInt::get(MS.IntptrTy, 16)), ConstantInt::get(MS.IntptrTy, 16)),
PointerType::get(RegSaveAreaPtrTy, 0)); PointerType::get(RegSaveAreaPtrTy, 0));
Value *RegSaveAreaPtr = Value *RegSaveAreaPtr =
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines if (!VAStartInstrumentationList.empty()) {
VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize); VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize);
IRB.CreateMemCpy(VAArgTLSCopy, Align(8), MS.VAArgTLS, Align(8), CopySize); IRB.CreateMemCpy(VAArgTLSCopy, Align(8), MS.VAArgTLS, Align(8), CopySize);
} }
// Instrument va_start. // Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents. // Copy va_list shadow from the backup copy of the TLS contents.
for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) { for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) {
CallInst *OrigInst = VAStartInstrumentationList[i]; CallInst *OrigInst = VAStartInstrumentationList[i];
IRBuilder<> IRB(OrigInst->getNextNode()); NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0); Value *VAListTag = OrigInst->getArgOperand(0);
Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C); Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C);
Value *RegSaveAreaPtrPtr = Value *RegSaveAreaPtrPtr =
IRB.CreateIntToPtr(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy), IRB.CreateIntToPtr(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy),
PointerType::get(RegSaveAreaPtrTy, 0)); PointerType::get(RegSaveAreaPtrTy, 0));
Value *RegSaveAreaPtr = Value *RegSaveAreaPtr =
IRB.CreateLoad(RegSaveAreaPtrTy, RegSaveAreaPtrPtr); IRB.CreateLoad(RegSaveAreaPtrTy, RegSaveAreaPtrPtr);
Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr; Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr;
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines void finalizeInstrumentation() override {
Value *GrArgSize = ConstantInt::get(MS.IntptrTy, kAArch64GrArgSize); Value *GrArgSize = ConstantInt::get(MS.IntptrTy, kAArch64GrArgSize);
Value *VrArgSize = ConstantInt::get(MS.IntptrTy, kAArch64VrArgSize); Value *VrArgSize = ConstantInt::get(MS.IntptrTy, kAArch64VrArgSize);
// Instrument va_start, copy va_list shadow from the backup copy of // Instrument va_start, copy va_list shadow from the backup copy of
// the TLS contents. // the TLS contents.
for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) { for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) {
CallInst *OrigInst = VAStartInstrumentationList[i]; CallInst *OrigInst = VAStartInstrumentationList[i];
IRBuilder<> IRB(OrigInst->getNextNode()); NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0); Value *VAListTag = OrigInst->getArgOperand(0);
// The variadic ABI for AArch64 creates two areas to save the incoming // The variadic ABI for AArch64 creates two areas to save the incoming
// argument registers (one for 64-bit general register xn-x7 and another // argument registers (one for 64-bit general register xn-x7 and another
// for 128-bit FP/SIMD vn-v7). // for 128-bit FP/SIMD vn-v7).
// We need then to propagate the shadow arguments on both regions // We need then to propagate the shadow arguments on both regions
// 'va::__gr_top + va::__gr_offs' and 'va::__vr_top + va::__vr_offs'. // 'va::__gr_top + va::__gr_offs' and 'va::__vr_top + va::__vr_offs'.
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines if (!VAStartInstrumentationList.empty()) {
VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize); VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize);
IRB.CreateMemCpy(VAArgTLSCopy, Align(8), MS.VAArgTLS, Align(8), CopySize); IRB.CreateMemCpy(VAArgTLSCopy, Align(8), MS.VAArgTLS, Align(8), CopySize);
} }
// Instrument va_start. // Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents. // Copy va_list shadow from the backup copy of the TLS contents.
for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) { for (size_t i = 0, n = VAStartInstrumentationList.size(); i < n; i++) {
CallInst *OrigInst = VAStartInstrumentationList[i]; CallInst *OrigInst = VAStartInstrumentationList[i];
IRBuilder<> IRB(OrigInst->getNextNode()); NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0); Value *VAListTag = OrigInst->getArgOperand(0);
Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C); Type *RegSaveAreaPtrTy = Type::getInt64PtrTy(*MS.C);
Value *RegSaveAreaPtrPtr = Value *RegSaveAreaPtrPtr =
IRB.CreateIntToPtr(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy), IRB.CreateIntToPtr(IRB.CreatePtrToInt(VAListTag, MS.IntptrTy),
PointerType::get(RegSaveAreaPtrTy, 0)); PointerType::get(RegSaveAreaPtrTy, 0));
Value *RegSaveAreaPtr = Value *RegSaveAreaPtr =
IRB.CreateLoad(RegSaveAreaPtrTy, RegSaveAreaPtrPtr); IRB.CreateLoad(RegSaveAreaPtrTy, RegSaveAreaPtrPtr);
Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr; Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr;
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines if (!VAStartInstrumentationList.empty()) {
} }
} }
// Instrument va_start. // Instrument va_start.
// Copy va_list shadow from the backup copy of the TLS contents. // Copy va_list shadow from the backup copy of the TLS contents.
for (size_t VaStartNo = 0, VaStartNum = VAStartInstrumentationList.size(); for (size_t VaStartNo = 0, VaStartNum = VAStartInstrumentationList.size();
VaStartNo < VaStartNum; VaStartNo++) { VaStartNo < VaStartNum; VaStartNo++) {
CallInst *OrigInst = VAStartInstrumentationList[VaStartNo]; CallInst *OrigInst = VAStartInstrumentationList[VaStartNo];
IRBuilder<> IRB(OrigInst->getNextNode()); NextNodeIRBuilder IRB(OrigInst);
Value *VAListTag = OrigInst->getArgOperand(0); Value *VAListTag = OrigInst->getArgOperand(0);
copyRegSaveArea(IRB, VAListTag); copyRegSaveArea(IRB, VAListTag);
copyOverflowArea(IRB, VAListTag); copyOverflowArea(IRB, VAListTag);
} }
} }
}; };
/// A no-op implementation of VarArgHelper. /// A no-op implementation of VarArgHelper.
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/Instrumentation/MemorySanitizer/msan_debug_info.ll

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define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory { define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory {
; CHECK-LABEL: @LoadAndCmp( ; CHECK-LABEL: @LoadAndCmp(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-DAG: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] ; CHECK-DAG: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]]
; CHECK-DAG: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] ; CHECK-DAG: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]]
; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] ; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]]
; CHECK-DAG: [[TMP2:%.*]] = load i32, i32* [[A:%.*]], align 4, !dbg [[DBG1]] ; CHECK-DAG: [[TMP2:%.*]] = load i32, i32* [[A:%.*]], align 4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP3:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG7:![0-9]+]] ; CHECK-DAG: [[TMP3:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG1]]
; CHECK-DAG: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG7]] ; CHECK-DAG: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG1]]
; CHECK-DAG: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG7]] ; CHECK-DAG: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG1]]
; CHECK-DAG: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG7]] ; CHECK-DAG: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG1]]
; CHECK-DAG: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32*, !dbg [[DBG7]] ; CHECK-DAG: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32*, !dbg [[DBG1]]
; CHECK-DAG: [[_MSLD:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG7]] ; CHECK-DAG: [[_MSLD:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG7]] ; CHECK-DAG: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP9:%.*]] = xor i32 [[TMP2]], 0, !dbg [[DBG7]] ; CHECK-DAG: [[TMP9:%.*]] = xor i32 [[TMP2]], 0, !dbg [[DBG7:![0-9]+]]
; CHECK-DAG: [[TMP10:%.*]] = or i32 [[_MSLD]], 0, !dbg [[DBG7]] ; CHECK-DAG: [[TMP10:%.*]] = or i32 [[_MSLD]], 0, !dbg [[DBG7]]
; CHECK-DAG: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0, !dbg [[DBG7]] ; CHECK-DAG: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0, !dbg [[DBG7]]
; CHECK-DAG: [[TMP12:%.*]] = xor i32 [[TMP10]], -1, !dbg [[DBG7]] ; CHECK-DAG: [[TMP12:%.*]] = xor i32 [[TMP10]], -1, !dbg [[DBG7]]
; CHECK-DAG: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP9]], !dbg [[DBG7]] ; CHECK-DAG: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP9]], !dbg [[DBG7]]
; CHECK-DAG: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0, !dbg [[DBG7]] ; CHECK-DAG: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0, !dbg [[DBG7]]
; CHECK-DAG: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP11]], [[TMP14]], !dbg [[DBG7]] ; CHECK-DAG: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP11]], [[TMP14]], !dbg [[DBG7]]
; CHECK-DAG: [[TOBOOL:%.*]] = icmp eq i32 [[TMP2]], 0, !dbg [[DBG7]] ; CHECK-DAG: [[TOBOOL:%.*]] = icmp eq i32 [[TMP2]], 0, !dbg [[DBG7]]
; CHECK-DAG: [[TMP15:%.*]] = zext i1 [[_MSPROP_ICMP]] to i8, !dbg [[DBG8:![0-9]+]] ; CHECK-DAG: [[TMP15:%.*]] = zext i1 [[_MSPROP_ICMP]] to i8, !dbg [[DBG8:![0-9]+]]
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @SExt( ; CHECK-LABEL: @SExt(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-DAG: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]] ; CHECK-DAG: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]]
; CHECK-DAG: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] ; CHECK-DAG: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP2:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] ; CHECK-DAG: [[TMP2:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]]
; CHECK-DAG: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] ; CHECK-DAG: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]]
; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] ; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]]
; CHECK-DAG: [[TMP4:%.*]] = load i16, i16* [[B:%.*]], align 2, !dbg [[DBG1]] ; CHECK-DAG: [[TMP4:%.*]] = load i16, i16* [[B:%.*]], align 2, !dbg [[DBG1]]
; CHECK-DAG: [[TMP5:%.*]] = ptrtoint i16* [[B]] to i64, !dbg [[DBG7]] ; CHECK-DAG: [[TMP5:%.*]] = ptrtoint i16* [[B]] to i64, !dbg [[DBG1]]
; CHECK-DAG: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080, !dbg [[DBG7]] ; CHECK-DAG: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080, !dbg [[DBG1]]
; CHECK-DAG: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i16*, !dbg [[DBG7]] ; CHECK-DAG: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i16*, !dbg [[DBG1]]
; CHECK-DAG: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416, !dbg [[DBG7]] ; CHECK-DAG: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416, !dbg [[DBG1]]
; CHECK-DAG: [[TMP9:%.*]] = and i64 [[TMP8]], -4, !dbg [[DBG7]] ; CHECK-DAG: [[TMP9:%.*]] = and i64 [[TMP8]], -4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i32*, !dbg [[DBG7]] ; CHECK-DAG: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i32*, !dbg [[DBG1]]
; CHECK-DAG: [[_MSLD:%.*]] = load i16, i16* [[TMP7]], align 2, !dbg [[DBG7]] ; CHECK-DAG: [[_MSLD:%.*]] = load i16, i16* [[TMP7]], align 2, !dbg [[DBG1]]
; CHECK-DAG: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG7]] ; CHECK-DAG: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG1]]
; CHECK-DAG: [[_MSPROP:%.*]] = sext i16 [[_MSLD]] to i32, !dbg [[DBG7]] ; CHECK-DAG: [[_MSPROP:%.*]] = sext i16 [[_MSLD]] to i32, !dbg [[DBG7]]
; CHECK-DAG: [[TMP12:%.*]] = sext i16 [[TMP4]] to i32, !dbg [[DBG7]] ; CHECK-DAG: [[TMP12:%.*]] = sext i16 [[TMP4]] to i32, !dbg [[DBG7]]
; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[TMP3]]), !dbg [[DBG8]] ; CHECK-DAG: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[TMP3]]), !dbg [[DBG8]]
; CHECK-DAG: [[TMP13:%.*]] = ptrtoint i32* [[A:%.*]] to i64, !dbg [[DBG8]] ; CHECK-DAG: [[TMP13:%.*]] = ptrtoint i32* [[A:%.*]] to i64, !dbg [[DBG8]]
; CHECK-DAG: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]] ; CHECK-DAG: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]]
; CHECK-DAG: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i32*, !dbg [[DBG8]] ; CHECK-DAG: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i32*, !dbg [[DBG8]]
; CHECK-DAG: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG8]] ; CHECK-DAG: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG8]]
; CHECK-DAG: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i32*, !dbg [[DBG8]] ; CHECK-DAG: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i32*, !dbg [[DBG8]]
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; CHECK-DAG: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i8*, !dbg [[DBG1]] ; CHECK-DAG: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i8*, !dbg [[DBG1]]
; CHECK-DAG: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416, !dbg [[DBG1]] ; CHECK-DAG: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416, !dbg [[DBG1]]
; CHECK-DAG: [[TMP5:%.*]] = and i64 [[TMP4]], -4, !dbg [[DBG1]] ; CHECK-DAG: [[TMP5:%.*]] = and i64 [[TMP4]], -4, !dbg [[DBG1]]
; CHECK-DAG: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32*, !dbg [[DBG1]] ; CHECK-DAG: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32*, !dbg [[DBG1]]
; CHECK-DAG: call void @llvm.memset.p0i8.i64(i8* align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] ; CHECK-DAG: call void @llvm.memset.p0i8.i64(i8* align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG1]]
; CHECK-DAG: [[TMP7:%.*]] = bitcast i32* [[Y]] to i8*, !dbg [[DBG1]] ; CHECK-DAG: [[TMP7:%.*]] = bitcast i32* [[Y]] to i8*, !dbg [[DBG1]]
; CHECK-DAG: call void @__msan_set_alloca_origin_with_descr(i8* [[TMP7]], i64 4, i8* bitcast (i32* @[[GLOB0:[0-9]+]] to i8*), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @[[GLOB1:[0-9]+]], i32 0, i32 0)), !dbg [[DBG1]] ; CHECK-DAG: call void @__msan_set_alloca_origin_with_descr(i8* [[TMP7]], i64 4, i8* bitcast (i32* @[[GLOB0:[0-9]+]] to i8*), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @[[GLOB1:[0-9]+]], i32 0, i32 0)), !dbg [[DBG1]]
; CHECK-DAG: [[TMP8:%.*]] = load volatile i32, i32* [[Y]], align 64, !dbg [[DBG7]] ; CHECK-DAG: [[TMP8:%.*]] = load volatile i32, i32* [[Y]], align 64, !dbg [[DBG7]]
; CHECK-DAG: [[TMP9:%.*]] = ptrtoint i32* [[Y]] to i64 ; CHECK-DAG: [[TMP9:%.*]] = ptrtoint i32* [[Y]] to i64, !dbg [[DBG7]]
; CHECK-DAG: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080 ; CHECK-DAG: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080, !dbg [[DBG7]]
; CHECK-DAG: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32* ; CHECK-DAG: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32*, !dbg [[DBG7]]
; CHECK-DAG: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416 ; CHECK-DAG: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416, !dbg [[DBG7]]
; CHECK-DAG: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i32* ; CHECK-DAG: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i32*, !dbg [[DBG7]]
; CHECK-DAG: [[_MSLD:%.*]] = load i32, i32* [[TMP11]], align 64 ; CHECK-DAG: [[_MSLD:%.*]] = load i32, i32* [[TMP11]], align 64, !dbg [[DBG7]]
; CHECK-DAG: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 64 ; CHECK-DAG: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 64, !dbg [[DBG7]]
; CHECK-DAG: store i32 [[_MSLD]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 ; CHECK-DAG: store i32 [[_MSLD]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8
; CHECK-DAG: store i32 [[TMP14]], i32* @__msan_retval_origin_tls, align 4 ; CHECK-DAG: store i32 [[TMP14]], i32* @__msan_retval_origin_tls, align 4
; CHECK-DAG: ret i32 [[TMP8]] ; CHECK-DAG: ret i32 [[TMP8]]
; ;
%y = alloca i32, align 64, !dbg !10 %y = alloca i32, align 64, !dbg !10
%1 = load volatile i32, i32* %y, align 64, !dbg !11 %1 = load volatile i32, i32* %y, align 64, !dbg !11
ret i32 %1 ret i32 %1
} }
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; CHECK-DAG: [[ARRAYDECAY1:%.*]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY]] to i8*, !dbg [[DBG10:![0-9]+]] ; CHECK-DAG: [[ARRAYDECAY1:%.*]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY]] to i8*, !dbg [[DBG10:![0-9]+]]
; CHECK-DAG: [[TMP26:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11:![0-9]+]] ; CHECK-DAG: [[TMP26:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11:![0-9]+]]
; CHECK-DAG: [[TMP27:%.*]] = xor i64 [[TMP26]], 87960930222080, !dbg [[DBG11]] ; CHECK-DAG: [[TMP27:%.*]] = xor i64 [[TMP26]], 87960930222080, !dbg [[DBG11]]
; CHECK-DAG: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to i8*, !dbg [[DBG11]] ; CHECK-DAG: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to i8*, !dbg [[DBG11]]
; CHECK-DAG: [[TMP29:%.*]] = add i64 [[TMP27]], 17592186044416, !dbg [[DBG11]] ; CHECK-DAG: [[TMP29:%.*]] = add i64 [[TMP27]], 17592186044416, !dbg [[DBG11]]
; CHECK-DAG: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to i32*, !dbg [[DBG11]] ; CHECK-DAG: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to i32*, !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP28]], i8 0, i64 24, i1 false), !dbg [[DBG11]] ; CHECK-DAG: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP28]], i8 0, i64 24, i1 false), !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.va_start(i8* [[ARRAYDECAY1]]), !dbg [[DBG11]] ; CHECK-DAG: call void @llvm.va_start(i8* [[ARRAYDECAY1]]), !dbg [[DBG11]]
; CHECK-DAG: [[TMP31:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64 ; CHECK-DAG: [[TMP31:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11]]
; CHECK-DAG: [[TMP32:%.*]] = add i64 [[TMP31]], 16 ; CHECK-DAG: [[TMP32:%.*]] = add i64 [[TMP31]], 16, !dbg [[DBG11]]
; CHECK-DAG: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to i64** ; CHECK-DAG: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to i64**, !dbg [[DBG11]]
; CHECK-DAG: [[TMP34:%.*]] = load i64*, i64** [[TMP33]], align 8 ; CHECK-DAG: [[TMP34:%.*]] = load i64*, i64** [[TMP33]], align 8, !dbg [[DBG11]]
; CHECK-DAG: [[TMP35:%.*]] = ptrtoint i64* [[TMP34]] to i64 ; CHECK-DAG: [[TMP35:%.*]] = ptrtoint i64* [[TMP34]] to i64, !dbg [[DBG11]]
; CHECK-DAG: [[TMP36:%.*]] = xor i64 [[TMP35]], 87960930222080 ; CHECK-DAG: [[TMP36:%.*]] = xor i64 [[TMP35]], 87960930222080, !dbg [[DBG11]]
; CHECK-DAG: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to i8* ; CHECK-DAG: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to i8*, !dbg [[DBG11]]
; CHECK-DAG: [[TMP38:%.*]] = add i64 [[TMP36]], 17592186044416 ; CHECK-DAG: [[TMP38:%.*]] = add i64 [[TMP36]], 17592186044416, !dbg [[DBG11]]
; CHECK-DAG: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to i32* ; CHECK-DAG: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to i32*, !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP37]], i8* align 16 [[TMP2]], i64 176, i1 false) ; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP37]], i8* align 16 [[TMP2]], i64 176, i1 false), !dbg [[DBG11]]
; CHECK-DAG: [[TMP40:%.*]] = bitcast i32* [[TMP39]] to i8* ; CHECK-DAG: [[TMP40:%.*]] = bitcast i32* [[TMP39]] to i8*, !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP40]], i8* align 16 [[TMP3]], i64 176, i1 false) ; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP40]], i8* align 16 [[TMP3]], i64 176, i1 false), !dbg [[DBG11]]
; CHECK-DAG: [[TMP41:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64 ; CHECK-DAG: [[TMP41:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11]]
; CHECK-DAG: [[TMP42:%.*]] = add i64 [[TMP41]], 8 ; CHECK-DAG: [[TMP42:%.*]] = add i64 [[TMP41]], 8, !dbg [[DBG11]]
; CHECK-DAG: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to i64** ; CHECK-DAG: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to i64**, !dbg [[DBG11]]
; CHECK-DAG: [[TMP44:%.*]] = load i64*, i64** [[TMP43]], align 8 ; CHECK-DAG: [[TMP44:%.*]] = load i64*, i64** [[TMP43]], align 8, !dbg [[DBG11]]
; CHECK-DAG: [[TMP45:%.*]] = ptrtoint i64* [[TMP44]] to i64 ; CHECK-DAG: [[TMP45:%.*]] = ptrtoint i64* [[TMP44]] to i64, !dbg [[DBG11]]
; CHECK-DAG: [[TMP46:%.*]] = xor i64 [[TMP45]], 87960930222080 ; CHECK-DAG: [[TMP46:%.*]] = xor i64 [[TMP45]], 87960930222080, !dbg [[DBG11]]
; CHECK-DAG: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to i8* ; CHECK-DAG: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to i8*, !dbg [[DBG11]]
; CHECK-DAG: [[TMP48:%.*]] = add i64 [[TMP46]], 17592186044416 ; CHECK-DAG: [[TMP48:%.*]] = add i64 [[TMP46]], 17592186044416, !dbg [[DBG11]]
; CHECK-DAG: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to i32* ; CHECK-DAG: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to i32*, !dbg [[DBG11]]
; CHECK-DAG: [[TMP50:%.*]] = getelementptr i8, i8* [[TMP2]], i32 176 ; CHECK-DAG: [[TMP50:%.*]] = getelementptr i8, i8* [[TMP2]], i32 176, !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP47]], i8* align 16 [[TMP50]], i64 [[TMP0]], i1 false) ; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP47]], i8* align 16 [[TMP50]], i64 [[TMP0]], i1 false), !dbg [[DBG11]]
; CHECK-DAG: [[TMP51:%.*]] = getelementptr i8, i8* [[TMP3]], i32 176 ; CHECK-DAG: [[TMP51:%.*]] = getelementptr i8, i8* [[TMP3]], i32 176, !dbg [[DBG11]]
; CHECK-DAG: [[TMP52:%.*]] = bitcast i32* [[TMP49]] to i8* ; CHECK-DAG: [[TMP52:%.*]] = bitcast i32* [[TMP49]] to i8*, !dbg [[DBG11]]
; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP52]], i8* align 16 [[TMP51]], i64 [[TMP0]], i1 false) ; CHECK-DAG: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP52]], i8* align 16 [[TMP51]], i64 [[TMP0]], i1 false), !dbg [[DBG11]]
; CHECK-DAG: ret void ; CHECK-DAG: ret void
; ;
entry: entry:
%x.addr = alloca i32, align 4, !dbg !10 %x.addr = alloca i32, align 4, !dbg !10
%va = alloca [1 x %struct.__va_list_tag], align 16, !dbg !11 %va = alloca [1 x %struct.__va_list_tag], align 16, !dbg !11
store i32 %x, i32* %x.addr, align 4, !dbg !12 store i32 %x, i32* %x.addr, align 4, !dbg !12
%arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i32 0, i32 0, !dbg !13 %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i32 0, i32 0, !dbg !13
%arraydecay1 = bitcast %struct.__va_list_tag* %arraydecay to i8*, !dbg !14 %arraydecay1 = bitcast %struct.__va_list_tag* %arraydecay to i8*, !dbg !14
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