[AMDGPU][GFX11] Fix dst register class for V_CVT_U32_U16

[Joe_Nash]

Summary

This instruction was referring to the wrong VOPProfile, likely due to a
typo, leading to an incorrect destination register type.

The MC layer will care about this change, but is NFC while 16-bit values
actually use 32 bit registers.

[Joe_Nash]

This instruction may not even be being used. Did we forget to implement an ISel pattern?

[foad]

In D132878#3756416, @Joe_Nash wrote:

This instruction may not even be being used. Did we forget to implement an ISel pattern?

I'm not sure "forget" is the right word. Without True16 this, instruction is of marginal utility, it's just a slightly shorter encoding of an AND with 0xFFFF. Even with True16 it's not necessary, since you could always use either an AND or a LSHR by 16, but I suppose having a single instruction for both cases is nice for readability.

[Joe_Nash]

In D132878#3757923, @foad wrote:

In D132878#3756416, @Joe_Nash wrote:

This instruction may not even be being used. Did we forget to implement an ISel pattern?

I'm not sure "forget" is the right word. Without True16 this, instruction is of marginal utility, it's just a slightly shorter encoding of an AND with 0xFFFF. Even with True16 it's not necessary, since you could always use either an AND or a LSHR by 16, but I suppose having a single instruction for both cases is nice for readability.

Ok, thanks for that explanation. I was wondering how this instruction would be used. I will commit this to fix the obvious mistake.

llvm/lib/Target/AMDGPU/VOP1Instructions.td

 let SubtargetPredicate = isGFX11Plus in {
   // Restrict src0 to be VGPR
   def V_PERMLANE64_B32 : VOP1_Pseudo<"v_permlane64_b32", VOP_MOVRELS,
                                       getVOP1Pat64<int_amdgcn_permlane64,
                                                    VOP_MOVRELS>.ret,
                                       /*VOP1Only=*/ 1>;
   defm V_NOT_B16        : VOP1Inst<"v_not_b16", VOP_I16_I16>;
   defm V_CVT_I32_I16    : VOP1Inst<"v_cvt_i32_i16", VOP_I32_I16>;
-  defm V_CVT_U32_U16    : VOP1Inst<"v_cvt_u32_u16", VOP_I16_I16>;
+  defm V_CVT_U32_U16    : VOP1Inst<"v_cvt_u32_u16", VOP_I32_I16>;
 } // End SubtargetPredicate = isGFX11Plus
 
 //===----------------------------------------------------------------------===//
 // Target-specific instruction encodings.
 //===----------------------------------------------------------------------===//
 
 class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP16 = 0> :
     VOP_DPP<ps.OpName, p, isDPP16> {