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Differential D132730

[AARCH64][COST] Improve cost of reverse shuffles for AArch64
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Authored by Miss_Grape on Aug 26 2022, 3:58 AM.

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greened
ABataev
dmgreen
Commits
rG723245bfac1a: [AARCH64][COST] Improve cost of reverse shuffles for AArch64

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Event Timeline

Miss_Grape created this revision.Aug 26 2022, 3:58 AM
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Miss_Grape requested review of this revision.Aug 26 2022, 3:58 AM
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Miss_Grape added a reviewer: ABataev.Aug 26 2022, 3:59 AM
Miss_Grape added a subscriber: • david.Aug 26 2022, 4:01 AM
Miss_Grape added inline comments.
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
2979

Why not set the scene for N X Ty < 64?
eg： {TTI::SK_Reverse, MVT::v2i16, 1}
@david Greene

Harbormaster completed remote builds in B183570: Diff 455858.Aug 26 2022, 5:04 AM
dmgreen added a subscriber: dmgreen.Aug 29 2022, 1:37 AM
dmgreen added inline comments.
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
2979

Hello. I don't have that many e's in my name, but I presume you meant me :)

This table acts upon legal types, through LT.second in the call to CostTableLookup. That means a v2i16 will be treated as a v2i32 (extending the i16's into the upper halves of each of the i32's), and should see a low cost of 1 because of it.

If you think the costs are wrong and need adjusting, they might need to be handled separately from this table.

Miss_Grape marked an inline comment as done.Aug 29 2022, 7:49 PM
Miss_Grape added a comment.Sep 5 2022, 7:44 PM

ping

dmgreen accepted this revision.Sep 6 2022, 1:03 AM

Hello - the updates for the comments and the new tests sound OK. I'm not sure if I'm misunderstanding and there is something else you want to propose, but these changes LGTM.

This revision is now accepted and ready to land.Sep 6 2022, 1:03 AM
This revision was landed with ongoing or failed builds.Sep 8 2022, 3:56 AM
Closed by commit rG723245bfac1a: [AARCH64][COST] Improve cost of reverse shuffles for AArch64 (authored by Miss_Grape). · Explain Why
This revision was automatically updated to reflect the committed changes.
Miss_Grape added a commit: rG723245bfac1a: [AARCH64][COST] Improve cost of reverse shuffles for AArch64.
dmgreen added a comment.Sep 8 2022, 2:14 PM

This should probably have had NFC in the title, and ended up being quite different to the version that was reviewed. We have tried not to format the tables in the past because it just creates a worse table (and obscures git-blame). I've tried to clean up the code again a little in 3875c38adf40.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
221 lines
test/
CodeGen/
AArch64/
30 lines

Diff 458701

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Show First 20 Lines • Show All 2,923 Lines • ▼ Show 20 Lines if (Mask.size() == 4 && Tp->getElementCount() == ElementCount::getFixed(4) &&
(Tp->getScalarSizeInBits() == 16 || Tp->getScalarSizeInBits() == 32) && (Tp->getScalarSizeInBits() == 16 || Tp->getScalarSizeInBits() == 32) &&
all_of(Mask, [](int E) { return E < 8; })) all_of(Mask, [](int E) { return E < 8; }))
return getPerfectShuffleCost(Mask); return getPerfectShuffleCost(Mask);
if (Kind == TTI::SK_Broadcast || Kind == TTI::SK_Transpose || if (Kind == TTI::SK_Broadcast || Kind == TTI::SK_Transpose ||
Kind == TTI::SK_Select || Kind == TTI::SK_PermuteSingleSrc || Kind == TTI::SK_Select || Kind == TTI::SK_PermuteSingleSrc ||
Kind == TTI::SK_Reverse || Kind == TTI::SK_Splice) { Kind == TTI::SK_Reverse || Kind == TTI::SK_Splice) {
static const CostTblEntry ShuffleTbl[] = { static const CostTblEntry ShuffleTbl[] = {
// Broadcast shuffle kinds can be performed with 'dup'. // Broadcast shuffle kinds can be performed with 'dup'.
{ TTI::SK_Broadcast, MVT::v8i8, 1 }, {TTI::SK_Broadcast, MVT::v8i8, 1},
{ TTI::SK_Broadcast, MVT::v16i8, 1 }, {TTI::SK_Broadcast, MVT::v16i8, 1},
{ TTI::SK_Broadcast, MVT::v4i16, 1 }, {TTI::SK_Broadcast, MVT::v4i16, 1},
{ TTI::SK_Broadcast, MVT::v8i16, 1 }, {TTI::SK_Broadcast, MVT::v8i16, 1},
{ TTI::SK_Broadcast, MVT::v2i32, 1 }, {TTI::SK_Broadcast, MVT::v2i32, 1},
{ TTI::SK_Broadcast, MVT::v4i32, 1 }, {TTI::SK_Broadcast, MVT::v4i32, 1},
{ TTI::SK_Broadcast, MVT::v2i64, 1 }, {TTI::SK_Broadcast, MVT::v2i64, 1},
{ TTI::SK_Broadcast, MVT::v2f32, 1 }, {TTI::SK_Broadcast, MVT::v2f32, 1},
{ TTI::SK_Broadcast, MVT::v4f32, 1 }, {TTI::SK_Broadcast, MVT::v4f32, 1},
{ TTI::SK_Broadcast, MVT::v2f64, 1 }, {TTI::SK_Broadcast, MVT::v2f64, 1},
// Transpose shuffle kinds can be performed with 'trn1/trn2' and // Transpose shuffle kinds can be performed with 'trn1/trn2' and
// 'zip1/zip2' instructions. // 'zip1/zip2' instructions.
{ TTI::SK_Transpose, MVT::v8i8, 1 }, {TTI::SK_Transpose, MVT::v8i8, 1},
{ TTI::SK_Transpose, MVT::v16i8, 1 }, {TTI::SK_Transpose, MVT::v16i8, 1},
{ TTI::SK_Transpose, MVT::v4i16, 1 }, {TTI::SK_Transpose, MVT::v4i16, 1},
{ TTI::SK_Transpose, MVT::v8i16, 1 }, {TTI::SK_Transpose, MVT::v8i16, 1},
{ TTI::SK_Transpose, MVT::v2i32, 1 }, {TTI::SK_Transpose, MVT::v2i32, 1},
{ TTI::SK_Transpose, MVT::v4i32, 1 }, {TTI::SK_Transpose, MVT::v4i32, 1},
{ TTI::SK_Transpose, MVT::v2i64, 1 }, {TTI::SK_Transpose, MVT::v2i64, 1},
{ TTI::SK_Transpose, MVT::v2f32, 1 }, {TTI::SK_Transpose, MVT::v2f32, 1},
{ TTI::SK_Transpose, MVT::v4f32, 1 }, {TTI::SK_Transpose, MVT::v4f32, 1},
{ TTI::SK_Transpose, MVT::v2f64, 1 }, {TTI::SK_Transpose, MVT::v2f64, 1},
// Select shuffle kinds. // Select shuffle kinds.
// TODO: handle vXi8/vXi16. // TODO: handle vXi8/vXi16.
{ TTI::SK_Select, MVT::v2i32, 1 }, // mov. {TTI::SK_Select, MVT::v2i32, 1}, // mov.
{ TTI::SK_Select, MVT::v4i32, 2 }, // rev+trn (or similar). {TTI::SK_Select, MVT::v4i32, 2}, // rev+trn (or similar).
{ TTI::SK_Select, MVT::v2i64, 1 }, // mov. {TTI::SK_Select, MVT::v2i64, 1}, // mov.
{ TTI::SK_Select, MVT::v2f32, 1 }, // mov. {TTI::SK_Select, MVT::v2f32, 1}, // mov.
{ TTI::SK_Select, MVT::v4f32, 2 }, // rev+trn (or similar). {TTI::SK_Select, MVT::v4f32, 2}, // rev+trn (or similar).
{ TTI::SK_Select, MVT::v2f64, 1 }, // mov. {TTI::SK_Select, MVT::v2f64, 1}, // mov.
// PermuteSingleSrc shuffle kinds. // PermuteSingleSrc shuffle kinds.
{ TTI::SK_PermuteSingleSrc, MVT::v2i32, 1 }, // mov. {TTI::SK_PermuteSingleSrc, MVT::v2i32, 1}, // mov.
{ TTI::SK_PermuteSingleSrc, MVT::v4i32, 3 }, // perfectshuffle worst case. {TTI::SK_PermuteSingleSrc, MVT::v4i32, 3}, // perfectshuffle worst case.
{ TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // mov. {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // mov.
{ TTI::SK_PermuteSingleSrc, MVT::v2f32, 1 }, // mov. {TTI::SK_PermuteSingleSrc, MVT::v2f32, 1}, // mov.
{ TTI::SK_PermuteSingleSrc, MVT::v4f32, 3 }, // perfectshuffle worst case. {TTI::SK_PermuteSingleSrc, MVT::v4f32, 3}, // perfectshuffle worst case.
{ TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // mov. {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // mov.
{ TTI::SK_PermuteSingleSrc, MVT::v4i16, 3 }, // perfectshuffle worst case. {TTI::SK_PermuteSingleSrc, MVT::v4i16, 3}, // perfectshuffle worst case.
{ TTI::SK_PermuteSingleSrc, MVT::v4f16, 3 }, // perfectshuffle worst case. {TTI::SK_PermuteSingleSrc, MVT::v4f16, 3}, // perfectshuffle worst case.
{ TTI::SK_PermuteSingleSrc, MVT::v4bf16, 3 }, // perfectshuffle worst case. {TTI::SK_PermuteSingleSrc, MVT::v4bf16,
3}, // perfectshuffle worst case.
{ TTI::SK_PermuteSingleSrc, MVT::v8i16, 8 }, // constpool + load + tbl {TTI::SK_PermuteSingleSrc, MVT::v8i16, 8}, // constpool + load + tbl
{ TTI::SK_PermuteSingleSrc, MVT::v8f16, 8 }, // constpool + load + tbl {TTI::SK_PermuteSingleSrc, MVT::v8f16, 8}, // constpool + load + tbl
{ TTI::SK_PermuteSingleSrc, MVT::v8bf16, 8 }, // constpool + load + tbl {TTI::SK_PermuteSingleSrc, MVT::v8bf16, 8}, // constpool + load + tbl
{ TTI::SK_PermuteSingleSrc, MVT::v8i8, 8 }, // constpool + load + tbl {TTI::SK_PermuteSingleSrc, MVT::v8i8, 8}, // constpool + load + tbl
{ TTI::SK_PermuteSingleSrc, MVT::v16i8, 8 }, // constpool + load + tbl {TTI::SK_PermuteSingleSrc, MVT::v16i8, 8}, // constpool + load + tbl
// Reverse can be lowered with `rev`. // Reverse can be lowered with `rev`.
{ TTI::SK_Reverse, MVT::v2i32, 1 }, // mov. {TTI::SK_Reverse, MVT::v2i32, 1}, // REV64
Miss_GrapeAuthorUnsubmitted
Done
ReplyInline Actions

Why not set the scene for N X Ty < 64?
eg： {TTI::SK_Reverse, MVT::v2i16, 1}
@david Greene

Miss_Grape: Why not set the scene for N X Ty < 64? eg： {TTI::SK_Reverse, MVT::v2i16, 1} @David Greene
dmgreenUnsubmitted
Done
ReplyInline Actions

Hello. I don't have that many e's in my name, but I presume you meant me :)

This table acts upon legal types, through LT.second in the call to CostTableLookup. That means a v2i16 will be treated as a v2i32 (extending the i16's into the upper halves of each of the i32's), and should see a low cost of 1 because of it.

If you think the costs are wrong and need adjusting, they might need to be handled separately from this table.

dmgreen: Hello. I don't have that many e's in my name, but I presume you meant me :) This table acts…
{ TTI::SK_Reverse, MVT::v4i32, 2 }, // REV64; EXT {TTI::SK_Reverse, MVT::v4i32, 2}, // REV64; EXT
{ TTI::SK_Reverse, MVT::v2i64, 1 }, // mov. {TTI::SK_Reverse, MVT::v2i64, 1}, // EXT
{ TTI::SK_Reverse, MVT::v2f32, 1 }, // mov. {TTI::SK_Reverse, MVT::v2f32, 1}, // REV64
{ TTI::SK_Reverse, MVT::v4f32, 2 }, // REV64; EXT {TTI::SK_Reverse, MVT::v4f32, 2}, // REV64; EXT
{ TTI::SK_Reverse, MVT::v2f64, 1 }, // mov. {TTI::SK_Reverse, MVT::v2f64, 1}, // EXT
{ TTI::SK_Reverse, MVT::v8f16, 2 }, // REV64; EXT {TTI::SK_Reverse, MVT::v8f16, 2}, // REV64; EXT
{ TTI::SK_Reverse, MVT::v8i16, 2 }, // REV64; EXT {TTI::SK_Reverse, MVT::v8i16, 2}, // REV64; EXT
{ TTI::SK_Reverse, MVT::v16i8, 2 }, // REV64; EXT {TTI::SK_Reverse, MVT::v16i8, 2}, // REV64; EXT
{ TTI::SK_Reverse, MVT::v4f16, 1 }, // REV64 {TTI::SK_Reverse, MVT::v4f16, 1}, // REV64
{ TTI::SK_Reverse, MVT::v4i16, 1 }, // REV64 {TTI::SK_Reverse, MVT::v4i16, 1}, // REV64
{ TTI::SK_Reverse, MVT::v8i8, 1 }, // REV64 {TTI::SK_Reverse, MVT::v8i8, 1}, // REV64
// Splice can all be lowered as `ext`. // Splice can all be lowered as `ext`.
{ TTI::SK_Splice, MVT::v2i32, 1 }, {TTI::SK_Splice, MVT::v2i32, 1},
{ TTI::SK_Splice, MVT::v4i32, 1 }, {TTI::SK_Splice, MVT::v4i32, 1},
{ TTI::SK_Splice, MVT::v2i64, 1 }, {TTI::SK_Splice, MVT::v2i64, 1},
{ TTI::SK_Splice, MVT::v2f32, 1 }, {TTI::SK_Splice, MVT::v2f32, 1},
{ TTI::SK_Splice, MVT::v4f32, 1 }, {TTI::SK_Splice, MVT::v4f32, 1},
{ TTI::SK_Splice, MVT::v2f64, 1 }, {TTI::SK_Splice, MVT::v2f64, 1},
{ TTI::SK_Splice, MVT::v8f16, 1 }, {TTI::SK_Splice, MVT::v8f16, 1},
{ TTI::SK_Splice, MVT::v8bf16, 1 }, {TTI::SK_Splice, MVT::v8bf16, 1},
{ TTI::SK_Splice, MVT::v8i16, 1 }, {TTI::SK_Splice, MVT::v8i16, 1},
{ TTI::SK_Splice, MVT::v16i8, 1 }, {TTI::SK_Splice, MVT::v16i8, 1},
{ TTI::SK_Splice, MVT::v4bf16, 1 }, {TTI::SK_Splice, MVT::v4bf16, 1},
{ TTI::SK_Splice, MVT::v4f16, 1 }, {TTI::SK_Splice, MVT::v4f16, 1},
{ TTI::SK_Splice, MVT::v4i16, 1 }, {TTI::SK_Splice, MVT::v4i16, 1},
{ TTI::SK_Splice, MVT::v8i8, 1 }, {TTI::SK_Splice, MVT::v8i8, 1},
// Broadcast shuffle kinds for scalable vectors // Broadcast shuffle kinds for scalable vectors
{ TTI::SK_Broadcast, MVT::nxv16i8, 1 }, {TTI::SK_Broadcast, MVT::nxv16i8, 1},
{ TTI::SK_Broadcast, MVT::nxv8i16, 1 }, {TTI::SK_Broadcast, MVT::nxv8i16, 1},
{ TTI::SK_Broadcast, MVT::nxv4i32, 1 }, {TTI::SK_Broadcast, MVT::nxv4i32, 1},
{ TTI::SK_Broadcast, MVT::nxv2i64, 1 }, {TTI::SK_Broadcast, MVT::nxv2i64, 1},
{ TTI::SK_Broadcast, MVT::nxv2f16, 1 }, {TTI::SK_Broadcast, MVT::nxv2f16, 1},
{ TTI::SK_Broadcast, MVT::nxv4f16, 1 }, {TTI::SK_Broadcast, MVT::nxv4f16, 1},
{ TTI::SK_Broadcast, MVT::nxv8f16, 1 }, {TTI::SK_Broadcast, MVT::nxv8f16, 1},
{ TTI::SK_Broadcast, MVT::nxv2bf16, 1 }, {TTI::SK_Broadcast, MVT::nxv2bf16, 1},
{ TTI::SK_Broadcast, MVT::nxv4bf16, 1 }, {TTI::SK_Broadcast, MVT::nxv4bf16, 1},
{ TTI::SK_Broadcast, MVT::nxv8bf16, 1 }, {TTI::SK_Broadcast, MVT::nxv8bf16, 1},
{ TTI::SK_Broadcast, MVT::nxv2f32, 1 }, {TTI::SK_Broadcast, MVT::nxv2f32, 1},
{ TTI::SK_Broadcast, MVT::nxv4f32, 1 }, {TTI::SK_Broadcast, MVT::nxv4f32, 1},
{ TTI::SK_Broadcast, MVT::nxv2f64, 1 }, {TTI::SK_Broadcast, MVT::nxv2f64, 1},
{ TTI::SK_Broadcast, MVT::nxv16i1, 1 }, {TTI::SK_Broadcast, MVT::nxv16i1, 1},
{ TTI::SK_Broadcast, MVT::nxv8i1, 1 }, {TTI::SK_Broadcast, MVT::nxv8i1, 1},
{ TTI::SK_Broadcast, MVT::nxv4i1, 1 }, {TTI::SK_Broadcast, MVT::nxv4i1, 1},
{ TTI::SK_Broadcast, MVT::nxv2i1, 1 }, {TTI::SK_Broadcast, MVT::nxv2i1, 1},
// Handle the cases for vector.reverse with scalable vectors // Handle the cases for vector.reverse with scalable vectors
{ TTI::SK_Reverse, MVT::nxv16i8, 1 }, {TTI::SK_Reverse, MVT::nxv16i8, 1},
{ TTI::SK_Reverse, MVT::nxv8i16, 1 }, {TTI::SK_Reverse, MVT::nxv8i16, 1},
{ TTI::SK_Reverse, MVT::nxv4i32, 1 }, {TTI::SK_Reverse, MVT::nxv4i32, 1},
{ TTI::SK_Reverse, MVT::nxv2i64, 1 }, {TTI::SK_Reverse, MVT::nxv2i64, 1},
{ TTI::SK_Reverse, MVT::nxv2f16, 1 }, {TTI::SK_Reverse, MVT::nxv2f16, 1},
{ TTI::SK_Reverse, MVT::nxv4f16, 1 }, {TTI::SK_Reverse, MVT::nxv4f16, 1},
{ TTI::SK_Reverse, MVT::nxv8f16, 1 }, {TTI::SK_Reverse, MVT::nxv8f16, 1},
{ TTI::SK_Reverse, MVT::nxv2bf16, 1 }, {TTI::SK_Reverse, MVT::nxv2bf16, 1},
{ TTI::SK_Reverse, MVT::nxv4bf16, 1 }, {TTI::SK_Reverse, MVT::nxv4bf16, 1},
{ TTI::SK_Reverse, MVT::nxv8bf16, 1 }, {TTI::SK_Reverse, MVT::nxv8bf16, 1},
{ TTI::SK_Reverse, MVT::nxv2f32, 1 }, {TTI::SK_Reverse, MVT::nxv2f32, 1},
{ TTI::SK_Reverse, MVT::nxv4f32, 1 }, {TTI::SK_Reverse, MVT::nxv4f32, 1},
{ TTI::SK_Reverse, MVT::nxv2f64, 1 }, {TTI::SK_Reverse, MVT::nxv2f64, 1},
{ TTI::SK_Reverse, MVT::nxv16i1, 1 }, {TTI::SK_Reverse, MVT::nxv16i1, 1},
{ TTI::SK_Reverse, MVT::nxv8i1, 1 }, {TTI::SK_Reverse, MVT::nxv8i1, 1},
{ TTI::SK_Reverse, MVT::nxv4i1, 1 }, {TTI::SK_Reverse, MVT::nxv4i1, 1},
{ TTI::SK_Reverse, MVT::nxv2i1, 1 }, {TTI::SK_Reverse, MVT::nxv2i1, 1},
}; };
if (const auto *Entry = CostTableLookup(ShuffleTbl, Kind, LT.second)) if (const auto *Entry = CostTableLookup(ShuffleTbl, Kind, LT.second))
return LT.first * Entry->Cost; return LT.first * Entry->Cost;
} }
if (Kind == TTI::SK_Splice && isa<ScalableVectorType>(Tp)) if (Kind == TTI::SK_Splice && isa<ScalableVectorType>(Tp))
return getSpliceCost(Tp, Index); return getSpliceCost(Tp, Index);
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll

Show All 24 Lines
; CHECK-NEXT: rev64 v0.8h, v0.8h ; CHECK-NEXT: rev64 v0.8h, v0.8h
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a) %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <2 x i16> @reverse_v2i16(<2 x i16> %a) #0 {
; CHECK-LABEL: reverse_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: rev64 v0.2s, v0.2s
; CHECK-NEXT: ret
%res = call <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16> %a)
ret <2 x i16> %res
}
define <2 x i32> @reverse_v2i32(<2 x i32> %a) #0 {
; CHECK-LABEL: reverse_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: rev64 v0.2s, v0.2s
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %a)
ret <2 x i32> %res
}
define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 { define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
; CHECK-LABEL: reverse_v4i32: ; CHECK-LABEL: reverse_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: rev64 v0.4s, v0.4s ; CHECK-NEXT: rev64 v0.4s, v0.4s
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a) %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
Show All 16 Lines
; CHECK-NEXT: rev64 v0.8h, v0.8h ; CHECK-NEXT: rev64 v0.8h, v0.8h
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a) %res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a)
ret <8 x half> %res ret <8 x half> %res
} }
define <2 x float> @reverse_v2f32(<2 x float> %a) #0 {
; CHECK-LABEL: reverse_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: rev64 v0.2s, v0.2s
; CHECK-NEXT: ret
%res = call <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float> %a)
ret <2 x float> %res
}
define <4 x float> @reverse_v4f32(<4 x float> %a) #0 { define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
; CHECK-LABEL: reverse_v4f32: ; CHECK-LABEL: reverse_v4f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: rev64 v0.4s, v0.4s ; CHECK-NEXT: rev64 v0.4s, v0.4s
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a) %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines; CHECK-FASTISEL-NEXT: ret
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a) %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
ret <16 x float> %res ret <16 x float> %res
} }
declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>) declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>) declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
declare <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16>)
declare <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32>)
declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>) declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>) declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>) declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>) declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
declare <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float>)
declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>) declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>) declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>) declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
attributes #0 = { nounwind "target-features"="+neon" } attributes #0 = { nounwind "target-features"="+neon" }