[LoongArch] Support Load and Store with 14-bit signed immediate operands

[SixWeining]

Do we need to give a better name to the test files because the tests also check other instructions except ldptr/stptr. @xen0n Any suggestion?

[xen0n]

In general you should name the testcases after your intent. For example for the getelementptr ..., 255 case it's evident you want to check {ld,st}ptr is not emitted for misaligned offsets, and for getelementptr ..., 4096 case you seem to be checking {ld,st}ptr is not emitted for out-of-range offsets. So names like ldptr_w, ldptr_w_misaligned_offset or ldptr_w_too_big_offset could be better conveying the intent.

Otherwise LGTM.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

952

I'm not sure if these AddLike's could be simplified into plain add.

@wangleiat any opinion?

[gonglingqin]

In D131954#3730927, @xen0n wrote:

In general you should name the testcases after your intent. For example for the getelementptr ..., 255 case it's evident you want to check {ld,st}ptr is not emitted for misaligned offsets, and for getelementptr ..., 4096 case you seem to be checking {ld,st}ptr is not emitted for out-of-range offsets. So names like ldptr_w, ldptr_w_misaligned_offset or ldptr_w_too_big_offset could be better conveying the intent.

Otherwise LGTM.

Thanks, I will change it.

[SixWeining]

In D131954#3730927, @xen0n wrote:

In general you should name the testcases after your intent. For example for the getelementptr ..., 255 case it's evident you want to check {ld,st}ptr is not emitted for misaligned offsets, and for getelementptr ..., 4096 case you seem to be checking {ld,st}ptr is not emitted for out-of-range offsets. So names like ldptr_w, ldptr_w_misaligned_offset or ldptr_w_too_big_offset could be better conveying the intent.

For getelementptr ..., 255, the offset is not 255 but 2040. It's also 4-bytes aligned. The reason why {ld,st}ptr is not generated is that {ld,st} is selected by codegen prior to {ld,st}ptr (maybe because the Pats for {ld,st} are defined before the Pats for {ld,st}ptr). AddedComplexity may change patterns' matching order.

[SixWeining]

llvm/test/CodeGen/LoongArch/ldptr.ll

5

How about rename to ldptr_w_too_small_offset and write some comments for this test:

;; Check that ldptr_w is not emitted for samll offsets.

21

Write some comments before this test:

;; Check that ldptr_w is emitted for applicable offsets.

39

How about rename to ldptr_w_too_big_offset and write some comments for this test:

;; Check that ldptr_w is not emitted for out-of-range offsets.

[gonglingqin]

llvm/test/CodeGen/LoongArch/ldptr.ll

5

Thanks, I will change it.

21

Thanks, I will change it.

39

Thanks, I will change it.

[gonglingqin]

Address @xen0n and @SixWeining's comments.

[xen0n]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

952

So AddLike is needed due to frame index processing producing or nodes (confirmed off-line). No problem then.

llvm/test/CodeGen/LoongArch/ldptr.ll

6

"small" ;-)

62

same here

66–68

Hmm, I wonder why LLVM isn't producing ld.w $a1, $a0, 2044 then simply ld.w $a0, $a0, 2040... I don't know if there's strong requirement to read the low bits first, but we're required to split the 64-bit access into two already, so I think it's not the case.

It would take another patch to fix this codegen nit though, if it's truly unexpected. No need to hurry this time.

llvm/test/CodeGen/LoongArch/stptr.ll

6

"small", also here.

59

and here.

And by the way it's better to refer to the instruction in its mnemonic form, i.e. "stptr.d", because this is a natural language sentence so we aren't forced to speak valid identifiers at all times. Please change all such occurrences.

[gonglingqin]

llvm/test/CodeGen/LoongArch/ldptr.ll

6

Thank you for checking, I will fix it.

62

Thanks.

66–68

Wow that's some serious simplification. I haven't seen optimizations like this on RISCV32 and ARM. Thanks.

llvm/test/CodeGen/LoongArch/stptr.ll

6

Thanks.

59

Thanks for the suggestion, I will change it.

[gonglingqin]

Address @xen0n's comments.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

def uimm15 : Operand<GRLenVT> {
   let ParserMatchClass = UImmAsmOperand<15>;
 }
 
 def simm12 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isInt<12>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<12>;
   let DecoderMethod = "decodeSImmOperand<12>";
 }
 
-def simm14_lsl2 : Operand<GRLenVT> {
+def simm14_lsl2 : Operand<GRLenVT>,
+    ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<14, "lsl2">;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<14, 2>";
 }
 
 def simm16 : Operand<GRLenVT> {
   let ParserMatchClass = SImmAsmOperand<16>;
   let DecoderMethod = "decodeSImmOperand<16>";

 defm : StPat<truncstorei8, ST_B, GPR, GRLenVT>;
 defm : StPat<truncstorei16, ST_H, GPR, GRLenVT>;
 defm : StPat<store, ST_W, GPR, i32>, Requires<[IsLA32]>;
 let Predicates = [IsLA64] in {
 defm : StPat<truncstorei32, ST_W, GPR, i64>;
 defm : StPat<store, ST_D, GPR, i64>;
 } // Predicates = [IsLA64]
 
+let Predicates = [IsLA64] in {
+def : Pat<(i64 (sextloadi32 (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
+          (LDPTR_W BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(i64 (load (AddLike BaseAddr:$rj, simm14_lsl2:$imm14))),
+          (LDPTR_D BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(truncstorei32 (i64 GPR:$rd),
+                         (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
+          (STPTR_W GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
+def : Pat<(store (i64 GPR:$rd), (AddLike BaseAddr:$rj, simm14_lsl2:$imm14)),
+          (STPTR_D GPR:$rd, BaseAddr:$rj, simm14_lsl2:$imm14)>;
+} // Predicates = [IsLA64]
+
 // LA64 register-register-addressed stores
 let Predicates = [IsLA64] in {
 class RegRegStPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy>
   : Pat<(StoreOp (i64 StTy:$rd), (add BaseAddr:$rj, GPR:$rk)),
         (Inst StTy:$rd, BaseAddr:$rj, GPR:$rk)>;
 
 def : RegRegStPat<truncstorei8, STX_B, GPR>;
 def : RegRegStPat<truncstorei16, STX_H, GPR>;

llvm/test/CodeGen/LoongArch/ldptr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define signext i32 @ld_w(ptr %p) nounwind {
+; LA32-LABEL: ld_w:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.w $a0, $a0, 2044
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ld_w:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.w $a0, $a0, 2044
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 511
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+define signext i32 @ldptr_w(ptr %p) nounwind {
+; LA32-LABEL: ldptr_w:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ori $a1, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_w:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ldptr.w $a0, $a0, 2048
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 512
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+define signext i32 @ldx_w(ptr %p) nounwind {
+; LA32-LABEL: ldx_w:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    lu12i.w $a1, 8
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldx_w:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    lu12i.w $a1, 8
+; LA64-NEXT:    ldx.w $a0, $a0, $a1
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i32, ptr %p, i64 8192
+  %val = load i32, ptr %addr, align 4
+  ret i32 %val
+}
+
+define i64 @ld_d(ptr %p) nounwind {
+; LA32-LABEL: ld_d:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.w $a2, $a0, 2040
+; LA32-NEXT:    ld.w $a1, $a0, 2044
+; LA32-NEXT:    move $a0, $a2
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ld_d:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.d $a0, $a0, 2040
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 255
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}
+
+define i64 @ldptr_d(ptr %p) nounwind {
+; LA32-LABEL: ldptr_d:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ori $a1, $zero, 2052
+; LA32-NEXT:    add.w $a1, $a0, $a1
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ld.w $a1, $a1, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldptr_d:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ldptr.d $a0, $a0, 2048
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 256
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}
+
+define i64 @ldx_d(ptr %p) nounwind {
+; LA32-LABEL: ldx_d:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    lu12i.w $a1, 8
+; LA32-NEXT:    ori $a2, $a1, 4
+; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    ld.w $a0, $a0, 0
+; LA32-NEXT:    ld.w $a1, $a2, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: ldx_d:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    lu12i.w $a1, 8
+; LA64-NEXT:    ldx.d $a0, $a0, $a1
+; LA64-NEXT:    ret
+entry:
+  %addr = getelementptr inbounds i64, ptr %p, i64 4096
+  %val = load i64, ptr %addr, align 8
+  ret i64 %val
+}

llvm/test/CodeGen/LoongArch/stptr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define void @st_w(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: st_w:
+; LA32:       # %bb.0:
+; LA32-NEXT:    st.w $a1, $a0, 2044
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: st_w:
+; LA64:       # %bb.0:
+; LA64-NEXT:    st.w $a1, $a0, 2044
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 511
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+define void @stptr_w(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: stptr_w:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_w:
+; LA64:       # %bb.0:
+; LA64-NEXT:    stptr.w $a1, $a0, 2048
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 512
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+define void @stx_w(ptr %p, i32 signext %val) nounwind {
+; LA32-LABEL: stx_w:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a2, 8
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stx_w:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a2, 8
+; LA64-NEXT:    stx.w $a1, $a0, $a2
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i32, ptr %p, i64 8192
+  store i32 %val, ptr %addr, align 4
+  ret void
+}
+
+define void @st_d(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: st_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    st.w $a2, $a0, 2044
+; LA32-NEXT:    st.w $a1, $a0, 2040
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: st_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    st.d $a1, $a0, 2040
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 255
+  store i64 %val, ptr %addr, align 8
+  ret void
+}
+
+define void @stptr_d(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: stptr_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ori $a3, $zero, 2052
+; LA32-NEXT:    add.w $a3, $a0, $a3
+; LA32-NEXT:    st.w $a2, $a3, 0
+; LA32-NEXT:    ori $a2, $zero, 2048
+; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stptr_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    stptr.d $a1, $a0, 2048
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 256
+  store i64 %val, ptr %addr, align 8
+  ret void
+}
+
+define void @stx_d(ptr %p, i64 %val) nounwind {
+; LA32-LABEL: stx_d:
+; LA32:       # %bb.0:
+; LA32-NEXT:    lu12i.w $a3, 8
+; LA32-NEXT:    add.w $a4, $a0, $a3
+; LA32-NEXT:    st.w $a1, $a4, 0
+; LA32-NEXT:    ori $a1, $a3, 4
+; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    st.w $a2, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: stx_d:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu12i.w $a2, 8
+; LA64-NEXT:    stx.d $a1, $a0, $a2
+; LA64-NEXT:    ret
+  %addr = getelementptr inbounds i64, ptr %p, i64 4096
+  store i64 %val, ptr %addr, align 8
+  ret void
+}