[LoongArch] Add insn aliases `jr` and `ret`

[SixWeining]

LGTM. Thanks.

[xen0n]

rebase

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 } // Defs = [R3], Uses = [R3]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 def : InstAlias<"nop", (ANDI R0, R0, 0)>;
 def : InstAlias<"move $dst, $src", (OR GPR:$dst, GPR:$src, R0)>;
+// `ret` is supported since binutils commit 20f2e2686c79a5ac (version 2.40 and
+// later).
+def : InstAlias<"ret", (JIRL R0, R1, 0)>;
+def : InstAlias<"jr $rj", (JIRL R0, GPR:$rj, 0)>;
 
 //===----------------------------------------------------------------------===//
 // Basic Floating-Point Instructions
 //===----------------------------------------------------------------------===//
 
 include "LoongArchFloat32InstrInfo.td"
 include "LoongArchFloat64InstrInfo.td"
 

llvm/test/CodeGen/LoongArch/analyze-branch.ll

 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a1, $zero, 42
 ; CHECK-NEXT:    bne $a0, $a1, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %true
 ; CHECK-NEXT:    bl test_true
 ; CHECK-NEXT:  .LBB0_2: # %true
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_3: # %false
 ; CHECK-NEXT:    bl test_false
 ; CHECK-NEXT:    b .LBB0_2
   %tst = icmp eq i64 %in, 42
   br i1 %tst, label %true, label %false, !prof !0
 
 ;; Expected layout order is: Entry, TrueBlock, FalseBlock
 ;; Entry->TrueBlock is the common path, which should be taken whenever the

 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a1, $zero, 42
 ; CHECK-NEXT:    beq $a0, $a1, .LBB1_1
 ; CHECK-NEXT:  # %bb.3: # %false
 ; CHECK-NEXT:    bl test_false
 ; CHECK-NEXT:  .LBB1_2: # %true
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_1: # %true
 ; CHECK-NEXT:    bl test_true
 ; CHECK-NEXT:    b .LBB1_2
   %tst = icmp eq i64 %in, 42
   br i1 %tst, label %true, label %false, !prof !1
 
 ;; Expected layout order is: Entry, FalseBlock, TrueBlock
 ;; Entry->FalseBlock is the common path, which should be taken whenever the

llvm/test/CodeGen/LoongArch/bitreverse.ll

 declare i64 @llvm.bitreverse.i64(i64)
 declare i77 @llvm.bitreverse.i77(i77)
 declare i128 @llvm.bitreverse.i128(i128)
 
 define i8 @test_bitreverse_i8(i8 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.4b $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.4b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i8 @llvm.bitreverse.i8(i8 %a)
   ret i8 %tmp
 }
 
 define i16 @test_bitreverse_i16(i16 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a0, $a0
 ; LA32-NEXT:    srli.w $a0, $a0, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 48
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i16 @llvm.bitreverse.i16(i16 %a)
   ret i16 %tmp
 }
 
 define i32 @test_bitreverse_i32(i32 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.w $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i32 @llvm.bitreverse.i32(i32 %a)
   ret i32 %tmp
 }
 
 define i64 @test_bitreverse_i64(i64 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a2, $a1
 ; LA32-NEXT:    bitrev.w $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i64 @llvm.bitreverse.i64(i64 %a)
   ret i64 %tmp
 }
 
 ;; Bitreverse on non-native integer widths.
 
 define i7 @test_bitreverse_i7(i7 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i7:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a0, $a0
 ; LA32-NEXT:    srli.w $a0, $a0, 25
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i7:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 57
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i7 @llvm.bitreverse.i7(i7 %a)
   ret i7 %tmp
 }
 
 define i24 @test_bitreverse_i24(i24 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i24:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a0, $a0
 ; LA32-NEXT:    srli.w $a0, $a0, 8
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i24:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 40
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i24 @llvm.bitreverse.i24(i24 %a)
   ret i24 %tmp
 }
 
 define i48 @test_bitreverse_i48(i48 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i48:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.w $a1, $a1
 ; LA32-NEXT:    srli.w $a1, $a1, 16
 ; LA32-NEXT:    bitrev.w $a2, $a0
 ; LA32-NEXT:    slli.w $a0, $a2, 16
 ; LA32-NEXT:    or $a0, $a1, $a0
 ; LA32-NEXT:    srli.w $a1, $a2, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i48:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i48 @llvm.bitreverse.i48(i48 %a)
   ret i48 %tmp
 }
 
 define i77 @test_bitreverse_i77(i77 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i77:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bitrev.w $a2, $a2
 ; LA32-NEXT:    ld.w $a3, $a1, 4
 ; LA32-NEXT:    bitrev.w $a3, $a3
 ; LA32-NEXT:    srli.w $a4, $a3, 19
 ; LA32-NEXT:    slli.w $a5, $a2, 13
 ; LA32-NEXT:    or $a4, $a5, $a4
 ; LA32-NEXT:    srli.w $a2, $a2, 19
 ; LA32-NEXT:    st.h $a2, $a0, 8
 ; LA32-NEXT:    st.w $a4, $a0, 4
 ; LA32-NEXT:    slli.w $a2, $a3, 13
 ; LA32-NEXT:    ld.w $a1, $a1, 8
 ; LA32-NEXT:    bitrev.w $a1, $a1
 ; LA32-NEXT:    srli.w $a1, $a1, 19
 ; LA32-NEXT:    or $a1, $a1, $a2
 ; LA32-NEXT:    st.w $a1, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i77:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a1, $a1
 ; LA64-NEXT:    srli.d $a1, $a1, 51
 ; LA64-NEXT:    bitrev.d $a2, $a0
 ; LA64-NEXT:    slli.d $a0, $a2, 13
 ; LA64-NEXT:    or $a0, $a1, $a0
 ; LA64-NEXT:    srli.d $a1, $a2, 51
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i77 @llvm.bitreverse.i77(i77 %a)
   ret i77 %tmp
 }
 
 define i128 @test_bitreverse_i128(i128 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_i128:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bitrev.w $a2, $a2
 ; LA32-NEXT:    st.w $a2, $a0, 12
 ; LA32-NEXT:    ld.w $a2, $a1, 4
 ; LA32-NEXT:    bitrev.w $a2, $a2
 ; LA32-NEXT:    st.w $a2, $a0, 8
 ; LA32-NEXT:    ld.w $a2, $a1, 8
 ; LA32-NEXT:    bitrev.w $a2, $a2
 ; LA32-NEXT:    st.w $a2, $a0, 4
 ; LA32-NEXT:    ld.w $a1, $a1, 12
 ; LA32-NEXT:    bitrev.w $a1, $a1
 ; LA32-NEXT:    st.w $a1, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_i128:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.d $a2, $a1
 ; LA64-NEXT:    bitrev.d $a1, $a0
 ; LA64-NEXT:    move $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i128 @llvm.bitreverse.i128(i128 %a)
   ret i128 %tmp
 }

llvm/test/CodeGen/LoongArch/bstrins_d.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 ;; Test generation of the bstrins.d instruction.
 ;; There are 8 patterns that can be matched to bstrins.d. See performORCombine
 ;; for details.
 
 ;; Pattern 1
 ;; R = or (and X, mask0), (and (shl Y, lsb), mask1)
 ;; =>
 ;; R = BSTRINS X, Y, msb, lsb
 define i64 @pat1(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 39, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -1099511562241  ; 0xffffff000000ffff
   %shl = shl i64 %b, 16
   %and2 = and i64 %shl, 1099511562240 ; 0x000000ffffff0000
   %or = or i64 %and1, %and2
   ret i64 %or
 }
 
 define i64 @pat1_swap(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat1_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 39, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -1099511562241  ; 0xffffff000000ffff
   %shl = shl i64 %b, 16
   %and2 = and i64 %shl, 1099511562240 ; 0x000000ffffff0000
   %or = or i64 %and2, %and1
   ret i64 %or
 }
 
 ;; Pattern 2
 ;; R = or (and X, mask0), (shl (and Y, mask1), lsb)
 ;; =>
 ;; R = BSTRINS X, Y, msb, lsb
 define i64 @pat2(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 39, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -1099511562241 ; 0xffffff000000ffff
   %and2 = and i64 %b, 16777215       ; 0x0000000000ffffff
   %shl = shl i64 %and2, 16
   %or = or i64 %and1, %shl
   ret i64 %or
 }
 
 define i64 @pat2_swap(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat2_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 39, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -1099511562241 ; 0xffffff000000ffff
   %and2 = and i64 %b, 16777215       ; 0x0000000000ffffff
   %shl = shl i64 %and2, 16
   %or = or i64 %shl, %and1
   ret i64 %or
 }
 
 ;; Pattern 3
 ;; R = or (and X, mask0), (and Y, mask1)
 ;; =>
 ;; R = BSTRINS X, (srl (and Y, mask1), lsb), msb, lsb
 define i64 @pat3(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a1, $a1, 288
 ; CHECK-NEXT:    srli.d $a1, $a1, 4
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -4081 ; 0xfffffffffffff00f
   %and2 = and i64 %b, 288   ; 0x0000000000000120
   %or = or i64 %and1, %and2
   ret i64 %or
 }
 
 define i64 @pat3_swap(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat3_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a1, $a1, 288
 ; CHECK-NEXT:    srli.d $a1, $a1, 4
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i64 %a, -4081 ; 0xfffffffffffff00f
   %and2 = and i64 %b, 288   ; 0x0000000000000120
   %or = or i64 %and2, %and1
   ret i64 %or
 }
 
 ;; Pattern 4
 ;; R = or (and X, mask), (shl Y, shamt)
 ;; =>
 ;; R = BSTRINS X, Y, 63, shamt
 define i64 @pat4(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 63, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 255
   %shl = shl i64 %b, 8
   %or = or i64 %and, %shl
   ret i64 %or
 }
 
 define i64 @pat4_swap(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: pat4_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 63, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 255
   %shl = shl i64 %b, 8
   %or = or i64 %shl, %and
   ret i64 %or
 }
 
 ;; Pattern 5
 ;; R = or (and X, mask0), const
 ;; =>
 ;; R = BSTRINS X, (const >> lsb), msb, lsb
 define i64 @pat5(i64 %a) nounwind {
 ; CHECK-LABEL: pat5:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 74565
 ; CHECK-NEXT:    ori $a1, $a1, 1656
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 47, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 18446462598732906495 ; 0xffff00000000ffff
   %or = or i64 %and, 20015998304256       ; 0x0000123456780000
   ret i64 %or
 }
 
 ;; Pattern 6: a = b | ((c & mask) << shamt)
 ;; In this testcase b is 0x123456000000789a, but in fact we do not require b
 ;; being a constant. As long as all positions in b to be overwritten by the
 ;; incoming bits are known to be zero, the pattern could be matched.
 define i64 @pat6(i64 %c) nounwind {
 ; CHECK-LABEL: pat6:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 7
 ; CHECK-NEXT:    ori $a1, $a1, 2202
 ; CHECK-NEXT:    lu32i.d $a1, 284160
 ; CHECK-NEXT:    lu52i.d $a1, $a1, 291
 ; CHECK-NEXT:    bstrins.d $a1, $a0, 39, 16
 ; CHECK-NEXT:    move $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %c, 16777215            ; 0x0000000000ffffff
   %shl = shl i64 %and, 16
   %or = or i64 %shl, 1311767949471676570 ; 0x123456000000789a
   ret i64 %or
 }
 
 ;; Pattern 7: a = b | ((c << shamt) & shifted_mask)
 ;; Similar to pattern 6.
 define i64 @pat7(i64 %c) nounwind {
 ; CHECK-LABEL: pat7:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 7
 ; CHECK-NEXT:    ori $a1, $a1, 2202
 ; CHECK-NEXT:    lu32i.d $a1, 284160
 ; CHECK-NEXT:    lu52i.d $a1, $a1, 291
 ; CHECK-NEXT:    bstrins.d $a1, $a0, 39, 16
 ; CHECK-NEXT:    move $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shl = shl i64 %c, 16
   %and = and i64 %shl, 1099511562240     ; 0x000000ffffff0000
   %or = or i64 %and, 1311767949471676570 ; 0x123456000000789a
   ret i64 %or
 }
 
 ;; Pattern 8: a = b | (c & shifted_mask)
 ;; Similar to pattern 7 but without shift to c.
 define i64 @pat8(i64 %c) nounwind {
 ; CHECK-LABEL: pat8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srli.d $a1, $a0, 16
 ; CHECK-NEXT:    lu12i.w $a0, 7
 ; CHECK-NEXT:    ori $a0, $a0, 2202
 ; CHECK-NEXT:    lu32i.d $a0, 284160
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 291
 ; CHECK-NEXT:    bstrins.d $a0, $a1, 39, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %c, 1099511562240       ; 0x000000ffffff0000
   %or = or i64 %and, 1311767949471676570 ; 0x123456000000789a
   ret i64 %or
 }
 
 ;; Test that bstrins.d is not generated because constant OR operand
 ;; doesn't fit into bits cleared by constant AND operand.
 define i64 @no_bstrins_d(i64 %a) nounwind {
 ; CHECK-LABEL: no_bstrins_d:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 354185
 ; CHECK-NEXT:    lu32i.d $a1, 4660
 ; CHECK-NEXT:    or $a0, $a0, $a1
 ; CHECK-NEXT:    lu12i.w $a1, 354191
 ; CHECK-NEXT:    ori $a1, $a1, 4095
 ; CHECK-NEXT:    lu32i.d $a1, -60876
 ; CHECK-NEXT:    and $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 18446462598732906495 ; 0xffff00000000ffff
   %or = or i64 %and, 20015998341120       ; 0x0000123456789000
   ret i64 %or
 }

llvm/test/CodeGen/LoongArch/bstrins_w.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
 
 ;; Test generation of the bstrins.w instruction.
 ;; There are 8 patterns that can be matched to bstrins.w. See performORCombine
 ;; for details.
 
 ;; Pattern 1
 ;; R = or (and X, mask0), (and (shl Y, lsb), mask1)
 ;; =>
 ;; R = BSTRINS X, Y, msb, lsb
 define i32 @pat1(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 19, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -1048321  ; 0xfff000ff
   %shl = shl i32 %b, 8
   %and2 = and i32 %shl, 1048320 ; 0x000fff00
   %or = or i32 %and1, %and2
   ret i32 %or
 }
 
 define i32 @pat1_swap(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat1_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 19, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -1048321  ; 0xfff000ff
   %shl = shl i32 %b, 8
   %and2 = and i32 %shl, 1048320 ; 0x000fff00
   %or = or i32 %and2, %and1
   ret i32 %or
 }
 
 ;; Pattern 2
 ;; R = or (and X, mask0), (shl (and Y, mask1), lsb)
 ;; =>
 ;; R = BSTRINS X, Y, msb, lsb
 define i32 @pat2(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 19, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -1048321 ; 0xfff000ff
   %and2 = and i32 %b, 4095     ; 0x00000fff
   %shl = shl i32 %and2, 8
   %or = or i32 %and1, %shl
   ret i32 %or
 }
 
 define i32 @pat2_swap(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat2_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 19, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -1048321 ; 0xfff000ff
   %and2 = and i32 %b, 4095     ; 0x00000fff
   %shl = shl i32 %and2, 8
   %or = or i32 %shl, %and1
   ret i32 %or
 }
 
 ;; Pattern 3
 ;; R = or (and X, mask0), (and Y, mask1)
 ;; =>
 ;; R = BSTRINS X, (srl (and Y, mask1), lsb), msb, lsb
 define i32 @pat3(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a1, $a1, 288
 ; CHECK-NEXT:    srli.w $a1, $a1, 4
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -4081 ; 0xfffff00f
   %and2 = and i32 %b, 288   ; 0x00000120
   %or = or i32 %and1, %and2
   ret i32 %or
 }
 
 define i32 @pat3_swap(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat3_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a1, $a1, 288
 ; CHECK-NEXT:    srli.w $a1, $a1, 4
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, -4081 ; 0xfffff00f
   %and2 = and i32 %b, 288   ; 0x00000120
   %or = or i32 %and2, %and1
   ret i32 %or
 }
 
 define i32 @pat3_positive_mask0(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat3_positive_mask0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srli.w $a1, $a1, 28
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 31, 28
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and1 = and i32 %a, 268435455  ; 0x0fffffff
   %and2 = and i32 %b, 4026531840 ; 0xf0000000
   %or = or i32 %and1, %and2
   ret i32 %or
 }
 
 ;; Pattern 4
 ;; R = or (and X, mask), (shl Y, shamt)
 ;; =>
 ;; R = BSTRINS X, Y, 31, shamt
 define i32 @pat4(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 31, 28
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 268435455 ; 0x0fffffff
   %shl = shl i32 %b, 28
   %or = or i32 %and, %shl
   ret i32 %or
 }
 
 define i32 @pat4_swap(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: pat4_swap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 31, 28
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 268435455 ; 0x0fffffff
   %shl = shl i32 %b, 28
   %or = or i32 %shl, %and
   ret i32 %or
 }
 
 ;; Pattern 5
 ;; R = or (and X, mask), const
 ;; =>
 ;; R = BSTRINS X, (const >> lsb), msb, lsb
 define i32 @pat5(i32 %a) nounwind {
 ; CHECK-LABEL: pat5:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 1
 ; CHECK-NEXT:    ori $a1, $a1, 564
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 23, 8
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4278190335 ; 0xff0000ff
   %or = or i32 %and, 1192960    ; 0x00123400
   ret i32 %or
 }
 
 ;; Pattern 6: a = b | ((c & mask) << shamt)
 ;; In this testcase b is 0x10000002, but in fact we do not require b being a
 ;; constant. As long as all positions in b to be overwritten by the incoming
 ;; bits are known to be zero, the pattern could be matched.
 define i32 @pat6(i32 %c) nounwind {
 ; CHECK-LABEL: pat6:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 65536
 ; CHECK-NEXT:    ori $a1, $a1, 2
 ; CHECK-NEXT:    bstrins.w $a1, $a0, 27, 4
 ; CHECK-NEXT:    move $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %c, 16777215  ; 0x00ffffff
   %shl = shl i32 %and, 4
   %or = or i32 %shl, 268435458 ; 0x10000002
   ret i32 %or
 }
 
 ;; Pattern 7: a = b | ((c << shamt) & shifted_mask)
 ;; Similar to pattern 6.
 define i32 @pat7(i32 %c) nounwind {
 ; CHECK-LABEL: pat7:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 65536
 ; CHECK-NEXT:    ori $a1, $a1, 2
 ; CHECK-NEXT:    bstrins.w $a1, $a0, 27, 4
 ; CHECK-NEXT:    move $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shl = shl i32 %c, 4
   %and = and i32 %shl, 268435440 ; 0x0ffffff0
   %or = or i32 %and, 268435458   ; 0x10000002
   ret i32 %or
 }
 
 ;; Pattern 8: a = b | (c & shifted_mask)
 ;; Similar to pattern 7 but without shift to c.
 define i32 @pat8(i32 %c) nounwind {
 ; CHECK-LABEL: pat8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srli.w $a1, $a0, 4
 ; CHECK-NEXT:    lu12i.w $a0, 65536
 ; CHECK-NEXT:    ori $a0, $a0, 2
 ; CHECK-NEXT:    bstrins.w $a0, $a1, 27, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %c, 268435440 ; 0x0ffffff0
   %or = or i32 %and, 268435458 ; 0x10000002
   ret i32 %or
 }
 
 ;; Test that bstrins.w is not generated because constant OR operand
 ;; doesn't fit into bits cleared by constant AND operand.
 define i32 @no_bstrins_w(i32 %a) nounwind {
 ; CHECK-LABEL: no_bstrins_w:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a1, 291
 ; CHECK-NEXT:    ori $a1, $a1, 1104
 ; CHECK-NEXT:    or $a0, $a0, $a1
 ; CHECK-NEXT:    lu12i.w $a1, -3805
 ; CHECK-NEXT:    ori $a1, $a1, 1279
 ; CHECK-NEXT:    and $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4278190335 ; 0xff0000ff
   %or = or i32 %and, 1193040    ; 0x00123450
   ret i32 %or
 }

llvm/test/CodeGen/LoongArch/bstrpick_d.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define i64 @lshr40_and255(i64 %a) {
 ; CHECK-LABEL: lshr40_and255:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 47, 40
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shr = lshr i64 %a, 40
   %and = and i64 %shr, 255
   ret i64 %and
 }
 
 define i64 @ashr50_and511(i64 %a) {
 ; CHECK-LABEL: ashr50_and511:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 58, 50
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shr = ashr i64 %a, 50
   %and = and i64 %shr, 511
   ret i64 %and
 }
 
 define i64 @zext_i32_to_i64(i32 %a) {
 ; CHECK-LABEL: zext_i32_to_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %res = zext i32 %a to i64
   ret i64 %res
 }
 
 define i64 @and8191(i64 %a) {
 ; CHECK-LABEL: and8191:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 12, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 8191
   ret i64 %and
 }
 
 ;; Check that andi but not bstrpick.d is generated.
 define i64 @and4095(i64 %a) {
 ; CHECK-LABEL: and4095:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 4095
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 4095
   ret i64 %and
 }
 
 ;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4)
 define i64 @and0xff0_lshr4(i64 %a) {
 ; CHECK-LABEL: and0xff0_lshr4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 4080
   %shr = lshr i64 %and, 4
   ret i64 %shr
 }
 
 ;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5).
 ;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5)
 ;; firstly by DAGCombiner::SimplifyDemandedBits.
 define i64 @and4080_ashr5(i64 %a) {
 ; CHECK-LABEL: and4080_ashr5:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.d $a0, $a0, 11, 5
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 4080
   %shr = ashr i64 %and, 5
   ret i64 %shr
 }
 
 ;; Negative test: the second operand of AND is not a shifted mask
 define i64 @and0xf30_lshr4(i64 %a) {
 ; CHECK-LABEL: and0xf30_lshr4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 3888
 ; CHECK-NEXT:    srli.d $a0, $a0, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 3888
   %shr = lshr i64 %and, 4
   ret i64 %shr
 }
 
 ;; Negative test: Shamt < MaskIdx
 define i64 @and0xff0_lshr3(i64 %a) {
 ; CHECK-LABEL: and0xff0_lshr3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 4080
 ; CHECK-NEXT:    srli.d $a0, $a0, 3
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i64 %a, 4080
   %shr = lshr i64 %and, 3
   ret i64 %shr
 }

llvm/test/CodeGen/LoongArch/bstrpick_w.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
 
 define i32 @lshr10_and255(i32 %a) {
 ; CHECK-LABEL: lshr10_and255:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 17, 10
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shr = lshr i32 %a, 10
   %and = and i32 %shr, 255
   ret i32 %and
 }
 
 define i32 @ashr20_and511(i32 %a) {
 ; CHECK-LABEL: ashr20_and511:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 28, 20
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %shr = ashr i32 %a, 20
   %and = and i32 %shr, 511
   ret i32 %and
 }
 
 define i32 @zext_i16_to_i32(i16 %a) {
 ; CHECK-LABEL: zext_i16_to_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 15, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %res = zext i16 %a to i32
   ret i32 %res
 }
 
 define i32 @and8191(i32 %a) {
 ; CHECK-LABEL: and8191:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 12, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 8191
   ret i32 %and
 }
 
 ;; Check that andi but not bstrpick.d is generated.
 define i32 @and4095(i32 %a) {
 ; CHECK-LABEL: and4095:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 4095
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4095
   ret i32 %and
 }
 
 ;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4)
 define i32 @and0xff0_lshr4(i32 %a) {
 ; CHECK-LABEL: and0xff0_lshr4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 11, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4080
   %shr = lshr i32 %and, 4
   ret i32 %shr
 }
 
 ;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5).
 ;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5)
 ;; firstly by DAGCombiner::SimplifyDemandedBits.
 define i32 @and4080_ashr5(i32 %a) {
 ; CHECK-LABEL: and4080_ashr5:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bstrpick.w $a0, $a0, 11, 5
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4080
   %shr = ashr i32 %and, 5
   ret i32 %shr
 }
 
 ;; Negative test: the second operand of AND is not a shifted mask
 define i32 @and0xf30_lshr4(i32 %a) {
 ; CHECK-LABEL: and0xf30_lshr4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 3888
 ; CHECK-NEXT:    srli.w $a0, $a0, 4
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 3888
   %shr = lshr i32 %and, 4
   ret i32 %shr
 }
 
 ;; Negative test: Shamt < MaskIdx
 define i32 @and0xff0_lshr3(i32 %a) {
 ; CHECK-LABEL: and0xff0_lshr3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi $a0, $a0, 4080
 ; CHECK-NEXT:    srli.w $a0, $a0, 3
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %and = and i32 %a, 4080
   %shr = lshr i32 %and, 3
   ret i32 %shr
 }

llvm/test/CodeGen/LoongArch/bswap-bitreverse.ll

 declare i64 @llvm.bswap.i64(i64)
 
 define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind {
 ; LA32-LABEL: test_bswap_bitreverse_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a0, $a0
 ; LA32-NEXT:    bitrev.w $a0, $a0
 ; LA32-NEXT:    srli.w $a0, $a0, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_bitreverse_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.2h $a0, $a0
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 48
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i16 @llvm.bswap.i16(i16 %a)
   %tmp2 = call i16 @llvm.bitreverse.i16(i16 %tmp)
   ret i16 %tmp2
 }
 
 define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind {
 ; LA32-LABEL: test_bswap_bitreverse_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.4b $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_bitreverse_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.4b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i32 @llvm.bswap.i32(i32 %a)
   %tmp2 = call i32 @llvm.bitreverse.i32(i32 %tmp)
   ret i32 %tmp2
 }
 
 define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind {
 ; LA32-LABEL: test_bswap_bitreverse_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.4b $a0, $a0
 ; LA32-NEXT:    bitrev.4b $a1, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_bitreverse_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.8b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i64 @llvm.bswap.i64(i64 %a)
   %tmp2 = call i64 @llvm.bitreverse.i64(i64 %tmp)
   ret i64 %tmp2
 }
 
 define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_bswap_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a0, $a0
 ; LA32-NEXT:    bitrev.w $a0, $a0
 ; LA32-NEXT:    srli.w $a0, $a0, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_bswap_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.2h $a0, $a0
 ; LA64-NEXT:    bitrev.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 48
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i16 @llvm.bitreverse.i16(i16 %a)
   %tmp2 = call i16 @llvm.bswap.i16(i16 %tmp)
   ret i16 %tmp2
 }
 
 define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_bswap_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.4b $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_bswap_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.4b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i32 @llvm.bitreverse.i32(i32 %a)
   %tmp2 = call i32 @llvm.bswap.i32(i32 %tmp)
   ret i32 %tmp2
 }
 
 define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
 ; LA32-LABEL: test_bitreverse_bswap_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bitrev.4b $a0, $a0
 ; LA32-NEXT:    bitrev.4b $a1, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bitreverse_bswap_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bitrev.8b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i64 @llvm.bitreverse.i64(i64 %a)
   %tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
   ret i64 %tmp2
 }
 
 define i32 @pr55484(i32 %0) {
 ; LA32-LABEL: pr55484:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a0, 8
 ; LA32-NEXT:    srli.w $a0, $a0, 8
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    ext.w.h $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: pr55484:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a0, 8
 ; LA64-NEXT:    srli.d $a0, $a0, 8
 ; LA64-NEXT:    or $a0, $a0, $a1
 ; LA64-NEXT:    ext.w.h $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %2 = lshr i32 %0, 8
   %3 = shl i32 %0, 8
   %4 = or i32 %2, %3
   %5 = trunc i32 %4 to i16
   %6 = sext i16 %5 to i32
   ret i32 %6
 }

llvm/test/CodeGen/LoongArch/bswap.ll

 declare i64 @llvm.bswap.i64(i64)
 declare i80 @llvm.bswap.i80(i80)
 declare i128 @llvm.bswap.i128(i128)
 
 define i16 @test_bswap_i16(i16 %a) nounwind {
 ; LA32-LABEL: test_bswap_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.2h $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i16 @llvm.bswap.i16(i16 %a)
   ret i16 %tmp
 }
 
 define i32 @test_bswap_i32(i32 %a) nounwind {
 ; LA32-LABEL: test_bswap_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a0, $a0
 ; LA32-NEXT:    rotri.w $a0, $a0, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.2w $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %tmp
 }
 
 define i64 @test_bswap_i64(i64 %a) nounwind {
 ; LA32-LABEL: test_bswap_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a1, $a1
 ; LA32-NEXT:    rotri.w $a2, $a1, 16
 ; LA32-NEXT:    revb.2h $a0, $a0
 ; LA32-NEXT:    rotri.w $a1, $a0, 16
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.d $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %tmp
 }
 
 ;; Bswap on non-native integer widths.
 
 define i48 @test_bswap_i48(i48 %a) nounwind {
 ; LA32-LABEL: test_bswap_i48:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    revb.2h $a1, $a1
 ; LA32-NEXT:    rotri.w $a1, $a1, 16
 ; LA32-NEXT:    srli.w $a1, $a1, 16
 ; LA32-NEXT:    revb.2h $a0, $a0
 ; LA32-NEXT:    rotri.w $a2, $a0, 16
 ; LA32-NEXT:    slli.w $a0, $a2, 16
 ; LA32-NEXT:    or $a0, $a1, $a0
 ; LA32-NEXT:    srli.w $a1, $a2, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i48:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.d $a0, $a0
 ; LA64-NEXT:    srli.d $a0, $a0, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i48 @llvm.bswap.i48(i48 %a)
   ret i48 %tmp
 }
 
 define i80 @test_bswap_i80(i80 %a) nounwind {
 ; LA32-LABEL: test_bswap_i80:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0

 ; LA32-NEXT:    st.w $a4, $a0, 4
 ; LA32-NEXT:    slli.w $a2, $a3, 16
 ; LA32-NEXT:    ld.w $a1, $a1, 8
 ; LA32-NEXT:    revb.2h $a1, $a1
 ; LA32-NEXT:    rotri.w $a1, $a1, 16
 ; LA32-NEXT:    srli.w $a1, $a1, 16
 ; LA32-NEXT:    or $a1, $a1, $a2
 ; LA32-NEXT:    st.w $a1, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i80:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.d $a1, $a1
 ; LA64-NEXT:    srli.d $a1, $a1, 48
 ; LA64-NEXT:    revb.d $a2, $a0
 ; LA64-NEXT:    slli.d $a0, $a2, 16
 ; LA64-NEXT:    or $a0, $a1, $a0
 ; LA64-NEXT:    srli.d $a1, $a2, 48
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i80 @llvm.bswap.i80(i80 %a)
   ret i80 %tmp
 }
 
 define i128 @test_bswap_i128(i128 %a) nounwind {
 ; LA32-LABEL: test_bswap_i128:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    revb.2h $a2, $a2
 ; LA32-NEXT:    rotri.w $a2, $a2, 16
 ; LA32-NEXT:    st.w $a2, $a0, 12
 ; LA32-NEXT:    ld.w $a2, $a1, 4
 ; LA32-NEXT:    revb.2h $a2, $a2
 ; LA32-NEXT:    rotri.w $a2, $a2, 16
 ; LA32-NEXT:    st.w $a2, $a0, 8
 ; LA32-NEXT:    ld.w $a2, $a1, 8
 ; LA32-NEXT:    revb.2h $a2, $a2
 ; LA32-NEXT:    rotri.w $a2, $a2, 16
 ; LA32-NEXT:    st.w $a2, $a0, 4
 ; LA32-NEXT:    ld.w $a1, $a1, 12
 ; LA32-NEXT:    revb.2h $a1, $a1
 ; LA32-NEXT:    rotri.w $a1, $a1, 16
 ; LA32-NEXT:    st.w $a1, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_bswap_i128:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    revb.d $a2, $a1
 ; LA64-NEXT:    revb.d $a1, $a0
 ; LA64-NEXT:    move $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %tmp = call i128 @llvm.bswap.i128(i128 %a)
   ret i128 %tmp
 }

llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 --mattr=+d --target-abi=lp64d < %s \
 ; RUN:   | FileCheck %s
 
 ;; Check that on LA64, i128 is passed in a pair of GPRs.
 define i64 @callee_i128_in_regs(i64 %a, i128 %b) nounwind {
 ; CHECK-LABEL: callee_i128_in_regs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %b_trunc = trunc i128 %b to i64
   %1 = add i64 %a, %b_trunc
   ret i64 %1
 }
 
 define i64 @caller_i128_in_regs() nounwind {
 ; CHECK-LABEL: caller_i128_in_regs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    ori $a1, $zero, 2
 ; CHECK-NEXT:    move $a2, $zero
 ; CHECK-NEXT:    bl callee_i128_in_regs
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_i128_in_regs(i64 1, i128 2)
   ret i64 %1
 }
 
 ;; Check that the stack is used once the GPRs are exhausted.
 define i64 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i128 %e, i64 %f, i128 %g, i64 %h) nounwind {
 ; CHECK-LABEL: callee_many_scalars:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld.d $t0, $sp, 0
 ; CHECK-NEXT:    xor $a5, $a5, $t0
 ; CHECK-NEXT:    xor $a4, $a4, $a7
 ; CHECK-NEXT:    or $a4, $a4, $a5
 ; CHECK-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; CHECK-NEXT:    andi $a0, $a0, 255
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
 ; CHECK-NEXT:    bstrpick.d $a1, $a2, 31, 0
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
 ; CHECK-NEXT:    add.d $a0, $a0, $a3
 ; CHECK-NEXT:    sltui $a1, $a4, 1
 ; CHECK-NEXT:    add.d $a0, $a1, $a0
 ; CHECK-NEXT:    add.d $a0, $a0, $a6
 ; CHECK-NEXT:    ld.d $a1, $sp, 8
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %a_ext = zext i8 %a to i64
   %b_ext = zext i16 %b to i64
   %c_ext = zext i32 %c to i64
   %1 = add i64 %a_ext, %b_ext
   %2 = add i64 %1, %c_ext
   %3 = add i64 %2, %d
   %4 = icmp eq i128 %e, %g
   %5 = zext i1 %4 to i64

 ; CHECK-NEXT:    ori $a3, $zero, 4
 ; CHECK-NEXT:    ori $a4, $zero, 5
 ; CHECK-NEXT:    ori $a6, $zero, 6
 ; CHECK-NEXT:    ori $a7, $zero, 7
 ; CHECK-NEXT:    move $a5, $zero
 ; CHECK-NEXT:    bl callee_many_scalars
 ; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i128 5, i64 6, i128 7, i64 8)
   ret i64 %1
 }
 
 ;; Check that i256 is passed indirectly.
 
 define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
 ; CHECK-LABEL: callee_large_scalars:

 ; CHECK-NEXT:    ld.d $a4, $a0, 16
 ; CHECK-NEXT:    xor $a3, $a4, $a3
 ; CHECK-NEXT:    ld.d $a1, $a1, 0
 ; CHECK-NEXT:    ld.d $a0, $a0, 0
 ; CHECK-NEXT:    xor $a0, $a0, $a1
 ; CHECK-NEXT:    or $a0, $a0, $a3
 ; CHECK-NEXT:    or $a0, $a0, $a2
 ; CHECK-NEXT:    sltui $a0, $a0, 1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = icmp eq i256 %a, %b
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @caller_large_scalars() nounwind {
 ; CHECK-LABEL: caller_large_scalars:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    st.d $zero, $sp, 40
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    st.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a1, $sp, 0
 ; CHECK-NEXT:    bl callee_large_scalars
 ; CHECK-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 80
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_large_scalars(i256 1, i256 2)
   ret i64 %1
 }
 
 ;; Check that arguments larger than 2*GRLen are handled correctly when their
 ;; address is passed on the stack rather than in memory.
 
 ;; Must keep define on a single line due to an update_llc_test_checks.py limitation

 ; CHECK-NEXT:    ld.d $a3, $a7, 16
 ; CHECK-NEXT:    xor $a2, $a3, $a2
 ; CHECK-NEXT:    ld.d $a0, $a0, 0
 ; CHECK-NEXT:    ld.d $a3, $a7, 0
 ; CHECK-NEXT:    xor $a0, $a3, $a0
 ; CHECK-NEXT:    or $a0, $a0, $a2
 ; CHECK-NEXT:    or $a0, $a0, $a1
 ; CHECK-NEXT:    sltui $a0, $a0, 1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = icmp eq i256 %h, %j
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @caller_large_scalars_exhausted_regs() nounwind {
 ; CHECK-LABEL: caller_large_scalars_exhausted_regs:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    ori $a3, $zero, 4
 ; CHECK-NEXT:    ori $a4, $zero, 5
 ; CHECK-NEXT:    ori $a5, $zero, 6
 ; CHECK-NEXT:    ori $a6, $zero, 7
 ; CHECK-NEXT:    addi.d $a7, $sp, 48
 ; CHECK-NEXT:    bl callee_large_scalars_exhausted_regs
 ; CHECK-NEXT:    ld.d $ra, $sp, 88 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 96
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_large_scalars_exhausted_regs(
       i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
       i256 10)
   ret i64 %1
 }
 
 ;; Check large struct arguments, which are passed byval
 
 %struct.large = type { i64, i64, i64, i64 }
 
 define i64 @callee_large_struct(ptr byval(%struct.large) align 8 %a) nounwind {
 ; CHECK-LABEL: callee_large_struct:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld.d $a1, $a0, 24
 ; CHECK-NEXT:    ld.d $a0, $a0, 0
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = getelementptr inbounds %struct.large, ptr %a, i64 0, i32 0
   %2 = getelementptr inbounds %struct.large, ptr %a, i64 0, i32 3
   %3 = load i64, ptr %1
   %4 = load i64, ptr %2
   %5 = add i64 %3, %4
   ret i64 %5
 }
 

 ; CHECK-NEXT:    st.d $a0, $sp, 24
 ; CHECK-NEXT:    ori $a0, $zero, 4
 ; CHECK-NEXT:    st.d $a0, $sp, 64
 ; CHECK-NEXT:    st.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a0, $sp, 8
 ; CHECK-NEXT:    bl callee_large_struct
 ; CHECK-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 80
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %ls = alloca %struct.large, align 8
   %a = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 0
   store i64 1, ptr %a
   %b = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 1
   store i64 2, ptr %b
   %c = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 2
   store i64 3, ptr %c
   %d = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 3
   store i64 4, ptr %d
   %1 = call i64 @callee_large_struct(ptr byval(%struct.large) align 8 %ls)
   ret i64 %1
 }
 
 ;; Check return scalar which size is 2*GRLen.
 
 define i128 @callee_small_scalar_ret() nounwind {
 ; CHECK-LABEL: callee_small_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a0, $zero, -1
 ; CHECK-NEXT:    move $a1, $a0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i128 -1
 }
 
 define i64 @caller_small_scalar_ret() nounwind {
 ; CHECK-LABEL: caller_small_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    bl callee_small_scalar_ret
 ; CHECK-NEXT:    addi.w $a2, $zero, -2
 ; CHECK-NEXT:    xor $a0, $a0, $a2
 ; CHECK-NEXT:    orn $a0, $a0, $a1
 ; CHECK-NEXT:    sltui $a0, $a0, 1
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i128 @callee_small_scalar_ret()
   %2 = icmp eq i128 -2, %1
   %3 = zext i1 %2 to i64
   ret i64 %3
 }
 
 ;; Check return struct which size is 2*GRLen.
 
 %struct.small = type { i64, ptr }
 
 define %struct.small @callee_small_struct_ret() nounwind {
 ; CHECK-LABEL: callee_small_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    move $a1, $zero
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret %struct.small { i64 1, ptr null }
 }
 
 define i64 @caller_small_struct_ret() nounwind {
 ; CHECK-LABEL: caller_small_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    bl callee_small_struct_ret
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call %struct.small @callee_small_struct_ret()
   %2 = extractvalue %struct.small %1, 0
   %3 = extractvalue %struct.small %1, 1
   %4 = ptrtoint ptr %3 to i64
   %5 = add i64 %2, %4
   ret i64 %5
 }
 
 ;; Check return scalar which size is more than 2*GRLen.
 
 define i256 @callee_large_scalar_ret() nounwind {
 ; CHECK-LABEL: callee_large_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a1, $zero, -1
 ; CHECK-NEXT:    st.d $a1, $a0, 24
 ; CHECK-NEXT:    st.d $a1, $a0, 16
 ; CHECK-NEXT:    st.d $a1, $a0, 8
 ; CHECK-NEXT:    lu12i.w $a1, -30141
 ; CHECK-NEXT:    ori $a1, $a1, 747
 ; CHECK-NEXT:    st.d $a1, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i256 -123456789
 }
 
 define void @caller_large_scalar_ret() nounwind {
 ; CHECK-LABEL: caller_large_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -48
 ; CHECK-NEXT:    st.d $ra, $sp, 40 # 8-byte Folded Spill
 ; CHECK-NEXT:    addi.d $a0, $sp, 0
 ; CHECK-NEXT:    bl callee_large_scalar_ret
 ; CHECK-NEXT:    ld.d $ra, $sp, 40 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 48
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i256 @callee_large_scalar_ret()
   ret void
 }
 
 ;; Check return struct which size is more than 2*GRLen.
 
 define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result) nounwind {
 ; CHECK-LABEL: callee_large_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a1, $zero, 4
 ; CHECK-NEXT:    st.w $a1, $a0, 24
 ; CHECK-NEXT:    ori $a1, $zero, 3
 ; CHECK-NEXT:    st.w $a1, $a0, 16
 ; CHECK-NEXT:    ori $a1, $zero, 2
 ; CHECK-NEXT:    st.w $a1, $a0, 8
 ; CHECK-NEXT:    st.w $zero, $a0, 28
 ; CHECK-NEXT:    st.w $zero, $a0, 20
 ; CHECK-NEXT:    st.w $zero, $a0, 12
 ; CHECK-NEXT:    st.w $zero, $a0, 4
 ; CHECK-NEXT:    ori $a1, $zero, 1
 ; CHECK-NEXT:    st.w $a1, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %a = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 0
   store i64 1, ptr %a, align 4
   %b = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 1
   store i64 2, ptr %b, align 4
   %c = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 2
   store i64 3, ptr %c, align 4
   %d = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 3
   store i64 4, ptr %d, align 4
   ret void
 }
 
 define i64 @caller_large_struct_ret() nounwind {
 ; CHECK-LABEL: caller_large_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -48
 ; CHECK-NEXT:    st.d $ra, $sp, 40 # 8-byte Folded Spill
 ; CHECK-NEXT:    addi.d $a0, $sp, 8
 ; CHECK-NEXT:    bl callee_large_struct_ret
 ; CHECK-NEXT:    ld.d $a0, $sp, 32
 ; CHECK-NEXT:    ld.d $a1, $sp, 8
 ; CHECK-NEXT:    add.d $a0, $a1, $a0
 ; CHECK-NEXT:    ld.d $ra, $sp, 40 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 48
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = alloca %struct.large
   call void @callee_large_struct_ret(ptr sret(%struct.large) %1)
   %2 = getelementptr inbounds %struct.large, ptr %1, i64 0, i32 0
   %3 = load i64, ptr %2
   %4 = getelementptr inbounds %struct.large, ptr %1, i64 0, i32 3
   %5 = load i64, ptr %4
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 ;; Check pass floating-point arguments whith FPRs.
 
 define i64 @callee_float_in_fpr(i64 %a, float %b, double %c) nounwind {
 ; CHECK-LABEL: callee_float_in_fpr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ftintrz.l.s $fa0, $fa0
 ; CHECK-NEXT:    movfr2gr.d $a1, $fa0
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
 ; CHECK-NEXT:    ftintrz.l.d $fa0, $fa1
 ; CHECK-NEXT:    movfr2gr.d $a1, $fa0
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %b_fptosi = fptosi float %b to i64
   %c_fptosi = fptosi double %c to i64
   %1 = add i64 %a, %b_fptosi
   %2 = add i64 %1, %c_fptosi
   ret i64 %2
 }
 
 define i64 @caller_float_in_fpr() nounwind {
 ; CHECK-LABEL: caller_float_in_fpr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    movgr2fr.w $fa0, $zero
 ; CHECK-NEXT:    movgr2fr.d $fa1, $zero
 ; CHECK-NEXT:    bl callee_float_in_fpr
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_float_in_fpr(i64 1, float 0.0, double 0.0)
   ret i64 %1
 }
 
 ;; Check that the GPR is used once the FPRs are exhausted.
 
 ;; Must keep define on a single line due to an update_llc_test_checks.py limitation.
 define i64 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {
 ; CHECK-LABEL: callee_double_in_gpr_exhausted_fprs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ftintrz.l.d $fa0, $fa7
 ; CHECK-NEXT:    movfr2gr.d $a1, $fa0
 ; CHECK-NEXT:    movgr2fr.d $fa0, $a0
 ; CHECK-NEXT:    ftintrz.l.d $fa0, $fa0
 ; CHECK-NEXT:    movfr2gr.d $a0, $fa0
 ; CHECK-NEXT:    add.d $a0, $a1, $a0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %h_fptosi = fptosi double %h to i64
   %i_fptosi = fptosi double %i to i64
   %1 = add i64 %h_fptosi, %i_fptosi
   ret i64 %1
 }
 
 define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
 ; CHECK-LABEL: caller_double_in_gpr_exhausted_fprs:

 ; CHECK-NEXT:    addi.d $a0, $a0, .LCPI21_6
 ; CHECK-NEXT:    fld.d $fa7, $a0, 0
 ; CHECK-NEXT:    ori $a0, $zero, 0
 ; CHECK-NEXT:    lu32i.d $a0, 131072
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 1026
 ; CHECK-NEXT:    bl callee_double_in_gpr_exhausted_fprs
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call i64 @callee_double_in_gpr_exhausted_fprs(
       double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
       double 7.0, double 8.0, double 9.0)
   ret i64 %1
 }
 
 ;; Check returning doubles.
 
 define double @callee_double_ret() nounwind {
 ; CHECK-LABEL: callee_double_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $a0, $zero, 1
 ; CHECK-NEXT:    movgr2fr.d $fa0, $a0
 ; CHECK-NEXT:    ffint.d.l $fa0, $fa0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret double 1.0
 }
 
 define i64 @caller_double_ret() nounwind {
 ; CHECK-LABEL: caller_double_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    bl callee_double_ret
 ; CHECK-NEXT:    movfr2gr.d $a0, $fa0
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = call double @callee_double_ret()
   %2 = bitcast double %1 to i64
   ret i64 %2
 }

llvm/test/CodeGen/LoongArch/double-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 define double @f64_positive_zero() nounwind {
 ; LA32-LABEL: f64_positive_zero:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $zero
 ; LA32-NEXT:    movgr2frh.w $fa0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_positive_zero:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret double 0.0
 }
 
 define double @f64_negative_zero() nounwind {
 ; LA32-LABEL: f64_negative_zero:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $zero
 ; LA32-NEXT:    movgr2frh.w $fa0, $zero
 ; LA32-NEXT:    fneg.d $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_negative_zero:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $zero
 ; LA64-NEXT:    fneg.d $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret double -0.0
 }
 
 define double @f64_constant_pi() nounwind {
 ; LA32-LABEL: f64_constant_pi:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
 ; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
 ; LA32-NEXT:    fld.d $fa0, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_constant_pi:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
 ; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
 ; LA64-NEXT:    fld.d $fa0, $a0, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret double 3.1415926535897931159979634685441851615905761718750
 }
 
 define double @f64_add_fimm1(double %a) nounwind {
 ; LA32-LABEL: f64_add_fimm1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $zero, 1
 ; LA32-NEXT:    movgr2fr.w $fa1, $a0
 ; LA32-NEXT:    ffint.s.w $fa1, $fa1
 ; LA32-NEXT:    fcvt.d.s $fa1, $fa1
 ; LA32-NEXT:    fadd.d $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_add_fimm1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $zero, 1
 ; LA64-NEXT:    movgr2fr.d $fa1, $a0
 ; LA64-NEXT:    ffint.d.l $fa1, $fa1
 ; LA64-NEXT:    fadd.d $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fadd double %a, 1.0
   ret double %1
 }
 
 define double @f64_positive_fimm1() nounwind {
 ; LA32-LABEL: f64_positive_fimm1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $zero, 1
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.s.w $fa0, $fa0
 ; LA32-NEXT:    fcvt.d.s $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_positive_fimm1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $zero, 1
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
 ; LA64-NEXT:    ffint.d.l $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret double 1.0
 }

llvm/test/CodeGen/LoongArch/float-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 define float @f32_positive_zero() nounwind {
 ; LA32-LABEL: f32_positive_zero:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_positive_zero:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret float 0.0
 }
 
 define float @f32_negative_zero() nounwind {
 ; LA32-LABEL: f32_negative_zero:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $zero
 ; LA32-NEXT:    fneg.s $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_negative_zero:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $zero
 ; LA64-NEXT:    fneg.s $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret float -0.0
 }
 
 define float @f32_constant_pi() nounwind {
 ; LA32-LABEL: f32_constant_pi:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
 ; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
 ; LA32-NEXT:    fld.s $fa0, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_constant_pi:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
 ; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
 ; LA64-NEXT:    fld.s $fa0, $a0, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @f32_add_fimm1(float %a) nounwind {
 ; LA32-LABEL: f32_add_fimm1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $zero, 1
 ; LA32-NEXT:    movgr2fr.w $fa1, $a0
 ; LA32-NEXT:    ffint.s.w $fa1, $fa1
 ; LA32-NEXT:    fadd.s $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_add_fimm1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a0, $zero, 1
 ; LA64-NEXT:    movgr2fr.w $fa1, $a0
 ; LA64-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64-NEXT:    fadd.s $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }
 
 define float @f32_positive_fimm1() nounwind {
 ; LA32-LABEL: f32_positive_fimm1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $zero, 1
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.s.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_positive_fimm1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a0, $zero, 1
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.s.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   ret float 1.0
 }

llvm/test/CodeGen/LoongArch/frame.ll

 ; CHECK-NEXT:    st.w $zero, $sp, 16
 ; CHECK-NEXT:    st.d $zero, $sp, 8
 ; CHECK-NEXT:    st.d $zero, $sp, 0
 ; CHECK-NEXT:    addi.d $a0, $sp, 4
 ; CHECK-NEXT:    bl test1
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %key = alloca %struct.key_t, align 4
   call void @llvm.memset.p0i8.i64(ptr %key, i8 0, i64 20, i1 false)
   %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
   call void @test1(ptr %1)
   ret i32 0
 }
 
 declare void @llvm.memset.p0i8.i64(ptr, i8, i64, i1)
 
 declare void @test1(ptr)

llvm/test/CodeGen/LoongArch/imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define i64 @imm0() {
 ; CHECK-LABEL: imm0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    move $a0, $zero
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 0
 }
 
 define i64 @imm7ff0000000000000() {
 ; CHECK-LABEL: imm7ff0000000000000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu52i.d $a0, $zero, 2047
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 9218868437227405312
 }
 
 define i64 @imm0000000000000fff() {
 ; CHECK-LABEL: imm0000000000000fff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a0, $zero, 4095
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 4095
 }
 
 define i64 @imm0007ffff00000800() {
 ; CHECK-LABEL: imm0007ffff00000800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a0, $zero, 2048
 ; CHECK-NEXT:    lu32i.d $a0, 524287
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2251795518720000
 }
 
 define i64 @immfff0000000000fff() {
 ; CHECK-LABEL: immfff0000000000fff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a0, $zero, 4095
 ; CHECK-NEXT:    lu52i.d $a0, $a0, -1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 -4503599627366401
 }
 
 define i64 @imm0008000000000fff() {
 ; CHECK-LABEL: imm0008000000000fff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a0, $zero, 4095
 ; CHECK-NEXT:    lu32i.d $a0, -524288
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2251799813689343
 }
 
 define i64 @immfffffffffffff800() {
 ; CHECK-LABEL: immfffffffffffff800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a0, $zero, -2048
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 -2048
 }
 
 define i64 @imm00000000fffff800() {
 ; CHECK-LABEL: imm00000000fffff800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a0, $zero, -2048
 ; CHECK-NEXT:    lu32i.d $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 4294965248
 }
 
 define i64 @imm000ffffffffff800() {
 ; CHECK-LABEL: imm000ffffffffff800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a0, $zero, -2048
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 4503599627368448
 }
 
 define i64 @imm00080000fffff800() {
 ; CHECK-LABEL: imm00080000fffff800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $a0, $zero, -2048
 ; CHECK-NEXT:    lu32i.d $a0, -524288
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2251804108650496
 }
 
 define i64 @imm000000007ffff000() {
 ; CHECK-LABEL: imm000000007ffff000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, 524287
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2147479552
 }
 
 define i64 @imm0000000080000000() {
 ; CHECK-LABEL: imm0000000080000000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    lu32i.d $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2147483648
 }
 
 define i64 @imm000ffffffffff000() {
 ; CHECK-LABEL: imm000ffffffffff000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -1
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 4503599627366400
 }
 
 define i64 @imm7ff0000080000000() {
 ; CHECK-LABEL: imm7ff0000080000000:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    lu32i.d $a0, 0
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 2047
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 9218868439374888960
 }
 
 define i64 @immffffffff80000800() {
 ; CHECK-LABEL: immffffffff80000800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    ori $a0, $a0, 2048
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 -2147481600
 }
 
 define i64 @immffffffff7ffff800() {
 ; CHECK-LABEL: immffffffff7ffff800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, 524287
 ; CHECK-NEXT:    ori $a0, $a0, 2048
 ; CHECK-NEXT:    lu32i.d $a0, -1
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 -2147485696
 }
 
 define i64 @imm7fffffff800007ff() {
 ; CHECK-LABEL: imm7fffffff800007ff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    ori $a0, $a0, 2047
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 2047
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 9223372034707294207
 }
 
 define i64 @imm0008000080000800() {
 ; CHECK-LABEL: imm0008000080000800:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lu12i.w $a0, -524288
 ; CHECK-NEXT:    ori $a0, $a0, 2048
 ; CHECK-NEXT:    lu32i.d $a0, -524288
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 0
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   ret i64 2251801961170944
 }

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'add' LLVM IR: https://llvm.org/docs/LangRef.html#add-instruction
 
 define i1 @add_i1(i1 %x, i1 %y) {
 ; LA32-LABEL: add_i1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i1 %x, %y
   ret i1 %add
 }
 
 define i8 @add_i8(i8 %x, i8 %y) {
 ; LA32-LABEL: add_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i8 %x, %y
   ret i8 %add
 }
 
 define i16 @add_i16(i16 %x, i16 %y) {
 ; LA32-LABEL: add_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i16 %x, %y
   ret i16 %add
 }
 
 define i32 @add_i32(i32 %x, i32 %y) {
 ; LA32-LABEL: add_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i32 %x, %y
   ret i32 %add
 }
 
 ;; Match the pattern:
 ;; def : PatGprGpr_32<add, ADD_W>;
 define signext i32 @add_i32_sext(i32 %x, i32 %y) {
 ; LA32-LABEL: add_i32_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_sext:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i32 %x, %y
   ret i32 %add
 }
 
 define i64 @add_i64(i64 %x, i64 %y) {
 ; LA32-LABEL: add_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a1, $a1, $a3
 ; LA32-NEXT:    add.w $a2, $a0, $a2
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i64 %x, %y
   ret i64 %add
 }
 
 define i1 @add_i1_3(i1 %x) {
 ; LA32-LABEL: add_i1_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i1_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i1 %x, 3
   ret i1 %add
 }
 
 define i8 @add_i8_3(i8 %x) {
 ; LA32-LABEL: add_i8_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i8_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i8 %x, 3
   ret i8 %add
 }
 
 define i16 @add_i16_3(i16 %x) {
 ; LA32-LABEL: add_i16_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i16_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i16 %x, 3
   ret i16 %add
 }
 
 define i32 @add_i32_3(i32 %x) {
 ; LA32-LABEL: add_i32_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i32 %x, 3
   ret i32 %add
 }
 
 ;; Match the pattern:
 ;; def : PatGprImm_32<add, ADDI_W, simm12>;
 define signext i32 @add_i32_3_sext(i32 %x) {
 ; LA32-LABEL: add_i32_3_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_3_sext:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i32 %x, 3
   ret i32 %add
 }
 
 define i64 @add_i64_3(i64 %x) {
 ; LA32-LABEL: add_i64_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a2, $a0, 3
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = add i64 %x, 3
   ret i64 %add
 }

llvm/test/CodeGen/LoongArch/ir-instruction/and.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'and' LLVM IR: https://llvm.org/docs/LangRef.html#and-instruction
 
 define i1 @and_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: and_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i1 %a, %b
   ret i1 %r
 }
 
 define i8 @and_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: and_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i8 %a, %b
   ret i8 %r
 }
 
 define i16 @and_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: and_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i16 %a, %b
   ret i16 %r
 }
 
 define i32 @and_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: and_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i32 %a, %b
   ret i32 %r
 }
 
 define i64 @and_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: and_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    and $a0, $a0, $a2
 ; LA32-NEXT:    and $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i64 %a, %b
   ret i64 %r
 }
 
 define i1 @and_i1_0(i1 %b) {
 ; LA32-LABEL: and_i1_0:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    move $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i1_0:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    move $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i1 4, %b
   ret i1 %r
 }
 
 define i1 @and_i1_5(i1 %b) {
 ; LA32-LABEL: and_i1_5:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i1_5:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i1 5, %b
   ret i1 %r
 }
 
 define i8 @and_i8_5(i8 %b) {
 ; LA32-LABEL: and_i8_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i8_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i8 5, %b
   ret i8 %r
 }
 
 define i8 @and_i8_257(i8 %b) {
 ; LA32-LABEL: and_i8_257:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i8_257:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i8 257, %b
   ret i8 %r
 }
 
 define i16 @and_i16_5(i16 %b) {
 ; LA32-LABEL: and_i16_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i16_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i16 5, %b
   ret i16 %r
 }
 
 define i16 @and_i16_0x1000(i16 %b) {
 ; LA32-LABEL: and_i16_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i16_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i16 4096, %b
   ret i16 %r
 }
 
 define i16 @and_i16_0x10001(i16 %b) {
 ; LA32-LABEL: and_i16_0x10001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i16_0x10001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i16 65537, %b
   ret i16 %r
 }
 
 define i32 @and_i32_5(i32 %b) {
 ; LA32-LABEL: and_i32_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i32_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i32 5, %b
   ret i32 %r
 }
 
 define i32 @and_i32_0x1000(i32 %b) {
 ; LA32-LABEL: and_i32_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    and $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i32_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i32 4096, %b
   ret i32 %r
 }
 
 define i32 @and_i32_0x100000001(i32 %b) {
 ; LA32-LABEL: and_i32_0x100000001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i32_0x100000001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i32 4294967297, %b
   ret i32 %r
 }
 
 define i64 @and_i64_5(i64 %b) {
 ; LA32-LABEL: and_i64_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a0, $a0, 5
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i64_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i64 5, %b
   ret i64 %r
 }
 
 define i64 @and_i64_0x1000(i64 %b) {
 ; LA32-LABEL: and_i64_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    and $a0, $a0, $a1
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_i64_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    and $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = and i64 4096, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'ashr' LLVM IR: https://llvm.org/docs/LangRef.html#ashr-instruction
 
 define i1 @ashr_i1(i1 %x, i1 %y) {
 ; LA32-LABEL: ashr_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i1 %x, %y
   ret i1 %ashr
 }
 
 define i8 @ashr_i8(i8 %x, i8 %y) {
 ; LA32-LABEL: ashr_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.b $a0, $a0
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.b $a0, $a0
 ; LA64-NEXT:    sra.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i8 %x, %y
   ret i8 %ashr
 }
 
 define i16 @ashr_i16(i16 %x, i16 %y) {
 ; LA32-LABEL: ashr_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.h $a0, $a0
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.h $a0, $a0
 ; LA64-NEXT:    sra.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i16 %x, %y
   ret i16 %ashr
 }
 
 define i32 @ashr_i32(i32 %x, i32 %y) {
 ; LA32-LABEL: ashr_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sra.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i32 %x, %y
   ret i32 %ashr
 }
 
 define i64 @ashr_i64(i64 %x, i64 %y) {
 ; LA32-LABEL: ashr_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srai.w $a3, $a1, 31
 ; LA32-NEXT:    addi.w $a4, $a2, -32
 ; LA32-NEXT:    slti $a5, $a4, 0
 ; LA32-NEXT:    masknez $a3, $a3, $a5
 ; LA32-NEXT:    sra.w $a6, $a1, $a2
 ; LA32-NEXT:    maskeqz $a6, $a6, $a5
 ; LA32-NEXT:    or $a3, $a6, $a3
 ; LA32-NEXT:    srl.w $a0, $a0, $a2
 ; LA32-NEXT:    xori $a2, $a2, 31
 ; LA32-NEXT:    slli.w $a6, $a1, 1
 ; LA32-NEXT:    sll.w $a2, $a6, $a2
 ; LA32-NEXT:    or $a0, $a0, $a2
 ; LA32-NEXT:    sra.w $a1, $a1, $a4
 ; LA32-NEXT:    maskeqz $a0, $a0, $a5
 ; LA32-NEXT:    masknez $a1, $a1, $a5
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    move $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sra.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i64 %x, %y
   ret i64 %ashr
 }
 
 define i1 @ashr_i1_3(i1 %x) {
 ; LA32-LABEL: ashr_i1_3:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i1_3:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i1 %x, 3
   ret i1 %ashr
 }
 
 define i8 @ashr_i8_3(i8 %x) {
 ; LA32-LABEL: ashr_i8_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.b $a0, $a0
 ; LA32-NEXT:    srai.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i8_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.b $a0, $a0
 ; LA64-NEXT:    srai.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i8 %x, 3
   ret i8 %ashr
 }
 
 define i16 @ashr_i16_3(i16 %x) {
 ; LA32-LABEL: ashr_i16_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.h $a0, $a0
 ; LA32-NEXT:    srai.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i16_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.h $a0, $a0
 ; LA64-NEXT:    srai.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i16 %x, 3
   ret i16 %ashr
 }
 
 define i32 @ashr_i32_3(i32 %x) {
 ; LA32-LABEL: ashr_i32_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srai.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i32_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    srai.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i32 %x, 3
   ret i32 %ashr
 }
 
 define i64 @ashr_i64_3(i64 %x) {
 ; LA32-LABEL: ashr_i64_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srli.w $a0, $a0, 3
 ; LA32-NEXT:    slli.w $a2, $a1, 29
 ; LA32-NEXT:    or $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a1, $a1, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ashr_i64_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srai.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %ashr = ashr i64 %x, 3
   ret i64 %ashr
 }

llvm/test/CodeGen/LoongArch/ir-instruction/br.ll

 define void @foo_br_eq(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_eq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    beq $a2, $a0, .LBB1_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB1_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_eq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    beq $a2, $a0, .LBB1_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB1_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp eq i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_ne(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_ne:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bne $a2, $a0, .LBB2_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB2_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ne:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    bne $a2, $a0, .LBB2_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB2_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ne i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_slt(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_slt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    blt $a2, $a0, .LBB3_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB3_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_slt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a2, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    blt $a2, $a0, .LBB3_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB3_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp slt i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_sge(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_sge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bge $a2, $a0, .LBB4_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB4_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_sge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a2, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bge $a2, $a0, .LBB4_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB4_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp sge i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_ult(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bltu $a2, $a0, .LBB5_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB5_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    bltu $a2, $a0, .LBB5_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB5_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ult i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_uge(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bgeu $a2, $a0, .LBB6_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB6_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    bgeu $a2, $a0, .LBB6_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB6_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp uge i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 ;; Check for condition codes that don't have a matching instruction.
 define void @foo_br_sgt(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_sgt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    blt $a0, $a2, .LBB7_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB7_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_sgt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a2, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    blt $a0, $a2, .LBB7_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB7_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp sgt i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_sle(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_sle:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bge $a0, $a2, .LBB8_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB8_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_sle:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a2, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bge $a0, $a2, .LBB8_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB8_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp sle i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_ugt(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bltu $a0, $a2, .LBB9_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB9_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    bltu $a0, $a2, .LBB9_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB9_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ugt i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 define void @foo_br_ule(i32 %a, ptr %b) nounwind {
 ; LA32-LABEL: foo_br_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    bgeu $a0, $a2, .LBB10_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB10_2: # %end
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a2, $a1, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    bgeu $a0, $a2, .LBB10_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB10_2: # %end
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ule i32 %val, %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %b
   br label %end
 
 end:
   ret void
 }
 
 ;; Check the case of a branch where the condition was generated in another
 ;; function.
 define void @foo_br_cc(ptr %a, i1 %cc) nounwind {
 ; ALL-LABEL: foo_br_cc:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    ld.w $a2, $a0, 0
 ; ALL-NEXT:    andi $a1, $a1, 1
 ; ALL-NEXT:    bnez $a1, .LBB11_2
 ; ALL-NEXT:  # %bb.1: # %test
 ; ALL-NEXT:    ld.w $a0, $a0, 0
 ; ALL-NEXT:  .LBB11_2: # %end
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   %val = load volatile i32, ptr %a
   br i1 %cc, label %end, label %test
 test:
   %tmp = load volatile i32, ptr %a
   br label %end
 
 end:
   ret void
 }

llvm/test/CodeGen/LoongArch/ir-instruction/call.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck --check-prefix=LA32 %s
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck --check-prefix=LA64 %s
 
 declare i32 @external_function(i32)
 
 define i32 @test_call_external(i32 %a) nounwind {
 ; LA32-LABEL: test_call_external:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl external_function
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_call_external:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    bl external_function
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = call i32 @external_function(i32 %a)
   ret i32 %1
 }
 
 define i32 @defined_function(i32 %a) nounwind {
 ; LA32-LABEL: defined_function:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: defined_function:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = add i32 %a, 1
   ret i32 %1
 }
 
 define i32 @test_call_defined(i32 %a) nounwind {
 ; LA32-LABEL: test_call_defined:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl defined_function
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_call_defined:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    bl defined_function
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = call i32 @defined_function(i32 %a) nounwind
   ret i32 %1
 }
 
 define i32 @test_call_indirect(ptr %a, i32 %b) nounwind {
 ; LA32-LABEL: test_call_indirect:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    move $a2, $a0
 ; LA32-NEXT:    move $a0, $a1
 ; LA32-NEXT:    jirl $ra, $a2, 0
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_call_indirect:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    move $a2, $a0
 ; LA64-NEXT:    move $a0, $a1
 ; LA64-NEXT:    jirl $ra, $a2, 0
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = call i32 %a(i32 %b)
   ret i32 %1
 }

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 define float @convert_double_to_float(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_float:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcvt.s.d $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_float:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcvt.s.d $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fptrunc double %a to float
   ret float %1
 }
 
 define double @convert_float_to_double(float %a) nounwind {
 ; LA32-LABEL: convert_float_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcvt.d.s $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_float_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcvt.d.s $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fpext float %a to double
   ret double %1
 }
 
 define double @convert_i8_to_double(i8 signext %a) nounwind {
 ; LA32-LABEL: convert_i8_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.d.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_i8_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.d.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sitofp i8 %a to double
   ret double %1
 }
 
 define double @convert_i16_to_double(i16 signext %a) nounwind {
 ; LA32-LABEL: convert_i16_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.d.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_i16_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.d.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sitofp i16 %a to double
   ret double %1
 }
 
 define double @convert_i32_to_double(i32 %a) nounwind {
 ; LA32-LABEL: convert_i32_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.d.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_i32_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.d.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sitofp i32 %a to double
   ret double %1
 }
 
 define double @convert_i64_to_double(i64 %a) nounwind {
 ; LA32-LABEL: convert_i64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl __floatdidf
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_i64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
 ; LA64-NEXT:    ffint.d.l $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sitofp i64 %a to double
   ret double %1
 }
 
 define i32 @convert_double_to_i32(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ftintrz.w.d $fa0, $fa0
 ; LA32-NEXT:    movfr2gr.s $a0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.w.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.s $a0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
 
 define i32 @convert_double_to_u32(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_u32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    pcalau12i $a0, .LCPI7_0
 ; LA32-NEXT:    addi.w $a0, $a0, .LCPI7_0
 ; LA32-NEXT:    fld.d $fa1, $a0, 0
 ; LA32-NEXT:    fsub.d $fa2, $fa0, $fa1
 ; LA32-NEXT:    ftintrz.w.d $fa2, $fa2
 ; LA32-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32-NEXT:    lu12i.w $a1, -524288
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a1, $fcc0
 ; LA32-NEXT:    masknez $a0, $a0, $a1
 ; LA32-NEXT:    ftintrz.w.d $fa0, $fa0
 ; LA32-NEXT:    movfr2gr.s $a2, $fa0
 ; LA32-NEXT:    maskeqz $a1, $a2, $a1
 ; LA32-NEXT:    or $a0, $a1, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_u32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fptoui double %a to i32
   ret i32 %1
 }
 
 define i64 @convert_double_to_i64(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl __fixdfdi
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fptosi double %a to i64
   ret i64 %1
 }
 
 define i64 @convert_double_to_u64(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_u64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl __fixunsdfdi
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_u64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    pcalau12i $a0, .LCPI9_0
 ; LA64-NEXT:    addi.d $a0, $a0, .LCPI9_0
 ; LA64-NEXT:    fld.d $fa1, $a0, 0
 ; LA64-NEXT:    fsub.d $fa2, $fa0, $fa1
 ; LA64-NEXT:    ftintrz.l.d $fa2, $fa2
 ; LA64-NEXT:    movfr2gr.d $a0, $fa2
 ; LA64-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a1, $fcc0
 ; LA64-NEXT:    masknez $a0, $a0, $a1
 ; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.d $a2, $fa0
 ; LA64-NEXT:    maskeqz $a1, $a2, $a1
 ; LA64-NEXT:    or $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = fptoui double %a to i64
   ret i64 %1
 }
 
 define double @convert_u8_to_double(i8 zeroext %a) nounwind {
 ; LA32-LABEL: convert_u8_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.d.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u8_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.d.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = uitofp i8 %a to double
   ret double %1
 }
 
 define double @convert_u16_to_double(i16 zeroext %a) nounwind {
 ; LA32-LABEL: convert_u16_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.d.w $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u16_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.d.w $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = uitofp i16 %a to double
   ret double %1
 }
 
 define double @convert_u32_to_double(i32 %a) nounwind {
 ; LA32-LABEL: convert_u32_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    lu12i.w $a1, 275200
 ; LA32-NEXT:    st.w $a1, $sp, 12
 ; LA32-NEXT:    st.w $a0, $sp, 8
 ; LA32-NEXT:    pcalau12i $a0, .LCPI12_0
 ; LA32-NEXT:    addi.w $a0, $a0, .LCPI12_0
 ; LA32-NEXT:    fld.d $fa0, $a0, 0
 ; LA32-NEXT:    fld.d $fa1, $sp, 8
 ; LA32-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u32_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    lu52i.d $a1, $zero, 1107
 ; LA64-NEXT:    movgr2fr.d $fa0, $a1
 ; LA64-NEXT:    pcalau12i $a1, .LCPI12_0
 ; LA64-NEXT:    addi.d $a1, $a1, .LCPI12_0
 ; LA64-NEXT:    fld.d $fa1, $a1, 0
 ; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
 ; LA64-NEXT:    lu12i.w $a1, 275200
 ; LA64-NEXT:    bstrins.d $a0, $a1, 63, 32
 ; LA64-NEXT:    movgr2fr.d $fa1, $a0
 ; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = uitofp i32 %a to double
   ret double %1
 }
 
 define double @convert_u64_to_double(i64 %a) nounwind {
 ; LA32-LABEL: convert_u64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl __floatundidf
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srli.d $a1, $a0, 32
 ; LA64-NEXT:    lu52i.d $a2, $zero, 1107
 ; LA64-NEXT:    or $a1, $a1, $a2
 ; LA64-NEXT:    movgr2fr.d $fa0, $a1
 ; LA64-NEXT:    pcalau12i $a1, .LCPI13_0
 ; LA64-NEXT:    addi.d $a1, $a1, .LCPI13_0
 ; LA64-NEXT:    fld.d $fa1, $a1, 0
 ; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
 ; LA64-NEXT:    lu12i.w $a1, 275200
 ; LA64-NEXT:    bstrins.d $a0, $a1, 63, 32
 ; LA64-NEXT:    movgr2fr.d $fa1, $a0
 ; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = uitofp i64 %a to double
   ret double %1
 }
 
 define double @bitcast_i64_to_double(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: bitcast_i64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $a1, $sp, 12
 ; LA32-NEXT:    st.w $a0, $sp, 8
 ; LA32-NEXT:    fld.d $fa0, $sp, 8
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bitcast_i64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = bitcast i64 %a to double
   ret double %1
 }
 
 define i64 @bitcast_double_to_i64(double %a) nounwind {
 ; LA32-LABEL: bitcast_double_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    fst.d $fa0, $sp, 8
 ; LA32-NEXT:    ld.w $a0, $sp, 8
 ; LA32-NEXT:    ld.w $a1, $sp, 12
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bitcast_double_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = bitcast double %a to i64
   ret i64 %1
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fadd.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'fadd' LLVM IR: https://llvm.org/docs/LangRef.html#fadd-instruction
 
 define float @fadd_s(float %x, float %y) {
 ; LA32-LABEL: fadd_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fadd.s $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fadd_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fadd.s $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = fadd float %x, %y
   ret float %add
 }
 
 define double @fadd_d(double %x, double %y) {
 ; LA32-LABEL: fadd_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fadd.d $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fadd_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fadd.d $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %add = fadd double %x, %y
   ret double %add
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the 'fcmp' LLVM IR: https://llvm.org/docs/LangRef.html#fcmp-instruction
 ;; over double values.
 
 define i1 @fcmp_false(double %a, double %b) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    move $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oeq(double %a, double %b) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ogt(double %a, double %b) {
 ; LA32-LABEL: fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oge(double %a, double %b) {
 ; LA32-LABEL: fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_olt(double %a, double %b) {
 ; LA32-LABEL: fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ole(double %a, double %b) {
 ; LA32-LABEL: fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_one(double %a, double %b) {
 ; LA32-LABEL: fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ord(double %a, double %b) {
 ; LA32-LABEL: fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ueq(double %a, double %b) {
 ; LA32-LABEL: fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ugt(double %a, double %b) {
 ; LA32-LABEL: fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_uge(double %a, double %b) {
 ; LA32-LABEL: fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ult(double %a, double %b) {
 ; LA32-LABEL: fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ule(double %a, double %b) {
 ; LA32-LABEL: fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_une(double %a, double %b) {
 ; LA32-LABEL: fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_uno(double %a, double %b) {
 ; LA32-LABEL: fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno double %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_true(double %a, double %b) {
 ; LA32-LABEL: fcmp_true:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ori $a0, $zero, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_true:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ori $a0, $zero, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true double %a, %b
   ret i1 %cmp
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the 'fcmp' LLVM IR: https://llvm.org/docs/LangRef.html#fcmp-instruction
 ;; over float values.
 
 define i1 @fcmp_false(float %a, float %b) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    move $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oeq(float %a, float %b) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ogt(float %a, float %b) {
 ; LA32-LABEL: fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_oge(float %a, float %b) {
 ; LA32-LABEL: fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_olt(float %a, float %b) {
 ; LA32-LABEL: fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ole(float %a, float %b) {
 ; LA32-LABEL: fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_one(float %a, float %b) {
 ; LA32-LABEL: fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ord(float %a, float %b) {
 ; LA32-LABEL: fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ueq(float %a, float %b) {
 ; LA32-LABEL: fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ugt(float %a, float %b) {
 ; LA32-LABEL: fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_uge(float %a, float %b) {
 ; LA32-LABEL: fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ult(float %a, float %b) {
 ; LA32-LABEL: fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_ule(float %a, float %b) {
 ; LA32-LABEL: fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_une(float %a, float %b) {
 ; LA32-LABEL: fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_uno(float %a, float %b) {
 ; LA32-LABEL: fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno float %a, %b
   ret i1 %cmp
 }
 
 define i1 @fcmp_true(float %a, float %b) {
 ; LA32-LABEL: fcmp_true:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ori $a0, $zero, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_true:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ori $a0, $zero, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true float %a, %b
   ret i1 %cmp
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fdiv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'fdiv' LLVM IR: https://llvm.org/docs/LangRef.html#fdiv-instruction
 
 define float @fdiv_s(float %x, float %y) {
 ; LA32-LABEL: fdiv_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fdiv.s $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fdiv_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fdiv.s $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %div = fdiv float %x, %y
   ret float %div
 }
 
 define double @fdiv_d(double %x, double %y) {
 ; LA32-LABEL: fdiv_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fdiv.d $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fdiv_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fdiv.d $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %div = fdiv double %x, %y
   ret double %div
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fence.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 define void @fence_acquire() nounwind {
 ; LA32-LABEL: fence_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fence_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   fence acquire
   ret void
 }
 
 define void @fence_release() nounwind {
 ; LA32-LABEL: fence_release:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fence_release:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   fence release
   ret void
 }
 
 define void @fence_acq_rel() nounwind {
 ; LA32-LABEL: fence_acq_rel:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fence_acq_rel:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   fence acq_rel
   ret void
 }
 
 define void @fence_seq_cst() nounwind {
 ; LA32-LABEL: fence_seq_cst:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fence_seq_cst:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   fence seq_cst
   ret void
 }

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32F
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32D
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64F
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64D
 
 define signext i8 @convert_float_to_i8(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_i8:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_i8:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_i8:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_i8:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptosi float %a to i8
   ret i8 %1
 }
 
 define signext i16 @convert_float_to_i16(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_i16:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_i16:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_i16:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_i16:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptosi float %a to i16
   ret i16 %1
 }
 
 define i32 @convert_float_to_i32(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_i32:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_i32:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_i32:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_i32:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.s $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
 }
 
 define i64 @convert_float_to_i64(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_i64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32F-NEXT:    bl __fixsfdi
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_i64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl __fixsfdi
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_i64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_i64:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptosi float %a to i64
   ret i64 %1
 }
 
 define zeroext i8 @convert_float_to_u8(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u8:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u8:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u8:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_u8:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptoui float %a to i8
   ret i8 %1
 }
 
 define zeroext i16 @convert_float_to_u16(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u16:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u16:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u16:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_u16:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptoui float %a to i16
   ret i16 %1
 }
 
 define i32 @convert_float_to_u32(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u32:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    pcalau12i $a0, .LCPI6_0
 ; LA32F-NEXT:    addi.w $a0, $a0, .LCPI6_0
 ; LA32F-NEXT:    fld.s $fa1, $a0, 0
 ; LA32F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA32F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32F-NEXT:    lu12i.w $a1, -524288
 ; LA32F-NEXT:    xor $a0, $a0, $a1
 ; LA32F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32F-NEXT:    movcf2gr $a1, $fcc0
 ; LA32F-NEXT:    masknez $a0, $a0, $a1
 ; LA32F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA32F-NEXT:    maskeqz $a1, $a2, $a1
 ; LA32F-NEXT:    or $a0, $a1, $a0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u32:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    pcalau12i $a0, .LCPI6_0
 ; LA32D-NEXT:    addi.w $a0, $a0, .LCPI6_0
 ; LA32D-NEXT:    fld.s $fa1, $a0, 0
 ; LA32D-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA32D-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa2
 ; LA32D-NEXT:    lu12i.w $a1, -524288
 ; LA32D-NEXT:    xor $a0, $a0, $a1
 ; LA32D-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32D-NEXT:    movcf2gr $a1, $fcc0
 ; LA32D-NEXT:    masknez $a0, $a0, $a1
 ; LA32D-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA32D-NEXT:    movfr2gr.s $a2, $fa0
 ; LA32D-NEXT:    maskeqz $a1, $a2, $a1
 ; LA32D-NEXT:    or $a0, $a1, $a0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u32:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    pcalau12i $a0, .LCPI6_0
 ; LA64F-NEXT:    addi.d $a0, $a0, .LCPI6_0
 ; LA64F-NEXT:    fld.s $fa1, $a0, 0
 ; LA64F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA64F-NEXT:    lu12i.w $a1, -524288
 ; LA64F-NEXT:    xor $a0, $a0, $a1
 ; LA64F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64F-NEXT:    movcf2gr $a1, $fcc0
 ; LA64F-NEXT:    masknez $a0, $a0, $a1
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:    maskeqz $a1, $a2, $a1
 ; LA64F-NEXT:    or $a0, $a1, $a0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_u32:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptoui float %a to i32
   ret i32 %1
 }
 
 define i64 @convert_float_to_u64(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32F-NEXT:    bl __fixunssfdi
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl __fixunssfdi
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    pcalau12i $a0, .LCPI7_0
 ; LA64F-NEXT:    addi.d $a0, $a0, .LCPI7_0
 ; LA64F-NEXT:    fld.s $fa1, $a0, 0
 ; LA64F-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64F-NEXT:    ftintrz.w.s $fa2, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa2
 ; LA64F-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64F-NEXT:    xor $a0, $a0, $a1
 ; LA64F-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64F-NEXT:    movcf2gr $a1, $fcc0
 ; LA64F-NEXT:    masknez $a0, $a0, $a1
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:    maskeqz $a1, $a2, $a1
 ; LA64F-NEXT:    or $a0, $a1, $a0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_float_to_u64:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    pcalau12i $a0, .LCPI7_0
 ; LA64D-NEXT:    addi.d $a0, $a0, .LCPI7_0
 ; LA64D-NEXT:    fld.s $fa1, $a0, 0
 ; LA64D-NEXT:    fsub.s $fa2, $fa0, $fa1
 ; LA64D-NEXT:    ftintrz.l.s $fa2, $fa2
 ; LA64D-NEXT:    movfr2gr.d $a0, $fa2
 ; LA64D-NEXT:    lu52i.d $a1, $zero, -2048
 ; LA64D-NEXT:    xor $a0, $a0, $a1
 ; LA64D-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64D-NEXT:    movcf2gr $a1, $fcc0
 ; LA64D-NEXT:    masknez $a0, $a0, $a1
 ; LA64D-NEXT:    ftintrz.l.s $fa0, $fa0
 ; LA64D-NEXT:    movfr2gr.d $a2, $fa0
 ; LA64D-NEXT:    maskeqz $a1, $a2, $a1
 ; LA64D-NEXT:    or $a0, $a1, $a0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = fptoui float %a to i64
   ret i64 %1
 }
 
 define float @convert_i8_to_float(i8 signext %a) nounwind {
 ; LA32F-LABEL: convert_i8_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_i8_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i8_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i8_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = sitofp i8 %a to float
   ret float %1
 }
 
 define float @convert_i16_to_float(i16 signext %a) nounwind {
 ; LA32F-LABEL: convert_i16_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_i16_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i16_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i16_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = sitofp i16 %a to float
   ret float %1
 }
 
 define float @convert_i32_to_float(i32 %a) nounwind {
 ; LA32F-LABEL: convert_i32_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_i32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i32_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    addi.w $a0, $a0, 0
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i32_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    addi.w $a0, $a0, 0
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @convert_i64_to_float(i64 %a) nounwind {
 ; LA32F-LABEL: convert_i64_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32F-NEXT:    bl __floatdisf
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_i64_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl __floatdisf
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i64_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_i64_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = sitofp i64 %a to float
   ret float %1
 }
 
 define float @convert_u8_to_float(i8 zeroext %a) nounwind {
 ; LA32F-LABEL: convert_u8_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u8_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u8_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u8_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = uitofp i8 %a to float
   ret float %1
 }
 
 define float @convert_u16_to_float(i16 zeroext %a) nounwind {
 ; LA32F-LABEL: convert_u16_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u16_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32D-NEXT:    ffint.s.w $fa0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u16_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u16_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = uitofp i16 %a to float
   ret float %1
 }
 
 define float @convert_u32_to_float(i32 %a) nounwind {
 ; LA32F-LABEL: convert_u32_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    srli.w $a1, $a0, 1
 ; LA32F-NEXT:    andi $a2, $a0, 1
 ; LA32F-NEXT:    or $a1, $a2, $a1
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a1
 ; LA32F-NEXT:    ffint.s.w $fa0, $fa0
 ; LA32F-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA32F-NEXT:    slti $a1, $a0, 0
 ; LA32F-NEXT:    movgr2cf $fcc0, $a1
 ; LA32F-NEXT:    movgr2fr.w $fa1, $a0
 ; LA32F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA32F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    lu12i.w $a1, 275200
 ; LA32D-NEXT:    st.w $a1, $sp, 12
 ; LA32D-NEXT:    st.w $a0, $sp, 8
 ; LA32D-NEXT:    pcalau12i $a0, .LCPI14_0
 ; LA32D-NEXT:    addi.w $a0, $a0, .LCPI14_0
 ; LA32D-NEXT:    fld.d $fa0, $a0, 0
 ; LA32D-NEXT:    fld.d $fa1, $sp, 8
 ; LA32D-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32D-NEXT:    fcvt.s.d $fa0, $fa0
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u32_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    bstrpick.d $a1, $a0, 31, 1
 ; LA64F-NEXT:    andi $a2, $a0, 1
 ; LA64F-NEXT:    or $a1, $a2, $a1
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a1
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64F-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64F-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64F-NEXT:    slti $a1, $a0, 0
 ; LA64F-NEXT:    movgr2cf $fcc0, $a1
 ; LA64F-NEXT:    movgr2fr.w $fa1, $a0
 ; LA64F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u32_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    bstrpick.d $a1, $a0, 31, 1
 ; LA64D-NEXT:    andi $a2, $a0, 1
 ; LA64D-NEXT:    or $a1, $a2, $a1
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a1
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64D-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64D-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64D-NEXT:    slti $a1, $a0, 0
 ; LA64D-NEXT:    movgr2cf $fcc0, $a1
 ; LA64D-NEXT:    movgr2fr.w $fa1, $a0
 ; LA64D-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64D-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @convert_u64_to_float(i64 %a) nounwind {
 ; LA32F-LABEL: convert_u64_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32F-NEXT:    bl __floatundisf
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u64_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32D-NEXT:    bl __floatundisf
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u64_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    srli.d $a1, $a0, 1
 ; LA64F-NEXT:    andi $a2, $a0, 1
 ; LA64F-NEXT:    or $a1, $a2, $a1
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a1
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64F-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64F-NEXT:    slti $a1, $a0, 0
 ; LA64F-NEXT:    movgr2cf $fcc0, $a1
 ; LA64F-NEXT:    movgr2fr.w $fa1, $a0
 ; LA64F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: convert_u64_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    srli.d $a1, $a0, 1
 ; LA64D-NEXT:    andi $a2, $a0, 1
 ; LA64D-NEXT:    or $a1, $a2, $a1
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a1
 ; LA64D-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64D-NEXT:    fadd.s $fa0, $fa0, $fa0
 ; LA64D-NEXT:    slti $a1, $a0, 0
 ; LA64D-NEXT:    movgr2cf $fcc0, $a1
 ; LA64D-NEXT:    movgr2fr.w $fa1, $a0
 ; LA64D-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64D-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define i32 @bitcast_float_to_i32(float %a) nounwind {
 ; LA32F-LABEL: bitcast_float_to_i32:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movfr2gr.s $a0, $fa0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: bitcast_float_to_i32:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movfr2gr.s $a0, $fa0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: bitcast_float_to_i32:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: bitcast_float_to_i32:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movfr2gr.s $a0, $fa0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = bitcast float %a to i32
   ret i32 %1
 }
 
 define float @bitcast_i32_to_float(i32 %a) nounwind {
 ; LA32F-LABEL: bitcast_i32_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    movgr2fr.w $fa0, $a0
-; LA32F-NEXT:    jirl $zero, $ra, 0
+; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: bitcast_i32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    movgr2fr.w $fa0, $a0
-; LA32D-NEXT:    jirl $zero, $ra, 0
+; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: bitcast_i32_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
-; LA64F-NEXT:    jirl $zero, $ra, 0
+; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: bitcast_i32_to_float:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    movgr2fr.w $fa0, $a0
-; LA64D-NEXT:    jirl $zero, $ra, 0
+; LA64D-NEXT:    ret
   %1 = bitcast i32 %a to float
   ret float %1
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fmul.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'fmul' LLVM IR: https://llvm.org/docs/LangRef.html#fmul-instruction
 
 define float @fmul_s(float %x, float %y) {
 ; LA32-LABEL: fmul_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmul.s $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fmul_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmul.s $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %mul = fmul float %x, %y
   ret float %mul
 }
 
 define double @fmul_d(double %x, double %y) {
 ; LA32-LABEL: fmul_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmul.d $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fmul_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmul.d $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %mul = fmul double %x, %y
   ret double %mul
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fneg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'fneg' LLVM IR: https://llvm.org/docs/LangRef.html#fneg-instruction
 
 define float @fneg_s(float %x) {
 ; LA32-LABEL: fneg_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fneg.s $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fneg_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fneg.s $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = fneg float %x
   ret float %neg
 }
 
 define double @fneg_d(double %x) {
 ; LA32-LABEL: fneg_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fneg.d $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fneg_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fneg.d $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = fneg double %x
   ret double %neg
 }

llvm/test/CodeGen/LoongArch/ir-instruction/fsub.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'fsub' LLVM IR: https://llvm.org/docs/LangRef.html#fsub-instruction
 
 define float @fsub_s(float %x, float %y) {
 ; LA32-LABEL: fsub_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fsub.s $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fsub_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fsub.s $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = fsub float %x, %y
   ret float %sub
 }
 
 define double @fsub_d(double %x, double %y) {
 ; LA32-LABEL: fsub_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fsub.d $fa0, $fa0, $fa1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fsub_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = fsub double %x, %y
   ret double %sub
 }
 
 define float @fneg_s(float %x) {
 ; LA32-LABEL: fneg_s:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fneg.s $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fneg_s:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fneg.s $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
     %res = fsub float -0.0, %x
     ret float %res
 }
 
 define double @fneg_d(double %x) {
 ; LA32-LABEL: fneg_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fneg.d $fa0, $fa0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fneg_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fneg.d $fa0, $fa0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
     %res = fsub double -0.0, %x
     ret double %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/icmp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'icmp' LLVM IR: https://llvm.org/docs/LangRef.html#icmp-instruction
 
 define i1 @icmp_eq(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_eq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltui $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_eq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltui $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp eq i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_ne(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_ne:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltu $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ne:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltu $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ne i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_ugt(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ugt i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_uge(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp uge i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_ult(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ult i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_ule(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ule i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_sgt(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_sgt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_sgt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp sgt i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_sge(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_sge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_sge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp sge i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_slt(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_slt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_slt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp slt i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_sle(i32 signext %a, i32 signext %b) {
 ; LA32-LABEL: icmp_sle:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_sle:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp sle i32 %a, %b
   ret i1 %res
 }
 
 define i1 @icmp_slt_3(i32 signext %a) {
 ; LA32-LABEL: icmp_slt_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slti $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_slt_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slti $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp slt i32 %a, 3
   ret i1 %res
 }
 
 define i1 @icmp_ult_3(i32 signext %a) {
 ; LA32-LABEL: icmp_ult_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltui $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ult_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltui $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ult i32 %a, 3
   ret i1 %res
 }
 
 define i1 @icmp_eq_0(i32 signext %a) {
 ; LA32-LABEL: icmp_eq_0:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltui $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_eq_0:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltui $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp eq i32 %a, 0
   ret i1 %res
 }
 
 define i1 @icmp_eq_3(i32 signext %a) {
 ; LA32-LABEL: icmp_eq_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, -3
 ; LA32-NEXT:    sltui $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_eq_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, -3
 ; LA64-NEXT:    sltui $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp eq i32 %a, 3
   ret i1 %res
 }
 
 define i1 @icmp_ne_0(i32 signext %a) {
 ; LA32-LABEL: icmp_ne_0:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ne_0:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ne i32 %a, 0
   ret i1 %res
 }
 
 define i1 @icmp_ne_3(i32 signext %a) {
 ; LA32-LABEL: icmp_ne_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $a0, $a0, -3
 ; LA32-NEXT:    sltu $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: icmp_ne_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $a0, $a0, -3
 ; LA64-NEXT:    sltu $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = icmp ne i32 %a, 3
   ret i1 %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define i32 @indirectbr(ptr %target) nounwind {
 ; CHECK-LABEL: indirectbr:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    jirl $zero, $a0, 0
+; CHECK-NEXT:    jr $a0
 ; CHECK-NEXT:  .LBB0_1: # %test_label
 ; CHECK-NEXT:    move $a0, $zero
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   indirectbr ptr %target, [label %test_label]
 test_label:
   br label %ret
 ret:
   ret i32 0
 }
 
 define i32 @indirectbr_with_offset(ptr %a) nounwind {
 ; CHECK-LABEL: indirectbr_with_offset:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    jirl $zero, $a0, 1380
 ; CHECK-NEXT:  .LBB1_1: # %test_label
 ; CHECK-NEXT:    move $a0, $zero
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %target = getelementptr inbounds i8, ptr %a, i32 1380
   indirectbr ptr %target, [label %test_label]
 test_label:
   br label %ret
 ret:
   ret i32 0
 }

llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 define i8 @load_acquire_i8(ptr %ptr) {
 ; LA32-LABEL: load_acquire_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.b $a0, $a0, 0
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_acquire_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.b $a0, $a0, 0
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load atomic i8, ptr %ptr acquire, align 1
   ret i8 %val
 }
 
 define i16 @load_acquire_i16(ptr %ptr) {
 ; LA32-LABEL: load_acquire_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.h $a0, $a0, 0
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_acquire_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.h $a0, $a0, 0
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load atomic i16, ptr %ptr acquire, align 2
   ret i16 %val
 }
 
 define i32 @load_acquire_i32(ptr %ptr) {
 ; LA32-LABEL: load_acquire_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    dbar 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_acquire_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a0, $a0, 0
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load atomic i32, ptr %ptr acquire, align 4
   ret i32 %val
 }
 
 define i64 @load_acquire_i64(ptr %ptr) {
 ; LA32-LABEL: load_acquire_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    ori $a1, $zero, 2
 ; LA32-NEXT:    bl __atomic_load_8
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_acquire_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.d $a0, $a0, 0
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %val = load atomic i64, ptr %ptr acquire, align 8
   ret i64 %val
 }
 
 define void @store_release_i8(ptr %ptr, i8 signext %v) {
 ; LA32-LABEL: store_release_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    st.b $a0, $a1, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: store_release_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    st.b $a0, $a1, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   store atomic i8 %v, ptr %ptr release, align 1
   ret void
 }
 
 define void @store_release_i16(ptr %ptr, i16 signext %v) {
 ; LA32-LABEL: store_release_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    st.h $a0, $a1, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: store_release_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    st.h $a0, $a1, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   store atomic i16 %v, ptr %ptr release, align 2
   ret void
 }
 
 define void @store_release_i32(ptr %ptr, i32 signext %v) {
 ; LA32-LABEL: store_release_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    st.w $a0, $a1, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: store_release_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    st.w $a0, $a1, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   store atomic i32 %v, ptr %ptr release, align 4
   ret void
 }
 
 define void @store_release_i64(ptr %ptr, i64 %v) {
 ; LA32-LABEL: store_release_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    ori $a3, $zero, 3
 ; LA32-NEXT:    bl __atomic_store_8
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: store_release_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    st.d $a0, $a1, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   store atomic i64 %v, ptr %ptr release, align 8
   ret void
 }

llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll

 ; LA64NOPIC-NEXT:   pcalau12i $a0, G
 ; LA64NOPIC-NEXT:   addi.d $a1, $a0, G
 ; LA64PIC-NEXT:     pcalau12i $a0, .LG$local
 ; LA64PIC-NEXT:     addi.d $a1, $a0, .LG$local
 ; LA64-NEXT:        ld.w $a0, $a1, 0
 ; LA64-NEXT:        addi.d $a0, $a0, 1
 ; LA64-NEXT:        st.w $a0, $a1, 0
 
-; ALL-NEXT:         jirl $zero, $ra, 0
+; ALL-NEXT:         ret
 
   %v = load i32, ptr @G
   %sum = add i32 %v, 1
   store i32 %sum, ptr @G
   ret i32 %sum
 }
 
 define i32 @load_store_global_array(i32 %a) nounwind {

 ; LA64-NEXT:        ld.w $a1, $a2, 0
 ; LA64-NEXT:        st.w $a0, $a2, 0
 ; LA64NOPIC-NEXT:   ld.w $a3, $a2, 0
 ; LA64NOPIC-NEXT:   st.w $a0, $a2, 0
 ; LA64PIC-NEXT:     ld.w $a3, $a2, 36
 ; LA64PIC-NEXT:     st.w $a0, $a2, 36
 
 ; ALL-NEXT:         move $a0, $a1
-; ALL-NEXT:         jirl $zero, $ra, 0
+; ALL-NEXT:         ret
 
   %1 = load volatile i32, ptr @arr, align 4
   store i32 %a, ptr @arr, align 4
   %2 = getelementptr [10 x i32], ptr @arr, i32 0, i32 9
   %3 = load volatile i32, ptr %2, align 4
   store i32 %a, ptr %2, align 4
   ret i32 %1
 }
 
 ;; Check indexed and unindexed, sext, zext and anyext loads.
 
 define i64 @ld_b(ptr %a) nounwind {
 ; LA32-LABEL: ld_b:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.b $a1, $a0, 0
 ; LA32-NEXT:    ld.b $a0, $a0, 1
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_b:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.b $a1, $a0, 0
 ; LA64-NEXT:    ld.b $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i64 1
   %2 = load i8, ptr %1
   %3 = sext i8 %2 to i64
   %4 = load volatile i8, ptr %a
   ret i64 %3
 }
 
 define i64 @ld_h(ptr %a) nounwind {
 ; LA32-LABEL: ld_h:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.h $a1, $a0, 0
 ; LA32-NEXT:    ld.h $a0, $a0, 4
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_h:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.h $a1, $a0, 0
 ; LA64-NEXT:    ld.h $a0, $a0, 4
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i64 2
   %2 = load i16, ptr %1
   %3 = sext i16 %2 to i64
   %4 = load volatile i16, ptr %a
   ret i64 %3
 }
 
 define i64 @ld_w(ptr %a) nounwind {
 ; LA32-LABEL: ld_w:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a1, $a0, 0
 ; LA32-NEXT:    ld.w $a0, $a0, 12
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a1, $a0, 0
 ; LA64-NEXT:    ld.w $a0, $a0, 12
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i64 3
   %2 = load i32, ptr %1
   %3 = sext i32 %2 to i64
   %4 = load volatile i32, ptr %a
   ret i64 %3
 }
 
 define i64 @ld_d(ptr %a) nounwind {
 ; LA32-LABEL: ld_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a1, $a0, 4
 ; LA32-NEXT:    ld.w $a1, $a0, 0
 ; LA32-NEXT:    ld.w $a1, $a0, 28
 ; LA32-NEXT:    ld.w $a0, $a0, 24
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.d $a1, $a0, 0
 ; LA64-NEXT:    ld.d $a0, $a0, 24
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i64, ptr %a, i64 3
   %2 = load i64, ptr %1
   %3 = load volatile i64, ptr %a
   ret i64 %2
 }
 
 define i64 @ld_bu(ptr %a) nounwind {
 ; LA32-LABEL: ld_bu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.bu $a1, $a0, 0
 ; LA32-NEXT:    ld.bu $a2, $a0, 4
 ; LA32-NEXT:    add.w $a0, $a2, $a1
 ; LA32-NEXT:    sltu $a1, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_bu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.bu $a1, $a0, 0
 ; LA64-NEXT:    ld.bu $a0, $a0, 4
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i64 4
   %2 = load i8, ptr %1
   %3 = zext i8 %2 to i64
   %4 = load volatile i8, ptr %a
   %5 = zext i8 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 define i64 @ld_hu(ptr %a) nounwind {
 ; LA32-LABEL: ld_hu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.hu $a1, $a0, 0
 ; LA32-NEXT:    ld.hu $a2, $a0, 10
 ; LA32-NEXT:    add.w $a0, $a2, $a1
 ; LA32-NEXT:    sltu $a1, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_hu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.hu $a1, $a0, 0
 ; LA64-NEXT:    ld.hu $a0, $a0, 10
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i64 5
   %2 = load i16, ptr %1
   %3 = zext i16 %2 to i64
   %4 = load volatile i16, ptr %a
   %5 = zext i16 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 define i64 @ld_wu(ptr %a) nounwind {
 ; LA32-LABEL: ld_wu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.w $a1, $a0, 0
 ; LA32-NEXT:    ld.w $a2, $a0, 20
 ; LA32-NEXT:    add.w $a0, $a2, $a1
 ; LA32-NEXT:    sltu $a1, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_wu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.wu $a1, $a0, 0
 ; LA64-NEXT:    ld.wu $a0, $a0, 20
 ; LA64-NEXT:    add.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i64 5
   %2 = load i32, ptr %1
   %3 = zext i32 %2 to i64
   %4 = load volatile i32, ptr %a
   %5 = zext i32 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 define i64 @ldx_b(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_b:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.b $a2, $a1, 0
 ; LA32-NEXT:    ld.b $a0, $a0, 0
 ; LA32-NEXT:    srai.w $a1, $a2, 31
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_b:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ldx.b $a1, $a0, $a1
 ; LA64-NEXT:    ld.b $a0, $a0, 0
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i64 %idx
   %2 = load i8, ptr %1
   %3 = sext i8 %2 to i64
   %4 = load volatile i8, ptr %a
   ret i64 %3
 }
 
 define i64 @ldx_h(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_h:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 1
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.h $a2, $a1, 0
 ; LA32-NEXT:    ld.h $a0, $a0, 0
 ; LA32-NEXT:    srai.w $a1, $a2, 31
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_h:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 1
 ; LA64-NEXT:    ldx.h $a1, $a0, $a1
 ; LA64-NEXT:    ld.h $a0, $a0, 0
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i64 %idx
   %2 = load i16, ptr %1
   %3 = sext i16 %2 to i64
   %4 = load volatile i16, ptr %a
   ret i64 %3
 }
 
 define i64 @ldx_w(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_w:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 2
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    srai.w $a1, $a2, 31
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 2
 ; LA64-NEXT:    ldx.w $a1, $a0, $a1
 ; LA64-NEXT:    ld.w $a0, $a0, 0
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i64 %idx
   %2 = load i32, ptr %1
   %3 = sext i32 %2 to i64
   %4 = load volatile i32, ptr %a
   ret i64 %3
 }
 
 define i64 @ldx_d(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 3
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.w $a2, $a1, 0
 ; LA32-NEXT:    ld.w $a3, $a0, 0
 ; LA32-NEXT:    ld.w $a1, $a1, 4
 ; LA32-NEXT:    ld.w $a0, $a0, 4
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 3
 ; LA64-NEXT:    ldx.d $a1, $a0, $a1
 ; LA64-NEXT:    ld.d $a0, $a0, 0
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i64, ptr %a, i64 %idx
   %2 = load i64, ptr %1
   %3 = load volatile i64, ptr %a
   ret i64 %2
 }
 
 define i64 @ldx_bu(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_bu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.bu $a1, $a1, 0
 ; LA32-NEXT:    ld.bu $a0, $a0, 0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    sltu $a1, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_bu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ldx.bu $a1, $a0, $a1
 ; LA64-NEXT:    ld.bu $a0, $a0, 0
 ; LA64-NEXT:    add.d $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i8, ptr %a, i64 %idx
   %2 = load i8, ptr %1
   %3 = zext i8 %2 to i64
   %4 = load volatile i8, ptr %a
   %5 = zext i8 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 define i64 @ldx_hu(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_hu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 1
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.hu $a1, $a1, 0
 ; LA32-NEXT:    ld.hu $a0, $a0, 0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    sltu $a1, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_hu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 1
 ; LA64-NEXT:    ldx.hu $a1, $a0, $a1
 ; LA64-NEXT:    ld.hu $a0, $a0, 0
 ; LA64-NEXT:    add.d $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i16, ptr %a, i64 %idx
   %2 = load i16, ptr %1
   %3 = zext i16 %2 to i64
   %4 = load volatile i16, ptr %a
   %5 = zext i16 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 define i64 @ldx_wu(ptr %a, i64 %idx) nounwind {
 ; LA32-LABEL: ldx_wu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 2
 ; LA32-NEXT:    add.w $a1, $a0, $a1
 ; LA32-NEXT:    ld.w $a1, $a1, 0
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    sltu $a1, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldx_wu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 2
 ; LA64-NEXT:    ldx.wu $a1, $a0, $a1
 ; LA64-NEXT:    ld.wu $a0, $a0, 0
 ; LA64-NEXT:    add.d $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i64 %idx
   %2 = load i32, ptr %1
   %3 = zext i32 %2 to i64
   %4 = load volatile i32, ptr %a
   %5 = zext i32 %4 to i64
   %6 = add i64 %3, %5
   ret i64 %6
 }
 
 ;; Check indexed and unindexed stores.
 
 define void @st_b(ptr %a, i8 %b) nounwind {
 ; ALL-LABEL: st_b:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    st.b $a1, $a0, 6
 ; ALL-NEXT:    st.b $a1, $a0, 0
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   store i8 %b, ptr %a
   %1 = getelementptr i8, ptr %a, i64 6
   store i8 %b, ptr %1
   ret void
 }
 
 define void @st_h(ptr %a, i16 %b) nounwind {
 ; ALL-LABEL: st_h:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    st.h $a1, $a0, 14
 ; ALL-NEXT:    st.h $a1, $a0, 0
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   store i16 %b, ptr %a
   %1 = getelementptr i16, ptr %a, i64 7
   store i16 %b, ptr %1
   ret void
 }
 
 define void @st_w(ptr %a, i32 %b) nounwind {
 ; ALL-LABEL: st_w:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    st.w $a1, $a0, 28
 ; ALL-NEXT:    st.w $a1, $a0, 0
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   store i32 %b, ptr %a
   %1 = getelementptr i32, ptr %a, i64 7
   store i32 %b, ptr %1
   ret void
 }
 
 define void @st_d(ptr %a, i64 %b) nounwind {
 ; LA32-LABEL: st_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    st.w $a2, $a0, 68
 ; LA32-NEXT:    st.w $a2, $a0, 4
 ; LA32-NEXT:    st.w $a1, $a0, 64
 ; LA32-NEXT:    st.w $a1, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: st_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    st.d $a1, $a0, 64
 ; LA64-NEXT:    st.d $a1, $a0, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   store i64 %b, ptr %a
   %1 = getelementptr i64, ptr %a, i64 8
   store i64 %b, ptr %1
   ret void
 }
 
 define void @stx_b(ptr %dst, i64 %idx, i8 %val) nounwind {
 ; LA32-LABEL: stx_b:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    st.b $a3, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stx_b:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    stx.b $a2, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i8, ptr %dst, i64 %idx
   store i8 %val, ptr %1
   ret void
 }
 
 define void @stx_h(ptr %dst, i64 %idx, i16 %val) nounwind {
 ; LA32-LABEL: stx_h:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 1
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    st.h $a3, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stx_h:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 1
 ; LA64-NEXT:    stx.h $a2, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i16, ptr %dst, i64 %idx
   store i16 %val, ptr %1
   ret void
 }
 
 define void @stx_w(ptr %dst, i64 %idx, i32 %val) nounwind {
 ; LA32-LABEL: stx_w:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 2
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    st.w $a3, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stx_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 2
 ; LA64-NEXT:    stx.w $a2, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i32, ptr %dst, i64 %idx
   store i32 %val, ptr %1
   ret void
 }
 
 define void @stx_d(ptr %dst, i64 %idx, i64 %val) nounwind {
 ; LA32-LABEL: stx_d:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 3
 ; LA32-NEXT:    add.w $a0, $a0, $a1
 ; LA32-NEXT:    st.w $a4, $a0, 4
 ; LA32-NEXT:    st.w $a3, $a0, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stx_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 3
 ; LA64-NEXT:    stx.d $a2, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i64, ptr %dst, i64 %idx
   store i64 %val, ptr %1
   ret void
 }
 
 ;; Check load from and store to an i1 location.
 define i64 @load_sext_zext_anyext_i1(ptr %a) nounwind {
   ;; sextload i1
 ; LA32-LABEL: load_sext_zext_anyext_i1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.b $a1, $a0, 0
 ; LA32-NEXT:    ld.bu $a1, $a0, 1
 ; LA32-NEXT:    ld.bu $a2, $a0, 2
 ; LA32-NEXT:    sub.w $a0, $a2, $a1
 ; LA32-NEXT:    sltu $a1, $a2, $a1
 ; LA32-NEXT:    sub.w $a1, $zero, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_sext_zext_anyext_i1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.b $a1, $a0, 0
 ; LA64-NEXT:    ld.bu $a1, $a0, 1
 ; LA64-NEXT:    ld.bu $a0, $a0, 2
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i1, ptr %a, i64 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i64
   ;; zextload i1
   %4 = getelementptr i1, ptr %a, i64 2
   %5 = load i1, ptr %4
   %6 = zext i1 %5 to i64
   %7 = add i64 %3, %6
   ;; extload i1 (anyext). Produced as the load is unused.
   %8 = load volatile i1, ptr %a
   ret i64 %7
 }
 
 define i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
   ;; sextload i1
 ; LA32-LABEL: load_sext_zext_anyext_i1_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ld.b $a1, $a0, 0
 ; LA32-NEXT:    ld.bu $a1, $a0, 1
 ; LA32-NEXT:    ld.bu $a0, $a0, 2
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_sext_zext_anyext_i1_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.b $a1, $a0, 0
 ; LA64-NEXT:    ld.bu $a1, $a0, 1
 ; LA64-NEXT:    ld.bu $a0, $a0, 2
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = getelementptr i1, ptr %a, i64 1
   %2 = load i1, ptr %1
   %3 = sext i1 %2 to i16
   ;; zextload i1
   %4 = getelementptr i1, ptr %a, i64 2
   %5 = load i1, ptr %4
   %6 = zext i1 %5 to i16
   %7 = add i16 %3, %6

 ; LA32-NEXT:    ori $a4, $a3, 3823
 ; LA32-NEXT:    ld.w $a2, $a4, 0
 ; LA32-NEXT:    st.w $a0, $a4, 0
 ; LA32-NEXT:    ori $a0, $a3, 3827
 ; LA32-NEXT:    ld.w $a3, $a0, 0
 ; LA32-NEXT:    st.w $a1, $a0, 0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    move $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ld_sd_constant:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    lu12i.w $a1, -136485
 ; LA64-NEXT:    ori $a1, $a1, 3823
 ; LA64-NEXT:    lu32i.d $a1, -147729
 ; LA64-NEXT:    lu52i.d $a2, $a1, -534
 ; LA64-NEXT:    ld.d $a1, $a2, 0
 ; LA64-NEXT:    st.d $a0, $a2, 0
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = inttoptr i64 16045690984833335023 to ptr
   %2 = load volatile i64, ptr %1
   store i64 %a, ptr %1
   ret i64 %2
 }
 
 ;; Check load from and store to a float location.
 define float @load_store_float(ptr %a, float %b) nounwind {
 ; ALL-LABEL: load_store_float:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    fld.s $fa1, $a0, 4
 ; ALL-NEXT:    fst.s $fa0, $a0, 4
 ; ALL-NEXT:    fmov.s $fa0, $fa1
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   %1 = getelementptr float, ptr %a, i64 1
   %2 = load float, ptr %1
   store float %b, ptr %1
   ret float %2
 }
 
 ;; Check load from and store to a double location.
 define double @load_store_double(ptr %a, double %b) nounwind {
 ; ALL-LABEL: load_store_double:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    fld.d $fa1, $a0, 8
 ; ALL-NEXT:    fst.d $fa0, $a0, 8
 ; ALL-NEXT:    fmov.d $fa0, $fa1
-; ALL-NEXT:    jirl $zero, $ra, 0
+; ALL-NEXT:    ret
   %1 = getelementptr double, ptr %a, i64 1
   %2 = load double, ptr %1
   store double %b, ptr %1
   ret double %2
 }

llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'lshr' LLVM IR: https://llvm.org/docs/LangRef.html#lshr-instruction
 
 define i1 @lshr_i1(i1 %x, i1 %y) {
 ; LA32-LABEL: lshr_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i1 %x, %y
   ret i1 %lshr
 }
 
 define i8 @lshr_i8(i8 %x, i8 %y) {
 ; LA32-LABEL: lshr_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 255
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 255
 ; LA64-NEXT:    srl.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i8 %x, %y
   ret i8 %lshr
 }
 
 define i16 @lshr_i16(i16 %x, i16 %y) {
 ; LA32-LABEL: lshr_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
 ; LA64-NEXT:    srl.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i16 %x, %y
   ret i16 %lshr
 }
 
 define i32 @lshr_i32(i32 %x, i32 %y) {
 ; LA32-LABEL: lshr_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srl.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i32 %x, %y
   ret i32 %lshr
 }
 
 define i64 @lshr_i64(i64 %x, i64 %y) {
 ; LA32-LABEL: lshr_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xori $a3, $a2, 31
 ; LA32-NEXT:    slli.w $a4, $a1, 1
 ; LA32-NEXT:    sll.w $a3, $a4, $a3
 ; LA32-NEXT:    srl.w $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a3
 ; LA32-NEXT:    addi.w $a3, $a2, -32
 ; LA32-NEXT:    slti $a4, $a3, 0
 ; LA32-NEXT:    maskeqz $a0, $a0, $a4
 ; LA32-NEXT:    srl.w $a5, $a1, $a3
 ; LA32-NEXT:    masknez $a4, $a5, $a4
 ; LA32-NEXT:    or $a0, $a0, $a4
 ; LA32-NEXT:    srl.w $a1, $a1, $a2
 ; LA32-NEXT:    srai.w $a2, $a3, 31
 ; LA32-NEXT:    and $a1, $a2, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srl.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i64 %x, %y
   ret i64 %lshr
 }
 
 define i1 @lshr_i1_3(i1 %x) {
 ; LA32-LABEL: lshr_i1_3:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i1_3:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i1 %x, 3
   ret i1 %lshr
 }
 
 define i8 @lshr_i8_3(i8 %x) {
 ; LA32-LABEL: lshr_i8_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 7, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i8_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 7, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i8 %x, 3
   ret i8 %lshr
 }
 
 define i16 @lshr_i16_3(i16 %x) {
 ; LA32-LABEL: lshr_i16_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i16_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i16 %x, 3
   ret i16 %lshr
 }
 
 define i32 @lshr_i32_3(i32 %x) {
 ; LA32-LABEL: lshr_i32_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i32_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i32 %x, 3
   ret i32 %lshr
 }
 
 define i64 @lshr_i64_3(i64 %x) {
 ; LA32-LABEL: lshr_i64_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srli.w $a0, $a0, 3
 ; LA32-NEXT:    slli.w $a2, $a1, 29
 ; LA32-NEXT:    or $a0, $a0, $a2
 ; LA32-NEXT:    srli.w $a1, $a1, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: lshr_i64_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %lshr = lshr i64 %x, 3
   ret i64 %lshr
 }

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'mul' LLVM IR: https://llvm.org/docs/LangRef.html#mul-instruction
 
 define i1 @mul_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: mul_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mul.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = mul i1 %a, %b
   ret i1 %r
 }
 
 define i8 @mul_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: mul_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mul.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = mul i8 %a, %b
   ret i8 %r
 }
 
 define i16 @mul_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: mul_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mul.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define i32 @mul_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: mul_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mul.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define i64 @mul_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: mul_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mul.w $a3, $a0, $a3
 ; LA32-NEXT:    mulh.wu $a4, $a0, $a2
 ; LA32-NEXT:    add.w $a3, $a4, $a3
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = mul i64 %a, %b
   ret i64 %r
 }
 
 define i64 @mul_pow2(i64 %a) {
 ; LA32-LABEL: mul_pow2:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 3
 ; LA32-NEXT:    srli.w $a2, $a0, 29
 ; LA32-NEXT:    or $a1, $a1, $a2
 ; LA32-NEXT:    slli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_pow2:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = mul i64 %a, 8
   ret i64 %1
 }
 
 define i64 @mul_p5(i64 %a) {
 ; LA32-LABEL: mul_p5:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ori $a2, $zero, 5
 ; LA32-NEXT:    mul.w $a1, $a1, $a2
 ; LA32-NEXT:    mulh.wu $a3, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a3, $a1
 ; LA32-NEXT:    mul.w $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mul_p5:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ori $a1, $zero, 5
 ; LA64-NEXT:    mul.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = mul i64 %a, 5
   ret i64 %1
 }
 
 define i32 @mulh_w(i32 %a, i32 %b) {
 ; LA32-LABEL: mulh_w:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    mulh.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulh_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulw.d.w $a0, $a0, $a1
 ; LA64-NEXT:    srli.d $a0, $a0, 32
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i32 %a to i64
   %2 = sext i32 %b to i64
   %3 = mul i64 %1, %2
   %4 = lshr i64 %3, 32
   %5 = trunc i64 %4 to i32
   ret i32 %5
 }
 
 define i32 @mulh_wu(i32 %a, i32 %b) {
 ; LA32-LABEL: mulh_wu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    mulh.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulh_wu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulw.d.wu $a0, $a0, $a1
 ; LA64-NEXT:    srli.d $a0, $a0, 32
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i32 %a to i64
   %2 = zext i32 %b to i64
   %3 = mul i64 %1, %2
   %4 = lshr i64 %3, 32
   %5 = trunc i64 %4 to i32
   ret i32 %5
 }
 

 ; LA32-NEXT:    add.w $a1, $a1, $a2
 ; LA32-NEXT:    add.w $a2, $a0, $a7
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    add.w $a1, $a5, $a0
 ; LA32-NEXT:    add.w $a0, $a4, $a2
 ; LA32-NEXT:    sltu $a2, $a0, $a4
 ; LA32-NEXT:    add.w $a1, $a1, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulh_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulh.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i64 %a to i128
   %2 = sext i64 %b to i128
   %3 = mul i128 %1, %2
   %4 = lshr i128 %3, 64
   %5 = trunc i128 %4 to i64
   ret i64 %5
 }
 

 ; LA32-NEXT:    mul.w $a4, $a1, $a3
 ; LA32-NEXT:    mulh.wu $a1, $a1, $a3
 ; LA32-NEXT:    add.w $a0, $a2, $a0
 ; LA32-NEXT:    sltu $a2, $a0, $a2
 ; LA32-NEXT:    add.w $a1, $a1, $a2
 ; LA32-NEXT:    add.w $a0, $a4, $a0
 ; LA32-NEXT:    sltu $a2, $a0, $a4
 ; LA32-NEXT:    add.w $a1, $a1, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulh_du:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulh.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i64 %a to i128
   %2 = zext i64 %b to i128
   %3 = mul i128 %1, %2
   %4 = lshr i128 %3, 64
   %5 = trunc i128 %4 to i64
   ret i64 %5
 }
 
 define i64 @mulw_d_w(i32 %a, i32 %b) {
 ; LA32-LABEL: mulw_d_w:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    mul.w $a2, $a0, $a1
 ; LA32-NEXT:    mulh.w $a1, $a0, $a1
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulw_d_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulw.d.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i32 %a to i64
   %2 = sext i32 %b to i64
   %3 = mul i64 %1, %2
   ret i64 %3
 }
 
 define i64 @mulw_d_wu(i32 %a, i32 %b) {
 ; LA32-LABEL: mulw_d_wu:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    mul.w $a2, $a0, $a1
 ; LA32-NEXT:    mulh.wu $a1, $a0, $a1
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: mulw_d_wu:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    mulw.d.wu $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i32 %a to i64
   %2 = zext i32 %b to i64
   %3 = mul i64 %1, %2
   ret i64 %3
 }

llvm/test/CodeGen/LoongArch/ir-instruction/or.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'or' LLVM IR: https://llvm.org/docs/LangRef.html#or-instruction
 
 define i1 @or_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: or_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i1 %a, %b
   ret i1 %r
 }
 
 define i8 @or_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: or_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i8 %a, %b
   ret i8 %r
 }
 
 define i16 @or_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: or_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i16 %a, %b
   ret i16 %r
 }
 
 define i32 @or_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: or_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i32 %a, %b
   ret i32 %r
 }
 
 define i64 @or_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: or_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    or $a0, $a0, $a2
 ; LA32-NEXT:    or $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i64 %a, %b
   ret i64 %r
 }
 
 define i1 @or_i1_0(i1 %b) {
 ; LA32-LABEL: or_i1_0:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i1_0:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i1 4, %b
   ret i1 %r
 }
 
 define i1 @or_i1_5(i1 %b) {
 ; LA32-LABEL: or_i1_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $zero, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i1_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $zero, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i1 5, %b
   ret i1 %r
 }
 
 define i8 @or_i8_5(i8 %b) {
 ; LA32-LABEL: or_i8_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i8_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i8 5, %b
   ret i8 %r
 }
 
 define i8 @or_i8_257(i8 %b) {
 ; LA32-LABEL: or_i8_257:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i8_257:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i8 257, %b
   ret i8 %r
 }
 
 define i16 @or_i16_5(i16 %b) {
 ; LA32-LABEL: or_i16_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i16_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i16 5, %b
   ret i16 %r
 }
 
 define i16 @or_i16_0x1000(i16 %b) {
 ; LA32-LABEL: or_i16_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i16_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i16 4096, %b
   ret i16 %r
 }
 
 define i16 @or_i16_0x10001(i16 %b) {
 ; LA32-LABEL: or_i16_0x10001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i16_0x10001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i16 65537, %b
   ret i16 %r
 }
 
 define i32 @or_i32_5(i32 %b) {
 ; LA32-LABEL: or_i32_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i32_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i32 5, %b
   ret i32 %r
 }
 
 define i32 @or_i32_0x1000(i32 %b) {
 ; LA32-LABEL: or_i32_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i32_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i32 4096, %b
   ret i32 %r
 }
 
 define i32 @or_i32_0x100000001(i32 %b) {
 ; LA32-LABEL: or_i32_0x100000001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i32_0x100000001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i32 4294967297, %b
   ret i32 %r
 }
 
 define i64 @or_i64_5(i64 %b) {
 ; LA32-LABEL: or_i64_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i64_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i64 5, %b
   ret i64 %r
 }
 
 define i64 @or_i64_0x1000(i64 %b) {
 ; LA32-LABEL: or_i64_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    or $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: or_i64_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = or i64 4096, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 ; RUN: llc --mtriple=loongarch32 -loongarch-check-zero-division < %s \
 ; RUN:     | FileCheck %s --check-prefix=LA32-TRAP
 ; RUN: llc --mtriple=loongarch64 -loongarch-check-zero-division < %s \
 ; RUN:     | FileCheck %s --check-prefix=LA64-TRAP
 
 ;; Test the sdiv/udiv/srem/urem LLVM IR.
 
 define i1 @sdiv_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: sdiv_i1:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i1:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i1:
 ; LA32-TRAP:       # %bb.0: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i1:
 ; LA64-TRAP:       # %bb.0: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = sdiv i1 %a, %b
   ret i1 %r
 }
 
 define i8 @sdiv_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: sdiv_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ext.w.b $a1, $a1
 ; LA32-NEXT:    ext.w.b $a0, $a0
 ; LA32-NEXT:    div.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ext.w.b $a1, $a1
 ; LA64-NEXT:    ext.w.b $a0, $a0
 ; LA64-NEXT:    div.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i8:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    ext.w.b $a1, $a1
 ; LA32-TRAP-NEXT:    ext.w.b $a0, $a0
 ; LA32-TRAP-NEXT:    div.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB1_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB1_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i8:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    ext.w.b $a1, $a1
 ; LA64-TRAP-NEXT:    ext.w.b $a0, $a0
 ; LA64-TRAP-NEXT:    div.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB1_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB1_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = sdiv i8 %a, %b
   ret i8 %r
 }
 
 define i16 @sdiv_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: sdiv_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ext.w.h $a1, $a1
 ; LA32-NEXT:    ext.w.h $a0, $a0
 ; LA32-NEXT:    div.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ext.w.h $a1, $a1
 ; LA64-NEXT:    ext.w.h $a0, $a0
 ; LA64-NEXT:    div.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i16:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    ext.w.h $a1, $a1
 ; LA32-TRAP-NEXT:    ext.w.h $a0, $a0
 ; LA32-TRAP-NEXT:    div.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB2_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB2_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i16:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    ext.w.h $a1, $a1
 ; LA64-TRAP-NEXT:    ext.w.h $a0, $a0
 ; LA64-TRAP-NEXT:    div.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB2_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB2_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = sdiv i16 %a, %b
   ret i16 %r
 }
 
 define i32 @sdiv_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: sdiv_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    div.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    div.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i32:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    div.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB3_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB3_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i32:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    addi.w $a1, $a1, 0
 ; LA64-TRAP-NEXT:    addi.w $a0, $a0, 0
 ; LA64-TRAP-NEXT:    div.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB3_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB3_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 
 define i64 @sdiv_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: sdiv_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    bl __divdi3
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    div.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
 ; LA32-TRAP-NEXT:    bl __divdi3
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    div.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB4_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB4_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
 
 define i1 @udiv_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: udiv_i1:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i1:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i1:
 ; LA32-TRAP:       # %bb.0: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i1:
 ; LA64-TRAP:       # %bb.0: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = udiv i1 %a, %b
   ret i1 %r
 }
 
 define i8 @udiv_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: udiv_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a1, $a1, 255
 ; LA32-NEXT:    andi $a0, $a0, 255
 ; LA32-NEXT:    div.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    andi $a0, $a0, 255
 ; LA64-NEXT:    div.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i8:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    andi $a1, $a1, 255
 ; LA32-TRAP-NEXT:    andi $a0, $a0, 255
 ; LA32-TRAP-NEXT:    div.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB6_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB6_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i8:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    andi $a1, $a1, 255
 ; LA64-TRAP-NEXT:    andi $a0, $a0, 255
 ; LA64-TRAP-NEXT:    div.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB6_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB6_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = udiv i8 %a, %b
   ret i8 %r
 }
 
 define i16 @udiv_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: udiv_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    bstrpick.w $a1, $a1, 15, 0
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-NEXT:    div.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
 ; LA64-NEXT:    div.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i16:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    bstrpick.w $a1, $a1, 15, 0
 ; LA32-TRAP-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-TRAP-NEXT:    div.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB7_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB7_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i16:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-TRAP-NEXT:    bstrpick.d $a0, $a0, 15, 0
 ; LA64-TRAP-NEXT:    div.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB7_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB7_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = udiv i16 %a, %b
   ret i16 %r
 }
 
 define i32 @udiv_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: udiv_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    div.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 31, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    div.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i32:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    div.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB8_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB8_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i32:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    bstrpick.d $a1, $a1, 31, 0
 ; LA64-TRAP-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-TRAP-NEXT:    div.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB8_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB8_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = udiv i32 %a, %b
   ret i32 %r
 }
 
 define i64 @udiv_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: udiv_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    bl __udivdi3
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    div.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
 ; LA32-TRAP-NEXT:    bl __udivdi3
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    div.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB9_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB9_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = udiv i64 %a, %b
   ret i64 %r
 }
 
 define i1 @srem_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: srem_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    move $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    move $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i1:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    move $a0, $zero
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i1:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    move $a0, $zero
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = srem i1 %a, %b
   ret i1 %r
 }
 
 define i8 @srem_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: srem_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ext.w.b $a1, $a1
 ; LA32-NEXT:    ext.w.b $a0, $a0
 ; LA32-NEXT:    mod.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ext.w.b $a1, $a1
 ; LA64-NEXT:    ext.w.b $a0, $a0
 ; LA64-NEXT:    mod.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i8:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    ext.w.b $a1, $a1
 ; LA32-TRAP-NEXT:    ext.w.b $a0, $a0
 ; LA32-TRAP-NEXT:    mod.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB11_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB11_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i8:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    ext.w.b $a1, $a1
 ; LA64-TRAP-NEXT:    ext.w.b $a0, $a0
 ; LA64-TRAP-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB11_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB11_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = srem i8 %a, %b
   ret i8 %r
 }
 
 define i16 @srem_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: srem_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    ext.w.h $a1, $a1
 ; LA32-NEXT:    ext.w.h $a0, $a0
 ; LA32-NEXT:    mod.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ext.w.h $a1, $a1
 ; LA64-NEXT:    ext.w.h $a0, $a0
 ; LA64-NEXT:    mod.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i16:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    ext.w.h $a1, $a1
 ; LA32-TRAP-NEXT:    ext.w.h $a0, $a0
 ; LA32-TRAP-NEXT:    mod.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB12_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB12_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i16:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    ext.w.h $a1, $a1
 ; LA64-TRAP-NEXT:    ext.w.h $a0, $a0
 ; LA64-TRAP-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB12_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB12_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = srem i16 %a, %b
   ret i16 %r
 }
 
 define i32 @srem_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: srem_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mod.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    mod.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i32:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    mod.w $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB13_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB13_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i32:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    addi.w $a1, $a1, 0
 ; LA64-TRAP-NEXT:    addi.w $a0, $a0, 0
 ; LA64-TRAP-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB13_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB13_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = srem i32 %a, %b
   ret i32 %r
 }
 
 define i64 @srem_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: srem_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    bl __moddi3
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mod.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
 ; LA32-TRAP-NEXT:    bl __moddi3
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB14_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB14_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = srem i64 %a, %b
   ret i64 %r
 }
 
 define i1 @urem_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: urem_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    move $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    move $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i1:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    move $a0, $zero
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i1:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    move $a0, $zero
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i1 %a, %b
   ret i1 %r
 }
 
 define i8 @urem_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: urem_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    andi $a1, $a1, 255
 ; LA32-NEXT:    andi $a0, $a0, 255
 ; LA32-NEXT:    mod.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    andi $a0, $a0, 255
 ; LA64-NEXT:    mod.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i8:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    andi $a1, $a1, 255
 ; LA32-TRAP-NEXT:    andi $a0, $a0, 255
 ; LA32-TRAP-NEXT:    mod.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB16_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB16_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i8:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    andi $a1, $a1, 255
 ; LA64-TRAP-NEXT:    andi $a0, $a0, 255
 ; LA64-TRAP-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB16_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB16_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i8 %a, %b
   ret i8 %r
 }
 
 define i16 @urem_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: urem_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    bstrpick.w $a1, $a1, 15, 0
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-NEXT:    mod.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
 ; LA64-NEXT:    mod.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i16:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    bstrpick.w $a1, $a1, 15, 0
 ; LA32-TRAP-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-TRAP-NEXT:    mod.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB17_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB17_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i16:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-TRAP-NEXT:    bstrpick.d $a0, $a0, 15, 0
 ; LA64-TRAP-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB17_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB17_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i16 %a, %b
   ret i16 %r
 }
 
 define i32 @urem_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: urem_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    mod.wu $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 31, 0
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-NEXT:    mod.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i32:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    mod.wu $a0, $a0, $a1
 ; LA32-TRAP-NEXT:    bnez $a1, .LBB18_2
 ; LA32-TRAP-NEXT:  # %bb.1: # %entry
 ; LA32-TRAP-NEXT:    break 7
 ; LA32-TRAP-NEXT:  .LBB18_2: # %entry
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i32:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    bstrpick.d $a1, $a1, 31, 0
 ; LA64-TRAP-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; LA64-TRAP-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB18_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB18_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i32 %a, %b
   ret i32 %r
 }
 
 define i64 @urem_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: urem_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    bl __umoddi3
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mod.du $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
 ; LA32-TRAP-NEXT:    bl __umoddi3
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
-; LA32-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB19_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB19_2: # %entry
-; LA64-TRAP-NEXT:    jirl $zero, $ra, 0
+; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i64 %a, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-dbl.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the bare double-precision floating-point values selection:
 ;; https://llvm.org/docs/LangRef.html#select-instruction
 
 define double @test(i1 %a, double %b, double %c) {
 ; LA32-LABEL: test:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, double %b, double %c
   ret double %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-flt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test the bare single-precision floating-point values selection:
 ;; https://llvm.org/docs/LangRef.html#select-instruction
 
 define float @test(i1 %a, float %b, float %c) {
 ; LA32-LABEL: test:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, float %b, float %c
   ret float %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the bare integers 'select' LLVM IR: https://llvm.org/docs/LangRef.html#select-instruction
 
 define i1 @bare_select_i1(i1 %a, i1 %b, i1 %c) {
 ; LA32-LABEL: bare_select_i1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    masknez $a2, $a2, $a0
 ; LA32-NEXT:    maskeqz $a0, $a1, $a0
 ; LA32-NEXT:    or $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bare_select_i1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, i1 %b, i1 %c
   ret i1 %res
 }
 
 define i8 @bare_select_i8(i1 %a, i8 %b, i8 %c) {
 ; LA32-LABEL: bare_select_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    masknez $a2, $a2, $a0
 ; LA32-NEXT:    maskeqz $a0, $a1, $a0
 ; LA32-NEXT:    or $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bare_select_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, i8 %b, i8 %c
   ret i8 %res
 }
 
 define i16 @bare_select_i16(i1 %a, i16 %b, i16 %c) {
 ; LA32-LABEL: bare_select_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    masknez $a2, $a2, $a0
 ; LA32-NEXT:    maskeqz $a0, $a1, $a0
 ; LA32-NEXT:    or $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bare_select_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, i16 %b, i16 %c
   ret i16 %res
 }
 
 define i32 @bare_select_i32(i1 %a, i32 %b, i32 %c) {
 ; LA32-LABEL: bare_select_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    masknez $a2, $a2, $a0
 ; LA32-NEXT:    maskeqz $a0, $a1, $a0
 ; LA32-NEXT:    or $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bare_select_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, i32 %b, i32 %c
   ret i32 %res
 }
 
 define i64 @bare_select_i64(i1 %a, i64 %b, i64 %c) {
 ; LA32-LABEL: bare_select_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a5, $a0, 1
 ; LA32-NEXT:    masknez $a0, $a3, $a5
 ; LA32-NEXT:    maskeqz $a1, $a1, $a5
 ; LA32-NEXT:    or $a0, $a1, $a0
 ; LA32-NEXT:    masknez $a1, $a4, $a5
 ; LA32-NEXT:    maskeqz $a2, $a2, $a5
 ; LA32-NEXT:    or $a1, $a2, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bare_select_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    masknez $a2, $a2, $a0
 ; LA64-NEXT:    maskeqz $a0, $a1, $a0
 ; LA64-NEXT:    or $a0, $a0, $a2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %res = select i1 %a, i64 %b, i64 %c
   ret i64 %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-dbl.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test double-precision floating-point values selection after comparison
 
 define double @fcmp_false(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmov.d $fa0, $fa3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmov.d $fa0, $fa3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_oeq(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ogt(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_oge(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_olt(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ole(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_one(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ord(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ueq(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ugt(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_uge(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ult(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_ule(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_une(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_uno(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }
 
 define double @fcmp_true(double %a, double %b, double %x, double %y) {
 ; LA32-LABEL: fcmp_true:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmov.d $fa0, $fa2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_true:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmov.d $fa0, $fa2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true double %a, %b
   %res = select i1 %cmp, double %x, double %y
   ret double %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-flt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test single-precision floating-point values selection after comparison
 
 define float @fcmp_false(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmov.s $fa0, $fa3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmov.s $fa0, $fa3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_oeq(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ogt(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_oge(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_olt(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ole(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_one(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ord(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ueq(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ugt(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_uge(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ult(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_ule(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_une(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_uno(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    fsel $fa0, $fa3, $fa2, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }
 
 define float @fcmp_true(float %a, float %b, float %x, float %y) {
 ; LA32-LABEL: fcmp_true:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fmov.s $fa0, $fa2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_true:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fmov.s $fa0, $fa2
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true float %a, %b
   %res = select i1 %cmp, float %x, float %y
   ret float %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-int.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test integers selection after `fcmp`
 
 define i32 @f32_fcmp_false(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_oeq(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ogt(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_oge(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_olt(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ole(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_one(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ord(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ueq(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ugt(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_uge(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ult(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_ule(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_une(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_uno(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.s $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f32_fcmp_true(float %a, float %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f32_fcmp_true:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f32_fcmp_true:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true float %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_false(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_false:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_false:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    move $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp false double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_oeq(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_oeq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oeq double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ogt(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ogt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ogt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ogt double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_oge(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_oge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_oge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp oge double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_olt(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_olt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp olt double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ole(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ole:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ole double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_one(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_one:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_one:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cne.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp one double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ord(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ord:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ord:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cor.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ord double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ueq(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ueq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ueq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cueq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ueq double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ugt(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ugt double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_uge(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa1, $fa0
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uge double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ult(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cult.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ult double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_ule(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cule.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp ule double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_une(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_une:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_une:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cune.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp une double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_uno(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_uno:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a2, $fcc0
 ; LA32-NEXT:    masknez $a1, $a1, $a2
 ; LA32-NEXT:    maskeqz $a0, $a0, $a2
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_uno:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    fcmp.cun.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a2, $fcc0
 ; LA64-NEXT:    masknez $a1, $a1, $a2
 ; LA64-NEXT:    maskeqz $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp uno double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @f64_fcmp_true(double %a, double %b, i32 %x, i32 %y) {
 ; LA32-LABEL: f64_fcmp_true:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: f64_fcmp_true:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cmp = fcmp true double %a, %b
   %res = select i1 %cmp, i32 %x, i32 %y
   ret i32 %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-dbl.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test double-precision floating-point values selection after integers comparison
 
 define double @select_eq(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_eq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltui $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_eq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltui $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp eq i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_ne(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_ne:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltu $a0, $zero, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ne:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltu $a0, $zero, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ne i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_ugt(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ugt i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_uge(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp uge i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_ult(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ult i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_ule(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ule i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_sgt(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_sgt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sgt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sgt i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_sge(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_sge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sge i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_slt(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_slt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_slt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp slt i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }
 
 define double @select_sle(i32 signext %a, i32 signext %b, double %x, double %y) {
 ; LA32-LABEL: select_sle:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sle:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sle i32 %a, %b
   %res = select i1 %cond, double %x, double %y
   ret double %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-flt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test single-precision floating-point values selection after integers comparison
 
 define float @select_eq(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_eq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltui $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_eq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltui $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp eq i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_ne(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_ne:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltu $a0, $zero, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ne:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltu $a0, $zero, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ne i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_ugt(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ugt i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_uge(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp uge i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_ult(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ult i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_ule(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ule i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_sgt(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_sgt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sgt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sgt i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_sge(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_sge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sge i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_slt(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_slt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_slt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp slt i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }
 
 define float @select_sle(i32 signext %a, i32 signext %b, float %x, float %y) {
 ; LA32-LABEL: select_sle:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    movgr2cf $fcc0, $a0
 ; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sle:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    movgr2cf $fcc0, $a0
 ; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sle i32 %a, %b
   %res = select i1 %cond, float %x, float %y
   ret float %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-int.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test integers selection after integers comparison
 
 define i32 @select_eq(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_eq:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltui $a0, $a0, 1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_eq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltui $a0, $a0, 1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp eq i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_ne(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_ne:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xor $a0, $a0, $a1
 ; LA32-NEXT:    sltu $a0, $zero, $a0
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ne:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    xor $a0, $a0, $a1
 ; LA64-NEXT:    sltu $a0, $zero, $a0
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ne i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_ugt(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_ugt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ugt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ugt i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_uge(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_uge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_uge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp uge i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_ult(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_ult:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a0, $a1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ult:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a0, $a1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ult i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_ule(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_ule:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sltu $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_ule:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sltu $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp ule i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_sgt(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_sgt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sgt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sgt i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_sge(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_sge:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sge:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sge i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_slt(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_slt:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a0, $a1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_slt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a0, $a1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp slt i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }
 
 define i32 @select_sle(i32 signext %a, i32 signext %b, i32 %x, i32 %y) {
 ; LA32-LABEL: select_sle:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slt $a0, $a1, $a0
 ; LA32-NEXT:    xori $a0, $a0, 1
 ; LA32-NEXT:    masknez $a1, $a3, $a0
 ; LA32-NEXT:    maskeqz $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: select_sle:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slt $a0, $a1, $a0
 ; LA64-NEXT:    xori $a0, $a0, 1
 ; LA64-NEXT:    masknez $a1, $a3, $a0
 ; LA64-NEXT:    maskeqz $a0, $a2, $a0
 ; LA64-NEXT:    or $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %cond = icmp sle i32 %a, %b
   %res = select i1 %cond, i32 %x, i32 %y
   ret i32 %res
 }

llvm/test/CodeGen/LoongArch/ir-instruction/sext-zext-trunc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Test sext/zext/trunc
 
 define i8 @sext_i1_to_i8(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    sub.w $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i1_to_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    sub.d $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i1 %a to i8
   ret i8 %1
 }
 
 define i16 @sext_i1_to_i16(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    sub.w $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i1_to_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    sub.d $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i1 %a to i16
   ret i16 %1
 }
 
 define i32 @sext_i1_to_i32(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    sub.w $a0, $zero, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i1_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    sub.d $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i1 %a to i32
   ret i32 %1
 }
 
 define i64 @sext_i1_to_i64(i1 %a) {
 ; LA32-LABEL: sext_i1_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    sub.w $a0, $zero, $a0
 ; LA32-NEXT:    move $a1, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i1_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
 ; LA64-NEXT:    sub.d $a0, $zero, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i1 %a to i64
   ret i64 %1
 }
 
 define i16 @sext_i8_to_i16(i8 %a) {
 ; LA32-LABEL: sext_i8_to_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.b $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i8_to_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i8 %a to i16
   ret i16 %1
 }
 
 define i32 @sext_i8_to_i32(i8 %a) {
 ; LA32-LABEL: sext_i8_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.b $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i8_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i8 %a to i32
   ret i32 %1
 }
 
 define i64 @sext_i8_to_i64(i8 %a) {
 ; LA32-LABEL: sext_i8_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.b $a0, $a0
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i8_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.b $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i8 %a to i64
   ret i64 %1
 }
 
 define i32 @sext_i16_to_i32(i16 %a) {
 ; LA32-LABEL: sext_i16_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.h $a0, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i16_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.h $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i16 %a to i32
   ret i32 %1
 }
 
 define i64 @sext_i16_to_i64(i16 %a) {
 ; LA32-LABEL: sext_i16_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ext.w.h $a0, $a0
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i16_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ext.w.h $a0, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i16 %a to i64
   ret i64 %1
 }
 
 define i64 @sext_i32_to_i64(i32 %a) {
 ; LA32-LABEL: sext_i32_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srai.w $a1, $a0, 31
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sext_i32_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a0, $a0, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = sext i32 %a to i64
   ret i64 %1
 }
 
 define i8 @zext_i1_to_i8(i1 %a) {
 ; LA32-LABEL: zext_i1_to_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i1_to_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i1 %a to i8
   ret i8 %1
 }
 
 define i16 @zext_i1_to_i16(i1 %a) {
 ; LA32-LABEL: zext_i1_to_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i1_to_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i1 %a to i16
   ret i16 %1
 }
 
 define i32 @zext_i1_to_i32(i1 %a) {
 ; LA32-LABEL: zext_i1_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i1_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i1 %a to i32
   ret i32 %1
 }
 
 define i64 @zext_i1_to_i64(i1 %a) {
 ; LA32-LABEL: zext_i1_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 1
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i1_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i1 %a to i64
   ret i64 %1
 }
 
 define i16 @zext_i8_to_i16(i8 %a) {
 ; LA32-LABEL: zext_i8_to_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 255
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i8_to_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 255
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i8 %a to i16
   ret i16 %1
 }
 
 define i32 @zext_i8_to_i32(i8 %a) {
 ; LA32-LABEL: zext_i8_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 255
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i8_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 255
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i8 %a to i32
   ret i32 %1
 }
 
 define i64 @zext_i8_to_i64(i8 %a) {
 ; LA32-LABEL: zext_i8_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a0, $a0, 255
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i8_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a0, $a0, 255
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i8 %a to i64
   ret i64 %1
 }
 
 define i32 @zext_i16_to_i32(i16 %a) {
 ; LA32-LABEL: zext_i16_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i16_to_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i16 %a to i32
   ret i32 %1
 }
 
 define i64 @zext_i16_to_i64(i16 %a) {
 ; LA32-LABEL: zext_i16_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i16_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i16 %a to i64
   ret i64 %1
 }
 
 define i64 @zext_i32_to_i64(i32 %a) {
 ; LA32-LABEL: zext_i32_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: zext_i32_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = zext i32 %a to i64
   ret i64 %1
 }
 
 define i1 @trunc_i8_to_i1(i8 %a) {
 ; LA32-LABEL: trunc_i8_to_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i8_to_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i8 %a to i1
   ret i1 %1
 }
 
 define i1 @trunc_i16_to_i1(i16 %a) {
 ; LA32-LABEL: trunc_i16_to_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i16_to_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i16 %a to i1
   ret i1 %1
 }
 
 define i1 @trunc_i32_to_i1(i32 %a) {
 ; LA32-LABEL: trunc_i32_to_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i32_to_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i32 %a to i1
   ret i1 %1
 }
 
 define i1 @trunc_i64_to_i1(i64 %a) {
 ; LA32-LABEL: trunc_i64_to_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i64_to_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i64 %a to i1
   ret i1 %1
 }
 
 define i8 @trunc_i16_to_i8(i16 %a) {
 ; LA32-LABEL: trunc_i16_to_i8:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i16_to_i8:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i16 %a to i8
   ret i8 %1
 }
 
 define i8 @trunc_i32_to_i8(i32 %a) {
 ; LA32-LABEL: trunc_i32_to_i8:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i32_to_i8:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i32 %a to i8
   ret i8 %1
 }
 
 define i8 @trunc_i64_to_i8(i64 %a) {
 ; LA32-LABEL: trunc_i64_to_i8:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i64_to_i8:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i64 %a to i8
   ret i8 %1
 }
 
 define i16 @trunc_i32_to_i16(i32 %a) {
 ; LA32-LABEL: trunc_i32_to_i16:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i32_to_i16:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i32 %a to i16
   ret i16 %1
 }
 
 define i16 @trunc_i64_to_i16(i64 %a) {
 ; LA32-LABEL: trunc_i64_to_i16:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i64_to_i16:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i64 %a to i16
   ret i16 %1
 }
 
 define i32 @trunc_i64_to_i32(i64 %a) {
 ; LA32-LABEL: trunc_i64_to_i32:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: trunc_i64_to_i32:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = trunc i64 %a to i32
   ret i32 %1
 }

llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'shl' LLVM IR: https://llvm.org/docs/LangRef.html#shl-instruction
 
 define i1 @shl_i1(i1 %x, i1 %y) {
 ; LA32-LABEL: shl_i1:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i1:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i1 %x, %y
   ret i1 %shl
 }
 
 define i8 @shl_i8(i8 %x, i8 %y) {
 ; LA32-LABEL: shl_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sll.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i8 %x, %y
   ret i8 %shl
 }
 
 define i16 @shl_i16(i16 %x, i16 %y) {
 ; LA32-LABEL: shl_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sll.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i16 %x, %y
   ret i16 %shl
 }
 
 define i32 @shl_i32(i32 %x, i32 %y) {
 ; LA32-LABEL: shl_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sll.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i32 %x, %y
   ret i32 %shl
 }
 
 define i64 @shl_i64(i64 %x, i64 %y) {
 ; LA32-LABEL: shl_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    xori $a3, $a2, 31
 ; LA32-NEXT:    srli.w $a4, $a0, 1
 ; LA32-NEXT:    srl.w $a3, $a4, $a3
 ; LA32-NEXT:    sll.w $a1, $a1, $a2
 ; LA32-NEXT:    or $a1, $a1, $a3
 ; LA32-NEXT:    addi.w $a3, $a2, -32
 ; LA32-NEXT:    slti $a4, $a3, 0
 ; LA32-NEXT:    maskeqz $a1, $a1, $a4
 ; LA32-NEXT:    sll.w $a5, $a0, $a3
 ; LA32-NEXT:    masknez $a4, $a5, $a4
 ; LA32-NEXT:    or $a1, $a1, $a4
 ; LA32-NEXT:    sll.w $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a2, $a3, 31
 ; LA32-NEXT:    and $a0, $a2, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sll.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i64 %x, %y
   ret i64 %shl
 }
 
 define i1 @shl_i1_3(i1 %x) {
 ; LA32-LABEL: shl_i1_3:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i1_3:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i1 %x, 3
   ret i1 %shl
 }
 
 define i8 @shl_i8_3(i8 %x) {
 ; LA32-LABEL: shl_i8_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i8_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i8 %x, 3
   ret i8 %shl
 }
 
 define i16 @shl_i16_3(i16 %x) {
 ; LA32-LABEL: shl_i16_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i16_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i16 %x, 3
   ret i16 %shl
 }
 
 define i32 @shl_i32_3(i32 %x) {
 ; LA32-LABEL: shl_i32_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i32_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i32 %x, 3
   ret i32 %shl
 }
 
 define i64 @shl_i64_3(i64 %x) {
 ; LA32-LABEL: shl_i64_3:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 3
 ; LA32-NEXT:    srli.w $a2, $a0, 29
 ; LA32-NEXT:    or $a1, $a1, $a2
 ; LA32-NEXT:    slli.w $a0, $a0, 3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: shl_i64_3:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i64 %x, 3
   ret i64 %shl
 }

llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'sub' LLVM IR: https://llvm.org/docs/LangRef.html#sub-instruction
 
 define i1 @sub_i1(i1 %x, i1 %y) {
 ; LA32-LABEL: sub_i1:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i1 %x, %y
   ret i1 %sub
 }
 
 define i8 @sub_i8(i8 %x, i8 %y) {
 ; LA32-LABEL: sub_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i8 %x, %y
   ret i8 %sub
 }
 
 define i16 @sub_i16(i16 %x, i16 %y) {
 ; LA32-LABEL: sub_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i16 %x, %y
   ret i16 %sub
 }
 
 define i32 @sub_i32(i32 %x, i32 %y) {
 ; LA32-LABEL: sub_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i32 %x, %y
   ret i32 %sub
 }
 
 ;; Match the pattern:
 ;; def : PatGprGpr_32<sub, SUB_W>;
 define signext i32 @sub_i32_sext(i32 %x, i32 %y) {
 ; LA32-LABEL: sub_i32_sext:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i32_sext:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i32 %x, %y
   ret i32 %sub
 }
 
 define i64 @sub_i64(i64 %x, i64 %y) {
 ; LA32-LABEL: sub_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a1, $a1, $a3
 ; LA32-NEXT:    sltu $a3, $a0, $a2
 ; LA32-NEXT:    sub.w $a1, $a1, $a3
 ; LA32-NEXT:    sub.w $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sub_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %sub = sub i64 %x, %y
   ret i64 %sub
 }

llvm/test/CodeGen/LoongArch/ir-instruction/xor.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; Exercise the 'xor' LLVM IR: https://llvm.org/docs/LangRef.html#xor-instruction
 
 define i1 @xor_i1(i1 %a, i1 %b) {
 ; LA32-LABEL: xor_i1:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i1:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i1 %a, %b
   ret i1 %r
 }
 
 define i8 @xor_i8(i8 %a, i8 %b) {
 ; LA32-LABEL: xor_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i8 %a, %b
   ret i8 %r
 }
 
 define i16 @xor_i16(i16 %a, i16 %b) {
 ; LA32-LABEL: xor_i16:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i16 %a, %b
   ret i16 %r
 }
 
 define i32 @xor_i32(i32 %a, i32 %b) {
 ; LA32-LABEL: xor_i32:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i32:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i32 %a, %b
   ret i32 %r
 }
 
 define i64 @xor_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: xor_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xor $a0, $a0, $a2
 ; LA32-NEXT:    xor $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i64 %a, %b
   ret i64 %r
 }
 
 define i1 @xor_i1_0(i1 %b) {
 ; LA32-LABEL: xor_i1_0:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i1_0:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i1 4, %b
   ret i1 %r
 }
 
 define i1 @xor_i1_5(i1 %b) {
 ; LA32-LABEL: xor_i1_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i1_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i1 5, %b
   ret i1 %r
 }
 
 define i8 @xor_i8_5(i8 %b) {
 ; LA32-LABEL: xor_i8_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i8_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i8 5, %b
   ret i8 %r
 }
 
 define i8 @xor_i8_257(i8 %b) {
 ; LA32-LABEL: xor_i8_257:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i8_257:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i8 257, %b
   ret i8 %r
 }
 
 define i16 @xor_i16_5(i16 %b) {
 ; LA32-LABEL: xor_i16_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i16_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i16 5, %b
   ret i16 %r
 }
 
 define i16 @xor_i16_0x1000(i16 %b) {
 ; LA32-LABEL: xor_i16_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i16_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i16 4096, %b
   ret i16 %r
 }
 
 define i16 @xor_i16_0x10001(i16 %b) {
 ; LA32-LABEL: xor_i16_0x10001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i16_0x10001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i16 65537, %b
   ret i16 %r
 }
 
 define i32 @xor_i32_5(i32 %b) {
 ; LA32-LABEL: xor_i32_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i32_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i32 5, %b
   ret i32 %r
 }
 
 define i32 @xor_i32_0x1000(i32 %b) {
 ; LA32-LABEL: xor_i32_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a1, 1
 ; LA32-NEXT:    xor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i32_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i32 4096, %b
   ret i32 %r
 }
 
 define i32 @xor_i32_0x100000001(i32 %b) {
 ; LA32-LABEL: xor_i32_0x100000001:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i32_0x100000001:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i32 4294967297, %b
   ret i32 %r
 }
 
 define i64 @xor_i64_5(i64 %b) {
 ; LA32-LABEL: xor_i64_5:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    xori $a0, $a0, 5
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i64_5:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    xori $a0, $a0, 5
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i64 5, %b
   ret i64 %r
 }
 
 define i64 @xor_i64_0x1000(i64 %b) {
 ; LA32-LABEL: xor_i64_0x1000:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    lu12i.w $a2, 1
 ; LA32-NEXT:    xor $a0, $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: xor_i64_0x1000:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    lu12i.w $a1, 1
 ; LA64-NEXT:    xor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
 entry:
   %r = xor i64 4096, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/not.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 define i8 @nor_i8(i8 %a, i8 %b) nounwind {
 ; LA32-LABEL: nor_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = or i8 %a, %b
   %neg = xor i8 %or, -1
   ret i8 %neg
 }
 
 define i16 @nor_i16(i16 %a, i16 %b) nounwind {
 ; LA32-LABEL: nor_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = or i16 %a, %b
   %neg = xor i16 %or, -1
   ret i16 %neg
 }
 
 define i32 @nor_i32(i32 %a, i32 %b) nounwind {
 ; LA32-LABEL: nor_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = or i32 %a, %b
   %neg = xor i32 %or, -1
   ret i32 %neg
 }
 
 define i64 @nor_i64(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: nor_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $a2
 ; LA32-NEXT:    nor $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = or i64 %a, %b
   %neg = xor i64 %or, -1
   ret i64 %neg
 }
 
 define i8 @nor_zero_i8(i8 %a) nounwind {
 ; LA32-LABEL: nor_zero_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_zero_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i8 %a, -1
   ret i8 %neg
 }
 
 define i16 @nor_zero_i16(i16 %a) nounwind {
 ; LA32-LABEL: nor_zero_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_zero_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i16 %a, -1
   ret i16 %neg
 }
 
 define i32 @nor_zero_i32(i32 %a) nounwind {
 ; LA32-LABEL: nor_zero_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_zero_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i32 %a, -1
   ret i32 %neg
 }
 
 define i64 @nor_zero_i64(i64 %a) nounwind {
 ; LA32-LABEL: nor_zero_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    nor $a0, $a0, $zero
 ; LA32-NEXT:    nor $a1, $a1, $zero
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: nor_zero_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    nor $a0, $a0, $zero
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i64 %a, -1
   ret i64 %neg
 }
 
 define i8 @orn_i8(i8 %a, i8 %b) nounwind {
 ; LA32-LABEL: orn_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    orn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: orn_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    orn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i8 %b, -1
   %or = or i8 %neg, %a
   ret i8 %or
 }
 
 define i16 @orn_i16(i16 %a, i16 %b) nounwind {
 ; LA32-LABEL: orn_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    orn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: orn_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    orn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i16 %b, -1
   %or = or i16 %neg, %a
   ret i16 %or
 }
 
 define i32 @orn_i32(i32 %a, i32 %b) nounwind {
 ; LA32-LABEL: orn_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    orn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: orn_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    orn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i32 %b, -1
   %or = or i32 %neg, %a
   ret i32 %or
 }
 
 define i64 @orn_i64(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: orn_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    orn $a0, $a0, $a2
 ; LA32-NEXT:    orn $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: orn_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    orn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i64 %b, -1
   %or = or i64 %neg, %a
   ret i64 %or
 }
 
 define i8 @andn_i8(i8 %a, i8 %b) nounwind {
 ; LA32-LABEL: andn_i8:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: andn_i8:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i8 %b, -1
   %and = and i8 %neg, %a
   ret i8 %and
 }
 
 define i16 @andn_i16(i16 %a, i16 %b) nounwind {
 ; LA32-LABEL: andn_i16:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: andn_i16:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i16 %b, -1
   %and = and i16 %neg, %a
   ret i16 %and
 }
 
 define i32 @andn_i32(i32 %a, i32 %b) nounwind {
 ; LA32-LABEL: andn_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andn $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: andn_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i32 %b, -1
   %and = and i32 %neg, %a
   ret i32 %and
 }
 
 define i64 @andn_i64(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: andn_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andn $a0, $a0, $a2
 ; LA32-NEXT:    andn $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: andn_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andn $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %neg = xor i64 %b, -1
   %and = and i64 %neg, %a
   ret i64 %and
 }

llvm/test/CodeGen/LoongArch/rotl-rotr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; TODO: Add optimization to ISD::ROTL
 
 define i32 @rotl_32(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotl_32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    ori $a2, $zero, 32
 ; LA32-NEXT:    sub.w $a1, $a2, $a1
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a2, $zero, $a1
 ; LA64-NEXT:    sll.w $a1, $a0, $a1
 ; LA64-NEXT:    srl.w $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i32 32, %y
   %b = shl i32 %x, %y
   %c = lshr i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i32 @rotr_32(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotr_32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i32 32, %y
   %b = lshr i32 %x, %y
   %c = shl i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i64 @rotl_64(i64 %x, i64 %y) nounwind {

 ; LA32-NEXT:    slti $a5, $t0, 0
 ; LA32-NEXT:    masknez $a6, $a7, $a5
 ; LA32-NEXT:    maskeqz $a3, $a3, $a5
 ; LA32-NEXT:    or $a3, $a3, $a6
 ; LA32-NEXT:    sll.w $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a2, $a4, 31
 ; LA32-NEXT:    and $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ori $a2, $zero, 64
 ; LA64-NEXT:    sub.d $a1, $a2, $a1
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i64 64, %y
   %b = shl i64 %x, %y
   %c = lshr i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64(i64 %x, i64 %y) nounwind {

 ; LA32-NEXT:    slti $a5, $t0, 0
 ; LA32-NEXT:    masknez $a6, $a7, $a5
 ; LA32-NEXT:    maskeqz $a3, $a3, $a5
 ; LA32-NEXT:    or $a3, $a3, $a6
 ; LA32-NEXT:    srl.w $a1, $a1, $a2
 ; LA32-NEXT:    srai.w $a2, $a4, 31
 ; LA32-NEXT:    and $a1, $a2, $a1
 ; LA32-NEXT:    or $a1, $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i64 64, %y
   %b = lshr i64 %x, %y
   %c = shl i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotl_32_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a1, $zero, $a1
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_32_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a2, $zero, $a1
 ; LA64-NEXT:    sll.w $a1, $a0, $a1
 ; LA64-NEXT:    srl.w $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i32 0, %y
   %and = and i32 %z, 31
   %b = shl i32 %x, %y
   %c = lshr i32 %x, %and
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotl_32_mask_and_63_and_31:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a1, $zero, $a1
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_32_mask_and_63_and_31:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a2, $zero, $a1
 ; LA64-NEXT:    sll.w $a1, $a0, $a1
 ; LA64-NEXT:    srl.w $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = and i32 %y, 63
   %b = shl i32 %x, %a
   %c = sub i32 0, %y
   %d = and i32 %c, 31
   %e = lshr i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }
 
 define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotl_32_mask_or_64_or_32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sub.w $a1, $zero, $a1
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_32_mask_or_64_or_32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a2, $zero, $a1
 ; LA64-NEXT:    sll.w $a1, $a0, $a1
 ; LA64-NEXT:    srl.w $a0, $a0, $a2
 ; LA64-NEXT:    or $a0, $a1, $a0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = or i32 %y, 64
   %b = shl i32 %x, %a
   %c = sub i32 0, %y
   %d = or i32 %c, 32
   %e = lshr i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }
 
 define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotr_32_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_32_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i32 0, %y
   %and = and i32 %z, 31
   %b = lshr i32 %x, %y
   %c = shl i32 %x, %and
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotr_32_mask_and_63_and_31:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_32_mask_and_63_and_31:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = and i32 %y, 63
   %b = lshr i32 %x, %a
   %c = sub i32 0, %y
   %d = and i32 %c, 31
   %e = shl i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }
 
 define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
 ; LA32-LABEL: rotr_32_mask_or_64_or_32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotr.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_32_mask_or_64_or_32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = or i32 %y, 64
   %b = lshr i32 %x, %a
   %c = sub i32 0, %y
   %d = or i32 %c, 32
   %e = shl i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }

 ; LA32-NEXT:    masknez $a1, $a1, $a5
 ; LA32-NEXT:    maskeqz $a4, $a4, $a5
 ; LA32-NEXT:    or $a1, $a4, $a1
 ; LA32-NEXT:    sll.w $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a2, $t0, 31
 ; LA32-NEXT:    and $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    move $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_64_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a1, $zero, $a1
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i64 0, %y
   %and = and i64 %z, 63
   %b = shl i64 %x, %y
   %c = lshr i64 %x, %and
   %d = or i64 %b, %c
   ret i64 %d
 }
 

 ; LA32-NEXT:    masknez $a1, $a1, $a6
 ; LA32-NEXT:    maskeqz $a5, $a5, $a6
 ; LA32-NEXT:    or $a1, $a5, $a1
 ; LA32-NEXT:    sll.w $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a2, $a4, 31
 ; LA32-NEXT:    and $a0, $a2, $a0
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    move $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_64_mask_and_127_and_63:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a1, $zero, $a1
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = and i64 %y, 127
   %b = shl i64 %x, %a
   %c = sub i64 0, %y
   %d = and i64 %c, 63
   %e = lshr i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; LA32-LABEL: rotl_64_mask_or_128_or_64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sll.w $a3, $a0, $a2
 ; LA32-NEXT:    sub.w $a0, $zero, $a2
 ; LA32-NEXT:    srl.w $a0, $a1, $a0
 ; LA32-NEXT:    move $a1, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_64_mask_or_128_or_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a1, $zero, $a1
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = or i64 %y, 128
   %b = shl i64 %x, %a
   %c = sub i64 0, %y
   %d = or i64 %c, 64
   %e = lshr i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }

 ; LA32-NEXT:    masknez $a0, $a0, $a5
 ; LA32-NEXT:    maskeqz $a4, $a4, $a5
 ; LA32-NEXT:    or $a0, $a4, $a0
 ; LA32-NEXT:    srl.w $a1, $a1, $a2
 ; LA32-NEXT:    srai.w $a2, $t0, 31
 ; LA32-NEXT:    and $a1, $a2, $a1
 ; LA32-NEXT:    or $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_64_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %z = sub i64 0, %y
   %and = and i64 %z, 63
   %b = lshr i64 %x, %y
   %c = shl i64 %x, %and
   %d = or i64 %b, %c
   ret i64 %d
 }
 

 ; LA32-NEXT:    masknez $a0, $a0, $a6
 ; LA32-NEXT:    maskeqz $a5, $a5, $a6
 ; LA32-NEXT:    or $a0, $a5, $a0
 ; LA32-NEXT:    srl.w $a1, $a1, $a2
 ; LA32-NEXT:    srai.w $a2, $a4, 31
 ; LA32-NEXT:    and $a1, $a2, $a1
 ; LA32-NEXT:    or $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_64_mask_and_127_and_63:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = and i64 %y, 127
   %b = lshr i64 %x, %a
   %c = sub i64 0, %y
   %d = and i64 %c, 63
   %e = shl i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; LA32-LABEL: rotr_64_mask_or_128_or_64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srl.w $a3, $a1, $a2
 ; LA32-NEXT:    sub.w $a1, $zero, $a2
 ; LA32-NEXT:    sll.w $a1, $a0, $a1
 ; LA32-NEXT:    move $a0, $a3
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_64_mask_or_128_or_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %a = or i64 %y, 128
   %b = lshr i64 %x, %a
   %c = sub i64 0, %y
   %d = or i64 %c, 64
   %e = shl i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i32 @rotri_i32(i32 %a) nounwind {
 ; LA32-LABEL: rotri_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotri.w $a0, $a0, 16
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotri_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotri.w $a0, $a0, 16
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i32 %a, 16
   %shr = lshr i32 %a, 16
   %or = or i32 %shl, %shr
   ret i32 %or
 }
 
 define i64 @rotri_i64(i64 %a) nounwind {
 ; LA32-LABEL: rotri_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    move $a2, $a0
 ; LA32-NEXT:    move $a0, $a1
 ; LA32-NEXT:    move $a1, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotri_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotri.d $a0, $a0, 32
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %shl = shl i64 %a, 32
   %shr = lshr i64 %a, 32
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 declare i32 @llvm.fshl.i32(i32, i32, i32)
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 declare i32 @llvm.fshr.i32(i32, i32, i32)
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define signext i32 @rotl_i32_fshl(i32 signext %a) nounwind {
 ; LA32-LABEL: rotl_i32_fshl:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotri.w $a0, $a0, 20
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_i32_fshl:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotri.w $a0, $a0, 20
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 12)
   ret i32 %or
 }
 
 define i64 @rotl_i64_fshl(i64 %a) nounwind {
 ; LA32-LABEL: rotl_i64_fshl:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srli.w $a2, $a1, 20
 ; LA32-NEXT:    slli.w $a3, $a0, 12
 ; LA32-NEXT:    or $a2, $a3, $a2
 ; LA32-NEXT:    srli.w $a0, $a0, 20
 ; LA32-NEXT:    slli.w $a1, $a1, 12
 ; LA32-NEXT:    or $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_i64_fshl:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotri.d $a0, $a0, 52
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 12)
   ret i64 %or
 }
 
 define signext i32 @rotr_i32_fshr(i32 signext %a) nounwind {
 ; LA32-LABEL: rotr_i32_fshr:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    rotri.w $a0, $a0, 12
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_i32_fshr:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a0, 20
 ; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 12
 ; LA64-NEXT:    or $a0, $a0, $a1
 ; LA64-NEXT:    addi.w $a0, $a0, 0
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 12)
   ret i32 %or
 }
 
 define i64 @rotr_i64_fshr(i64 %a) nounwind {
 ; LA32-LABEL: rotr_i64_fshr:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srli.w $a2, $a0, 12
 ; LA32-NEXT:    slli.w $a3, $a1, 20
 ; LA32-NEXT:    or $a2, $a3, $a2
 ; LA32-NEXT:    srli.w $a1, $a1, 12
 ; LA32-NEXT:    slli.w $a0, $a0, 20
 ; LA32-NEXT:    or $a1, $a0, $a1
 ; LA32-NEXT:    move $a0, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_i64_fshr:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotri.d $a0, $a0, 12
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 12)
   ret i64 %or
 }

llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 ;; This test checks that unnecessary masking of shift amount operands is
 ;; eliminated during instruction selection. The test needs to ensure that the
 ;; masking is not removed if it may affect the shift amount.
 
 define i32 @sll_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: sll_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sll_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sll.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 31
   %2 = shl i32 %a, %1
   ret i32 %2
 }
 
 define i32 @sll_non_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: sll_non_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a1, $a1, 15
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sll_non_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a1, $a1, 15
 ; LA64-NEXT:    sll.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 15
   %2 = shl i32 %a, %1
   ret i32 %2
 }
 
 define i32 @srl_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: srl_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srl_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srl.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 4095
   %2 = lshr i32 %a, %1
   ret i32 %2
 }
 
 define i32 @srl_non_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: srl_non_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a1, $a1, 7
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srl_non_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a1, $a1, 7
 ; LA64-NEXT:    srl.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 7
   %2 = lshr i32 %a, %1
   ret i32 %2
 }
 
 define i32 @sra_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: sra_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sra_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sra.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 65535
   %2 = ashr i32 %a, %1
   ret i32 %2
 }
 
 define i32 @sra_non_redundant_mask(i32 %a, i32 %b) {
 ; LA32-LABEL: sra_non_redundant_mask:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    andi $a1, $a1, 32
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sra_non_redundant_mask:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    andi $a1, $a1, 32
 ; LA64-NEXT:    sra.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = and i32 %b, 32
   %2 = ashr i32 %a, %1
   ret i32 %2
 }
 
 define i32 @sll_redundant_mask_zeros(i32 %a, i32 %b) {
 ; LA32-LABEL: sll_redundant_mask_zeros:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 1
 ; LA32-NEXT:    sll.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sll_redundant_mask_zeros:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 1
 ; LA64-NEXT:    sll.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i32 %b, 1
   %2 = and i32 %1, 30
   %3 = shl i32 %a, %2
   ret i32 %3
 }
 
 define i32 @srl_redundant_mask_zeros(i32 %a, i32 %b) {
 ; LA32-LABEL: srl_redundant_mask_zeros:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 2
 ; LA32-NEXT:    srl.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srl_redundant_mask_zeros:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 2
 ; LA64-NEXT:    srl.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i32 %b, 2
   %2 = and i32 %1, 28
   %3 = lshr i32 %a, %2
   ret i32 %3
 }
 
 define i32 @sra_redundant_mask_zeros(i32 %a, i32 %b) {
 ; LA32-LABEL: sra_redundant_mask_zeros:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    slli.w $a1, $a1, 3
 ; LA32-NEXT:    sra.w $a0, $a0, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sra_redundant_mask_zeros:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 3
 ; LA64-NEXT:    sra.w $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i32 %b, 3
   %2 = and i32 %1, 24
   %3 = ashr i32 %a, %2
   ret i32 %3
 }
 
 define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: sll_redundant_mask_zeros_i64:

 ; LA32-NEXT:    slti $a4, $a3, 0
 ; LA32-NEXT:    maskeqz $a1, $a1, $a4
 ; LA32-NEXT:    sll.w $a5, $a0, $a3
 ; LA32-NEXT:    masknez $a4, $a5, $a4
 ; LA32-NEXT:    or $a1, $a1, $a4
 ; LA32-NEXT:    sll.w $a0, $a0, $a2
 ; LA32-NEXT:    srai.w $a2, $a3, 31
 ; LA32-NEXT:    and $a0, $a2, $a0
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sll_redundant_mask_zeros_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 2
 ; LA64-NEXT:    sll.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i64 %b, 2
   %2 = and i64 %1, 60
   %3 = shl i64 %a, %2
   ret i64 %3
 }
 
 define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: srl_redundant_mask_zeros_i64:

 ; LA32-NEXT:    slti $a4, $a3, 0
 ; LA32-NEXT:    maskeqz $a0, $a0, $a4
 ; LA32-NEXT:    srl.w $a5, $a1, $a3
 ; LA32-NEXT:    masknez $a4, $a5, $a4
 ; LA32-NEXT:    or $a0, $a0, $a4
 ; LA32-NEXT:    srl.w $a1, $a1, $a2
 ; LA32-NEXT:    srai.w $a2, $a3, 31
 ; LA32-NEXT:    and $a1, $a2, $a1
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srl_redundant_mask_zeros_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 3
 ; LA64-NEXT:    srl.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i64 %b, 3
   %2 = and i64 %1, 56
   %3 = lshr i64 %a, %2
   ret i64 %3
 }
 
 define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: sra_redundant_mask_zeros_i64:

 ; LA32-NEXT:    slli.w $a4, $a1, 1
 ; LA32-NEXT:    sll.w $a3, $a4, $a3
 ; LA32-NEXT:    or $a0, $a0, $a3
 ; LA32-NEXT:    sra.w $a1, $a1, $a5
 ; LA32-NEXT:    maskeqz $a0, $a0, $a6
 ; LA32-NEXT:    masknez $a1, $a1, $a6
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    move $a1, $a2
-; LA32-NEXT:    jirl $zero, $ra, 0
+; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sra_redundant_mask_zeros_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    slli.d $a1, $a1, 4
 ; LA64-NEXT:    sra.d $a0, $a0, $a1
-; LA64-NEXT:    jirl $zero, $ra, 0
+; LA64-NEXT:    ret
   %1 = shl i64 %b, 4
   %2 = and i64 %1, 48
   %3 = ashr i64 %a, %2
   ret i64 %3
 }

llvm/test/CodeGen/LoongArch/vararg.ll

 ; LA64-FPELIM-NEXT:    st.d $a5, $sp, 56
 ; LA64-FPELIM-NEXT:    st.d $a4, $sp, 48
 ; LA64-FPELIM-NEXT:    st.d $a3, $sp, 40
 ; LA64-FPELIM-NEXT:    st.d $a2, $sp, 32
 ; LA64-FPELIM-NEXT:    addi.d $a1, $sp, 32
 ; LA64-FPELIM-NEXT:    st.d $a1, $sp, 8
 ; LA64-FPELIM-NEXT:    st.d $a0, $sp, 24
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 80
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va1:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -96
 ; LA64-WITHFP-NEXT:    .cfi_def_cfa_offset 96
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 16 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    .cfi_offset 1, -72
 ; LA64-WITHFP-NEXT:    .cfi_offset 22, -80
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 32
 ; LA64-WITHFP-NEXT:    .cfi_def_cfa 22, 64
 ; LA64-WITHFP-NEXT:    move $a0, $a1
 ; LA64-WITHFP-NEXT:    st.d $a7, $fp, 56
 ; LA64-WITHFP-NEXT:    st.d $a6, $fp, 48
 ; LA64-WITHFP-NEXT:    st.d $a5, $fp, 40
 ; LA64-WITHFP-NEXT:    st.d $a4, $fp, 32
 ; LA64-WITHFP-NEXT:    st.d $a3, $fp, 24
 ; LA64-WITHFP-NEXT:    st.d $a2, $fp, 16
 ; LA64-WITHFP-NEXT:    addi.d $a1, $fp, 16
 ; LA64-WITHFP-NEXT:    st.d $a1, $fp, -24
 ; LA64-WITHFP-NEXT:    st.d $a0, $fp, 8
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 96
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
   %va = alloca ptr, align 8
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va, align 8
   %argp.next = getelementptr inbounds i64, ptr %argp.cur, i32 1
   store ptr %argp.next, ptr %va, align 8
   %1 = load i64, ptr %argp.cur, align 8
   call void @llvm.va_end(ptr %va)
   ret i64 %1

 ; LA64-FPELIM-NEXT:    st.d $a5, $sp, 56
 ; LA64-FPELIM-NEXT:    st.d $a4, $sp, 48
 ; LA64-FPELIM-NEXT:    st.d $a3, $sp, 40
 ; LA64-FPELIM-NEXT:    st.d $a2, $sp, 32
 ; LA64-FPELIM-NEXT:    addi.d $a1, $sp, 32
 ; LA64-FPELIM-NEXT:    st.d $a1, $sp, 8
 ; LA64-FPELIM-NEXT:    st.d $a0, $sp, 24
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 80
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va1_va_arg:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -96
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 16 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 32
 ; LA64-WITHFP-NEXT:    move $a0, $a1
 ; LA64-WITHFP-NEXT:    st.d $a7, $fp, 56
 ; LA64-WITHFP-NEXT:    st.d $a6, $fp, 48
 ; LA64-WITHFP-NEXT:    st.d $a5, $fp, 40
 ; LA64-WITHFP-NEXT:    st.d $a4, $fp, 32
 ; LA64-WITHFP-NEXT:    st.d $a3, $fp, 24
 ; LA64-WITHFP-NEXT:    st.d $a2, $fp, 16
 ; LA64-WITHFP-NEXT:    addi.d $a1, $fp, 16
 ; LA64-WITHFP-NEXT:    st.d $a1, $fp, -24
 ; LA64-WITHFP-NEXT:    st.d $a0, $fp, 8
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 96
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
   %va = alloca ptr, align 8
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i64
   call void @llvm.va_end(ptr %va)
   ret i64 %1
 }
 
 ;; Ensure the adjustment when restoring the stack pointer using the frame

 ; LA64-FPELIM-NEXT:    move $sp, $a0
 ; LA64-FPELIM-NEXT:    bl notdead
 ; LA64-FPELIM-NEXT:    move $a0, $s0
 ; LA64-FPELIM-NEXT:    addi.d $sp, $fp, -32
 ; LA64-FPELIM-NEXT:    ld.d $s0, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 96
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va1_va_arg_alloca:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -96
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 16 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $s0, $sp, 8 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 32

 ; LA64-WITHFP-NEXT:    move $sp, $a0
 ; LA64-WITHFP-NEXT:    bl notdead
 ; LA64-WITHFP-NEXT:    move $a0, $s0
 ; LA64-WITHFP-NEXT:    addi.d $sp, $fp, -32
 ; LA64-WITHFP-NEXT:    ld.d $s0, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 96
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
   %va = alloca ptr, align 8
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i64
   %2 = alloca i8, i64 %1
   call void @notdead(ptr %2)
   call void @llvm.va_end(ptr %va)
   ret i64 %1
 }
 
 define void @va1_caller() nounwind {
 ; LA64-FPELIM-LABEL: va1_caller:
 ; LA64-FPELIM:       # %bb.0:
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, -16
 ; LA64-FPELIM-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-FPELIM-NEXT:    lu52i.d $a1, $zero, 1023
 ; LA64-FPELIM-NEXT:    ori $a2, $zero, 2
 ; LA64-FPELIM-NEXT:    bl va1
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 16
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va1_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -16
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 16
 ; LA64-WITHFP-NEXT:    lu52i.d $a1, $zero, 1023
 ; LA64-WITHFP-NEXT:    ori $a2, $zero, 2
 ; LA64-WITHFP-NEXT:    bl va1
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 16
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
   %1 = call i64 (ptr, ...) @va1(ptr undef, double 1.0, i64 2)
   ret void
 }
 
 ;; Ensure a named 2*GRLen argument is passed in a1 and a2, while the
 ;; vararg long double is passed in a4 and a5 (rather than a3 and a4)
 
 declare i64 @va_aligned_register(i64 %a, i128 %b, ...)

 ; LA64-FPELIM-NEXT:    lu32i.d $a0, 37355
 ; LA64-FPELIM-NEXT:    lu52i.d $a5, $a0, 1024
 ; LA64-FPELIM-NEXT:    ori $a0, $zero, 2
 ; LA64-FPELIM-NEXT:    ori $a1, $zero, 1111
 ; LA64-FPELIM-NEXT:    move $a2, $zero
 ; LA64-FPELIM-NEXT:    bl va_aligned_register
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 16
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va_aligned_register_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -16
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 16
 ; LA64-WITHFP-NEXT:    lu12i.w $a0, 335544
 ; LA64-WITHFP-NEXT:    ori $a0, $a0, 1311
 ; LA64-WITHFP-NEXT:    lu32i.d $a0, 335544
 ; LA64-WITHFP-NEXT:    lu52i.d $a4, $a0, -328
 ; LA64-WITHFP-NEXT:    lu12i.w $a0, -503317
 ; LA64-WITHFP-NEXT:    ori $a0, $a0, 2129
 ; LA64-WITHFP-NEXT:    lu32i.d $a0, 37355
 ; LA64-WITHFP-NEXT:    lu52i.d $a5, $a0, 1024
 ; LA64-WITHFP-NEXT:    ori $a0, $zero, 2
 ; LA64-WITHFP-NEXT:    ori $a1, $zero, 1111
 ; LA64-WITHFP-NEXT:    move $a2, $zero
 ; LA64-WITHFP-NEXT:    bl va_aligned_register
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 16
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
  %1 = call i64 (i64, i128, ...) @va_aligned_register(i64 2, i128 1111,
    fp128 0xLEB851EB851EB851F400091EB851EB851)
  ret void
 }
 
 ;; Check 2*GRLen values are aligned appropriately when passed on the stack
 ;; in a vararg call
 

 ; LA64-FPELIM-NEXT:    ori $a3, $zero, 12
 ; LA64-FPELIM-NEXT:    ori $a4, $zero, 13
 ; LA64-FPELIM-NEXT:    ori $a0, $zero, 1
 ; LA64-FPELIM-NEXT:    move $a6, $zero
 ; LA64-FPELIM-NEXT:    move $a7, $a0
 ; LA64-FPELIM-NEXT:    bl va_aligned_stack_callee
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 104 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 112
-; LA64-FPELIM-NEXT:    jirl $zero, $ra, 0
+; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va_aligned_stack_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -112
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 104 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 96 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 112
 ; LA64-WITHFP-NEXT:    ori $a0, $zero, 17

 ; LA64-WITHFP-NEXT:    ori $a4, $zero, 13
 ; LA64-WITHFP-NEXT:    ori $a0, $zero, 1
 ; LA64-WITHFP-NEXT:    move $a6, $zero
 ; LA64-WITHFP-NEXT:    move $a7, $a0
 ; LA64-WITHFP-NEXT:    bl va_aligned_stack_callee
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 96 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 104 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 112
-; LA64-WITHFP-NEXT:    jirl $zero, $ra, 0
+; LA64-WITHFP-NEXT:    ret
   %1 = call i32 (i32, ...) @va_aligned_stack_callee(i32 1, i32 11,
     i256 1000, i32 12, i32 13, i128 18446744073709551616, i32 14,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i64 15,
     [2 x i64] [i64 16, i64 17])
   ret void
 }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_function_name.ll.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Check that we accept functions with '$' in the name.
 
 ; RUN: llc -mtriple=loongarch32-unknown-linux < %s | FileCheck %s
 
 define hidden i32 @"_Z54bar$ompvariant$bar"() {
 ; CHECK-LABEL: _Z54bar$ompvariant$bar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori $a0, $zero, 2
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
 entry:
   ret i32 2
 }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected

 ; CHECK-NEXT:    st.w $a0, $fp, -24
 ; CHECK-NEXT:    ori $a0, $zero, 4
 ; CHECK-NEXT:    st.w $a0, $fp, -28
 ; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.w $fp, $sp, 24 # 4-byte Folded Reload
 ; CHECK-NEXT:    ld.w $ra, $sp, 28 # 4-byte Folded Reload
 ; CHECK-NEXT:    addi.w $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
 ;
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.w $sp, $sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    st.w $ra, $sp, 28 # 4-byte Folded Spill
 ; CHECK-NEXT:    st.w $fp, $sp, 24 # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset 1, -4

 ; CHECK-NEXT:    st.w $a0, $fp, -20
 ; CHECK-NEXT:    st.w $a1, $fp, -16
 ; CHECK-NEXT:    st.w $a2, $fp, -24
 ; CHECK-NEXT:    st.w $a3, $fp, -28
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.w $fp, $sp, 24 # 4-byte Folded Reload
 ; CHECK-NEXT:    ld.w $ra, $sp, 28 # 4-byte Folded Reload
 ; CHECK-NEXT:    addi.w $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected

 ; CHECK-NEXT:    st.w $a0, $fp, -24
 ; CHECK-NEXT:    ori $a0, $zero, 4
 ; CHECK-NEXT:    st.w $a0, $fp, -28
 ; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.w $fp, $sp, 24 # 4-byte Folded Reload
 ; CHECK-NEXT:    ld.w $ra, $sp, 28 # 4-byte Folded Reload
 ; CHECK-NEXT:    addi.w $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   store i32 0, ptr %1, align 4
   store i32 0, ptr %2, align 4
   %6 = load i32, ptr %2, align 4

 ; CHECK-NEXT:    st.w $a0, $fp, -20
 ; CHECK-NEXT:    st.w $a1, $fp, -16
 ; CHECK-NEXT:    st.w $a2, $fp, -24
 ; CHECK-NEXT:    st.w $a3, $fp, -28
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.w $fp, $sp, 24 # 4-byte Folded Reload
 ; CHECK-NEXT:    ld.w $ra, $sp, 28 # 4-byte Folded Reload
 ; CHECK-NEXT:    addi.w $sp, $sp, 32
-; CHECK-NEXT:    jirl $zero, $ra, 0
+; CHECK-NEXT:    ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
 
   store i32 0, ptr %1, align 4
   store i32 0, ptr @x, align 4