[LoongArch] Add codegen support for not

[xen0n]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

664

This is the same codegen as gcc, while I previously used NOR rj, zero (putting zero in rk position) in my QEMU TCG port.

I'm not sure which form is better or more consistent, because apparently they behave the same but usually we put zero in rk position (like with move i.e. move rd, rj == or rd, rj, zero).

665

nit: single space.

same below

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

664

Thank you for your reminder , I will change that.

665

Thanks, I will fix it.

[gonglingqin]

Address @xen0n's comments.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 } // Predicates = [IsLA64]
 
 def : PatGprGpr<and, AND>;
 def : PatGprImm<and, ANDI, uimm12>;
 def : PatGprGpr<or, OR>;
 def : PatGprImm<or, ORI, uimm12>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprImm<xor, XORI, uimm12>;
+def : Pat<(not GPR:$rj), (NOR GPR:$rj, R0)>;
+def : Pat<(not (or GPR:$rj, GPR:$rk)), (NOR GPR:$rj, GPR:$rk)>;
+def : Pat<(or GPR:$rj, (not GPR:$rk)), (ORN GPR:$rj, GPR:$rk)>;
+def : Pat<(and GPR:$rj, (not GPR:$rk)), (ANDN GPR:$rj, GPR:$rk)>;
 
 /// FrameIndex calculations
 let Predicates = [IsLA32] in {
 def : Pat<(AddLike (i32 BaseAddr:$rj), simm12:$imm12),
           (ADDI_W (i32 BaseAddr:$rj), simm12:$imm12)>;
 } // Predicates = [IsLA32]
 let Predicates = [IsLA64] in {
 def : Pat<(AddLike (i64 BaseAddr:$rj), simm12:$imm12),

llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll

 }
 
 define i64 @caller_small_scalar_ret() nounwind {
 ; CHECK-LABEL: caller_small_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    bl callee_small_scalar_ret
-; CHECK-NEXT:    addi.w $a2, $zero, -1
-; CHECK-NEXT:    xor $a1, $a1, $a2
 ; CHECK-NEXT:    addi.w $a2, $zero, -2
 ; CHECK-NEXT:    xor $a0, $a0, $a2
-; CHECK-NEXT:    or $a0, $a0, $a1
+; CHECK-NEXT:    orn $a0, $a0, $a1
 ; CHECK-NEXT:    sltui $a0, $a0, 1
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    jirl $zero, $ra, 0
   %1 = call i128 @callee_small_scalar_ret()
   %2 = icmp eq i128 -2, %1
   %3 = zext i1 %2 to i64
   ret i64 %3

llvm/test/CodeGen/LoongArch/not.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
+
+define i8 @nor_i8(i8 %a, i8 %b) nounwind {
+; LA32-LABEL: nor_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %or = or i8 %a, %b
+  %neg = xor i8 %or, -1
+  ret i8 %neg
+}
+
+define i16 @nor_i16(i16 %a, i16 %b) nounwind {
+; LA32-LABEL: nor_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %or = or i16 %a, %b
+  %neg = xor i16 %or, -1
+  ret i16 %neg
+}
+
+define i32 @nor_i32(i32 %a, i32 %b) nounwind {
+; LA32-LABEL: nor_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %or = or i32 %a, %b
+  %neg = xor i32 %or, -1
+  ret i32 %neg
+}
+
+define i64 @nor_i64(i64 %a, i64 %b) nounwind {
+; LA32-LABEL: nor_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $a2
+; LA32-NEXT:    nor $a1, $a1, $a3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %or = or i64 %a, %b
+  %neg = xor i64 %or, -1
+  ret i64 %neg
+}
+
+define i8 @nor_zero_i8(i8 %a) nounwind {
+; LA32-LABEL: nor_zero_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_zero_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i8 %a, -1
+  ret i8 %neg
+}
+
+define i16 @nor_zero_i16(i16 %a) nounwind {
+; LA32-LABEL: nor_zero_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_zero_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i16 %a, -1
+  ret i16 %neg
+}
+
+define i32 @nor_zero_i32(i32 %a) nounwind {
+; LA32-LABEL: nor_zero_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_zero_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i32 %a, -1
+  ret i32 %neg
+}
+
+define i64 @nor_zero_i64(i64 %a) nounwind {
+; LA32-LABEL: nor_zero_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    nor $a0, $a0, $zero
+; LA32-NEXT:    nor $a1, $a1, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: nor_zero_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    nor $a0, $a0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i64 %a, -1
+  ret i64 %neg
+}
+
+define i8 @orn_i8(i8 %a, i8 %b) nounwind {
+; LA32-LABEL: orn_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    orn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: orn_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    orn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i8 %b, -1
+  %or = or i8 %neg, %a
+  ret i8 %or
+}
+
+define i16 @orn_i16(i16 %a, i16 %b) nounwind {
+; LA32-LABEL: orn_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    orn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: orn_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    orn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i16 %b, -1
+  %or = or i16 %neg, %a
+  ret i16 %or
+}
+
+define i32 @orn_i32(i32 %a, i32 %b) nounwind {
+; LA32-LABEL: orn_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    orn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: orn_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    orn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i32 %b, -1
+  %or = or i32 %neg, %a
+  ret i32 %or
+}
+
+define i64 @orn_i64(i64 %a, i64 %b) nounwind {
+; LA32-LABEL: orn_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    orn $a0, $a0, $a2
+; LA32-NEXT:    orn $a1, $a1, $a3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: orn_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    orn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i64 %b, -1
+  %or = or i64 %neg, %a
+  ret i64 %or
+}
+
+define i8 @andn_i8(i8 %a, i8 %b) nounwind {
+; LA32-LABEL: andn_i8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: andn_i8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i8 %b, -1
+  %and = and i8 %neg, %a
+  ret i8 %and
+}
+
+define i16 @andn_i16(i16 %a, i16 %b) nounwind {
+; LA32-LABEL: andn_i16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: andn_i16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i16 %b, -1
+  %and = and i16 %neg, %a
+  ret i16 %and
+}
+
+define i32 @andn_i32(i32 %a, i32 %b) nounwind {
+; LA32-LABEL: andn_i32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andn $a0, $a0, $a1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: andn_i32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i32 %b, -1
+  %and = and i32 %neg, %a
+  ret i32 %and
+}
+
+define i64 @andn_i64(i64 %a, i64 %b) nounwind {
+; LA32-LABEL: andn_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    andn $a0, $a0, $a2
+; LA32-NEXT:    andn $a1, $a1, $a3
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: andn_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    andn $a0, $a0, $a1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %neg = xor i64 %b, -1
+  %and = and i64 %neg, %a
+  ret i64 %and
+}