Update llvm.experimental.patchpoint to use opaque pointer for target.

[vext01]

Summary

I wanted to check that patchpoints still work with opaque pointers, since there is (was) an i8* function pointer in the signature. They do work!

This change updates the stackmaps/patchpoints documentation so that it doesn't mention old-style pointers. Note that some of the varargs type qualifiers erroneously had a trailing *. e.g. call void (i64, i32, ...)* @... shouldn't have a star.

I've also made changes to the tests so that the target operand of patchpoint calls is now a ptr. I've not touched any other pointers in those tests unless strictly necessary (sometimes I had to change other pointers due to the "you can only use ptr in opaque pointers mode" error. It's not clear to me why sometimes it's ok to mix typed and opaque pointers, and other times not...)

[nikic]

I've also made changes to the tests so that the target operand of patchpoint calls is now a ptr. I've not touched any other pointers in those tests unless strictly necessary (sometimes I had to change other pointers due to the "you can only use ptr in opaque pointers mode" error. It's not clear to me why sometimes it's ok to mix typed and opaque pointers, and other times not...)

Please always update all pointers in the file. It happens to work if the first used pointer type is opaque, but tests really shouldn't mix different pointers...

[vext01]

As requested, revised diff updates all pointers to opaque pointers in the test files that I've touched.

All tests passing locally.

[nikic]

LGTM

llvm/docs/StackMaps.rst

 current function. We disallow overlapping stack map shadows so that
 the runtime does not need to consider this corner case.
 
 For example, a stack map with 8 byte shadow:
 
 .. code-block:: llvm
 
   call void @runtime()
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 77, i32 8,
-                                                         i64* %ptr)
-  %val = load i64* %ptr
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 77, i32 8,
+                                                        ptr %ptr)
+  %val = load i64, ptr %ptr
   %add = add i64 %val, 3
   ret i64 %add
 
 May require one byte of nop-padding:
 
 .. code-block:: none
 
   0x00 callq _runtime

 
 Syntax:
 """""""
 
 ::
 
       declare void
         @llvm.experimental.patchpoint.void(i64 <id>, i32 <numBytes>,
-                                           i8* <target>, i32 <numArgs>, ...)
+                                           ptr <target>, i32 <numArgs>, ...)
       declare i64
         @llvm.experimental.patchpoint.i64(i64 <id>, i32 <numBytes>,
-                                          i8* <target>, i32 <numArgs>, ...)
+                                          ptr <target>, i32 <numArgs>, ...)
 
 Overview:
 """""""""
 
 The '``llvm.experimental.patchpoint.*``' intrinsics creates a function
 call to the specified ``<target>`` and records the location of specified
 values in the stack map.
 

 patching is not allowed. The runtime must patch all reserved bytes,
 padding with nops if necessary.
 
 This example shows a patch point reserving 15 bytes, with one argument
 in $rdi, and a return value in $rax per native calling convention:
 
 .. code-block:: llvm
 
-  %target = inttoptr i64 -281474976710654 to i8*
-  %val = call i64 (i64, i32, ...)*
+  %target = inttoptr i64 -281474976710654 to ptr
+  %val = call i64 (i64, i32, ...)
            @llvm.experimental.patchpoint.i64(i64 78, i32 15,
-                                             i8* %target, i32 1, i64* %ptr)
+                                             ptr %target, i32 1, ptr %ptr)
   %add = add i64 %val, 3
   ret i64 %add
 
 May generate:
 
 .. code-block:: none
 
   0x00 movabsq $0xffff000000000002, %r11 <--- patch point address
   0x0a callq   *%r11
   0x0d nop
   0x0e nop                               <--- end of reserved 15-bytes
   0x0f addq    $0x3, %rax
   0x10 movl    %rax, 8(%rsp)
 
 Note that no stack map locations will be recorded. If the patched code
 sequence does not need arguments fixed to specific calling convention
 registers, then the ``anyregcc`` convention may be used:
 
 .. code-block:: none
 
   %val = call anyregcc @llvm.experimental.patchpoint(i64 78, i32 15,
-                                                     i8* %target, i32 1,
-                                                     i64* %ptr)
+                                                     ptr %target, i32 1,
+                                                     ptr %ptr)
 
 The stack map now indicates the location of the %ptr argument and
 return value:
 
 .. code-block:: none
 
   Stack Map: ID=78, Loc0=%r9 Loc1=%r8
 

 while Indirect locations handle register spills.
 
 For example:
 
 .. code-block:: none
 
   entry:
     %a = alloca i64...
-    llvm.experimental.stackmap(i64 <ID>, i32 <shadowBytes>, i64* %a)
+    llvm.experimental.stackmap(i64 <ID>, i32 <shadowBytes>, ptr %a)
 
 The runtime can determine this alloca's relative location on the
 stack immediately after compilation, or at any time thereafter. This
 differs from Register and Indirect locations, because the runtime can
 only read the values in those locations when execution reaches the
 instruction address of the stack map.
 
 This functionality requires LLVM to treat entry-block allocas

llvm/test/Analysis/CallGraph/non-leaf-intrinsics.ll

 ; RUN: opt -S -print-callgraph -disable-output < %s 2>&1 | FileCheck %s
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, ptr, i32, i32, ...)
 
 define private void @f() {
   ret void
 }
 
-define void @calls_statepoint(i8 addrspace(1)* %arg) gc "statepoint-example" {
+define void @calls_statepoint(ptr addrspace(1) %arg) gc "statepoint-example" {
 entry:
-  %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
-  %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* elementtype(void ()) @f, i32 0, i32 0, i32 0, i32 0) ["gc-live"(i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg), "deopt" (i32 0, i32 0, i32 0, i32 10, i32 0)]
+  %safepoint_token = call token (i64, i32, ptr, i32, i32, ...)
+  @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, ptr elementtype(void ()) @f, i32 0, i32 0, i32 0, i32 0) ["gc-live"(ptr addrspace(1) %arg, ptr addrspace(1) %arg, ptr addrspace(1) %arg, ptr addrspace(1) %arg), "deopt" (i32 0, i32 0, i32 0, i32 10, i32 0)]
   ret void
 }
 
 define void @calls_patchpoint() {
 entry:
-  %c = bitcast void()* @f to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %c, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, ptr @f, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }
 
 
 ; CHECK: Call graph node <<null function>>
 ; CHECK:  CS<None> calls function 'f'
 
 ; CHECK: Call graph node for function: 'calls_patchpoint'
 ; CHECK-NEXT:  CS<[[addr_1:[^>]+]]> calls external node
 
 ; CHECK: Call graph node for function: 'calls_statepoint'
 ; CHECK-NEXT:  CS<[[addr_0:[^>]+]]> calls external node

llvm/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll

 ; RUN: opt -S -disable-output -passes=print-lcg < %s 2>&1 | FileCheck %s
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, ptr, i32, i32, ...)
 
 define private void @f() {
   ret void
 }
 
-define void @calls_statepoint(i8 addrspace(1)* %arg) gc "statepoint-example" {
+define void @calls_statepoint(ptr addrspace(1) %arg) gc "statepoint-example" {
 ; CHECK: Edges in function: calls_statepoint
 ; CHECK-NEXT:  -> f
 entry:
-  %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
-  %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* elementtype(void ()) @f, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg), "deopt" (i32 0, i32 0, i32 0, i32 10, i32 0)]
+  %safepoint_token = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, ptr elementtype(void ()) @f, i32 0, i32 0, i32 0, i32 0) ["gc-live" (ptr addrspace(1) %arg, ptr addrspace(1) %arg, ptr addrspace(1) %arg, ptr addrspace(1) %arg), "deopt" (i32 0, i32 0, i32 0, i32 10, i32 0)]
   ret void
 }
 
 define void @calls_patchpoint() {
 ; CHECK:  Edges in function: calls_patchpoint
 ; CHECK-NEXT:    -> f
 entry:
-  %c = bitcast void()* @f to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %c, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, ptr @f, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-anyregcc-crash.ll

 ; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
 ;
 ; Check that misuse of anyregcc results in a compile time error.
 
 ; CHECK: error: ran out of registers during register allocation
 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                         i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, ptr inttoptr (i64 0 to ptr), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                 i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32)
   ret i64 %result
 }
 
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/AArch64/arm64-anyregcc.ll

 ; CHECK-NEXT:   .byte 4
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, ptr null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access1
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
+define i64 @property_access1(ptr %obj) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access2
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access3
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 29
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long -8
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, ptr %f, i32 0, ptr %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
 ; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14

 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
+define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test2
 ; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14

 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
+define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef

 ; CHECK-NEXT: .byte  1
 ; CHECK-NEXT: .byte 0
 ; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;

 ; CHECK-NEXT: .byte 0
 ; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 29
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long -88
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll

 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
 
 ; Test that scratch registers are spilled around patchpoints
 ; CHECK: InlineAsm End
 ; CHECK-NEXT: mov x{{[0-9]+}}, x16
 ; CHECK-NEXT: mov x{{[0-9]+}}, x17
 ; CHECK-NEXT: Ltmp
 ; CHECK-NEXT: nop
-define void @clobberScratch(i32* %p) {
-  %v = load i32, i32* %p
+define void @clobberScratch(ptr %p) {
+  %v = load i32, ptr %p
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v)
-  store i32 %v, i32* %p
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 5, i32 20, ptr null, i32 0, ptr %p, i32 %v)
+  store i32 %v, ptr %p
   ret void
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
 

llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll

 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen:
 ; FAST:        str x{{.+}}, [sp]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
-  %resolveCall2 = inttoptr i64 281474417671919 to i8*
-  %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
-  %resolveCall3 = inttoptr i64 244837814038255 to i8*
-  tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
+  %resolveCall2 = inttoptr i64 281474417671919 to ptr
+  %result = tail call webkit_jscc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr %resolveCall2, i32 2, i64 %p4, i64 %p2)
+  %resolveCall3 = inttoptr i64 244837814038255 to ptr
+  tail call webkit_jscc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, ptr %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen2:
 ; CHECK:       mov w[[REG:[0-9]+]], #6

 ; FAST-NEXT:   str [[REG1]], [sp]
 ; FAST-NEXT:   str [[REG2]], [sp, #16]
 ; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov  x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
-  %call = inttoptr i64 281474417671919 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
+  %call = inttoptr i64 281474417671919 to ptr
+  %result = call webkit_jscc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, ptr %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
 ; CHECK:       mov  w[[REG:[0-9]+]], #10

 ; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST-NEXT:   str [[REG4]], [sp, #36]
 ; FAST-NEXT:   str [[REG5]], [sp, #48]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
-  %call = inttoptr i64 281474417671919 to i8*
-  %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
+  %call = inttoptr i64 281474417671919 to ptr
+  %result = call webkit_jscc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, ptr %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
   ret i64 %result
 }
 
 ; CHECK-LABEL: test_i16:
 ; CHECK: ldrh [[BREG:w[0-9]+]], [sp]
 ; CHECK: add {{w[0-9]+}}, w0, [[BREG]]
 define webkit_jscc zeroext i16 @test_i16(i16 zeroext %a, i16 zeroext %b) {
   %sum = add i16 %a, %b
   ret i16 %sum
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/AArch64/arm64-patchpoint.ll

 ; CHECK-NEXT:  movk x16, #48879, lsl #16
 ; CHECK-NEXT:  movk x16, #51966
 ; CHECK-NEXT:  blr  x16
 ; CHECK:       mov  x16, #244834610708480
 ; CHECK-NEXT:  movk x16, #48879, lsl #16
 ; CHECK-NEXT:  movk x16, #51967
 ; CHECK-NEXT:  blr  x16
 ; CHECK:       ret
-  %resolveCall2 = inttoptr i64 244837814094590 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
-  %resolveCall3 = inttoptr i64 244837814094591 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  %resolveCall2 = inttoptr i64 244837814094590 to ptr
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, ptr %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %resolveCall3 = inttoptr i64 244837814094591 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 20, ptr %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
 ; Caller frame metadata with stackmaps. This should not be optimized
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
 ; CHECK:       sub sp, sp, #48
 ; CHECK-NEXT: .cfi_def_cfa_offset 48
 ; CHECK-NEXT:  stp x29, x30, [sp, #32]
 ; CHECK-NEXT:  add x29, sp, #32
 ; CHECK:       Ltmp
 ; CHECK:       add sp, sp, #48
 ; CHECK:       ret
 
 define void @caller_meta_leaf() {
 entry:
   %metadata = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata
-  store i64 12, i64* %metadata
-  store i64 13, i64* %metadata
-  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  store i64 11, ptr %metadata
+  store i64 12, ptr %metadata
+  store i64 13, ptr %metadata
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, ptr %metadata)
   ret void
 }
 
 ; Test patchpoints reusing the same TargetConstant.
 ; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
 ; There is no way to verify this, since it depends on memory allocation.
 ; But I think it's useful to include as a working example.
-define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
+define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, ptr %tmp33, i64 %tmp79) {
 entry:
   %tmp80 = add i64 %tmp79, -16
-  %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64, i64* %tmp81, align 8
+  %tmp81 = inttoptr i64 %tmp80 to ptr
+  %tmp82 = load i64, ptr %tmp81, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64, i64* %tmp33, align 8
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, ptr %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
-  %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64, i64* %tmp85, align 8
+  %tmp85 = inttoptr i64 %tmp84 to ptr
+  %tmp86 = load i64, ptr %tmp85, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
 ; Test small patchpoints that don't emit calls.
 define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: small_patchpoint_codegen:
 ; CHECK:      Ltmp
 ; CHECK:      nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: ldp
 ; CHECK-NEXT: ret
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
 

llvm/test/CodeGen/AArch64/arm64-stackmap.ll

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2
 
 define void @constantargs() {
 entry:
-  %0 = inttoptr i64 244837814094590 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296, i128 66, i128 4294967297)
+  %0 = inttoptr i64 244837814094590 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 20, ptr %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296, i128 66, i128 4294967297)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_osrinline
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
-  call void inttoptr (i64 244837814094590 to void ()*)()
+  call void inttoptr (i64 244837814094590 to ptr)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.

 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
-  %thunk = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b)
+  %thunk = inttoptr i64 244837814094590 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 20, ptr %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
 ; CHECK-LABEL:  .long   L{{.*}}-_propertyRead
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ;
 ; FIXME: There are currently no stackmap entries. After moving to
 ; AnyRegCC, we will have entries for the object and return value.
-define i64 @propertyRead(i64* %obj) {
+define i64 @propertyRead(ptr %obj) {
 entry:
-  %resolveRead = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj)
+  %resolveRead = inttoptr i64 244837814094590 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr %resolveRead, i32 1, ptr %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK-LABEL:  .long   L{{.*}}-_propertyWrite
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
+define void @propertyWrite(i64 %dummy1, ptr %obj, i64 %dummy2, i64 %a) {
 entry:
-  %resolveWrite = inttoptr i64 244837814094590 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  %resolveWrite = inttoptr i64 244837814094590 to ptr
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, ptr %resolveWrite, i32 2, ptr %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsVoidCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define void @jsVoidCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 244837814094590 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 20, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsIntCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define i64 @jsIntCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 244837814094590 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 20, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 28 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 28
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 29
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, ptr null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 23 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledStackMapValue

 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{.*}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -{{.*}}
 define void @floats(float %f, double %g) {
   %ff = alloca float
   %gg = alloca double
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
-    double 1.5, float %f, double %g, float* %ff, double* %gg)
+    double 1.5, float %f, double %g, ptr %ff, ptr %gg)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/AArch64/stackmap-liveness.ll

 ; CHECK-NEXT:   .byte 8
 ; LiveOut Entry 1: SP
 ; CHECK-NEXT:   .short 31
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .byte 8
 ; Align
 ; CHECK-NEXT:   .p2align  3
   %1 = select i1 %c, i64 1, i64 2
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0)
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, ptr null, i32 0)
   ret i64 %1
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/AArch64/stackmap.ll

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   3
 
 define void @constantargs() {
 entry:
-  %0 = inttoptr i64 12345 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 16, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1, i128 66, i128 4294967297)
+  %0 = inttoptr i64 12345 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 16, ptr %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1, i128 66, i128 4294967297)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK-LABEL:  .word   .L{{.*}}-osrinline
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
-  call void inttoptr (i64 -559038737 to void ()*)()
+  call void inttoptr (i64 -559038737 to ptr)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.

 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
-  %thunk = inttoptr i64 3735928559 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 16, i8* %thunk, i32 0, i64 %a, i64 %b)
+  %thunk = inttoptr i64 3735928559 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 16, ptr %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
 ; CHECK-LABEL:  .word   .L{{.*}}-propertyRead
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
-define i64 @propertyRead(i64* %obj) {
+define i64 @propertyRead(ptr %obj) {
 entry:
-  %resolveRead = inttoptr i64 3735928559 to i8*
-  %result = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 16, i8* %resolveRead, i32 1, i64* %obj)
+  %resolveRead = inttoptr i64 3735928559 to ptr
+  %result = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 16, ptr %resolveRead, i32 1, ptr %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK-LABEL:  .word   .L{{.*}}-propertyWrite
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
+define void @propertyWrite(i64 %dummy1, ptr %obj, i64 %dummy2, i64 %a) {
 entry:
-  %resolveWrite = inttoptr i64 3735928559 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 16, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  %resolveWrite = inttoptr i64 3735928559 to ptr
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 16, ptr %resolveWrite, i32 2, ptr %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .word   .L{{.*}}-jsVoidCall
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define void @jsVoidCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 3735928559 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 16, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 3735928559 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 16, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .word   .L{{.*}}-jsIntCall
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .hword  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{[0-9]+}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define i64 @jsIntCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 3735928559 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 16, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 3735928559 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 16, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 28 stack map entries.
 ;
 ; CHECK-LABEL:  .word .L{{.*}}-spilledValue
 ; CHECK-NEXT:   .hword 0
 ; CHECK-NEXT:   .hword 28
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect RBP + ...
 ; CHECK:        .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .hword 8
 ; CHECK-NEXT:   .hword 29
 ; CHECK-NEXT:   .hword 0
 ; CHECK-NEXT:   .word
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, ptr null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 30 stack map entries.
 ;
 ; CHECK-LABEL:  .word .L{{.*}}-spilledStackMapValue

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  29
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word
 define void @directFrameIdx() {
 entry:
   %metadata1 = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata1
-  store i64 12, i64* %metadata1
-  store i64 13, i64* %metadata1
-  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
+  store i64 11, ptr %metadata1
+  store i64 12, ptr %metadata1
+  store i64 13, ptr %metadata1
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, ptr %metadata1)
   %metadata2 = alloca i8, i32 4, align 8
   %metadata3 = alloca i16, i32 4, align 8
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 4, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 4, ptr null, i32 0, ptr %metadata2, ptr %metadata3)
   ret void
 }
 
 ; Test a 64-bit ID.
 ;
 ; CHECK:        .xword 4294967295
 ; CHECK-LABEL:  .word .L{{.*}}-longid
 ; CHECK:        .xword 4294967296
 ; CHECK-LABEL:  .word .L{{.*}}-longid
 ; CHECK:        .xword 9223372036854775807
 ; CHECK-LABEL:  .word .L{{.*}}-longid
 ; CHECK:        .xword -1
 ; CHECK-LABEL:  .word .L{{.*}}-longid
 define void @longid() {
 entry:
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, ptr null, i32 0)
   ret void
 }
 
 ; Map a value when R11 is the only free register.
 ; The scratch register should not be used for a live stackmap value.
 ;
 ; CHECK-LABEL:  .word .L{{.*}}-clobberLR
 ; CHECK-NEXT:   .hword 0

 ; A stack frame which needs to be realigned at runtime (to meet alignment 
 ; criteria for values on the stack) does not have a fixed frame size. 
 ; CHECK-LABEL:  .word .L{{.*}}-needsStackRealignment
 ; CHECK-NEXT:   .hword 0
 ; 0 locations
 ; CHECK-NEXT:   .hword 0
 define void @needsStackRealignment() {
   %val = alloca i64, i32 3, align 128
-  tail call void (...) @escape_values(i64* %val)
+  tail call void (...) @escape_values(ptr %val)
 ; Note: Adding any non-constant to the stackmap would fail because we
 ; expected to be able to address off the frame pointer.  In a realigned
 ; frame, we must use the stack pointer instead.  This is a separate bug.
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0)
   ret void
 }
 declare void @escape_values(...)
 

 ; CHECK-NEXT:   .hword  8
 ; CHECK-NEXT:   .hword  {{.*}}
 ; CHECK-NEXT:   .hword  0
 ; CHECK-NEXT:   .word   -{{.*}}
 define void @floats(float %f, double %g) {
   %ff = alloca float
   %gg = alloca double
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
-    double 1.5, float %f, double %g, float* %ff, double* %gg)
+    double 1.5, float %f, double %g, ptr %ff, ptr %gg)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses the liveout register mask
 # machine operands correctly.
 
 --- |
 
   define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
   entry:
-    %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
+    %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, ptr null, i32 2, i64 %p1, i64 %p2)
     ret void
   }
 
-  declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+  declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
 
 ...
 ---
 name:            small_patchpoint_codegen
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll

 ; RUN: not llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 ;
 ; Check that misuse of anyregcc results in a compile time error.
 
 ; CHECK: error: ran out of registers during register allocation
 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                         i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                         i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                         i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 32,
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, ptr inttoptr (i64 0 to ptr), i32 32,
                 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
                 i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
                 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
                 i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32)
   ret i64 %result
 }
 
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/PowerPC/ppc64-anyregcc.ll

 ; CHECK-NEXT:   .byte 4
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, ptr null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
+define i64 @property_access1(ptr %obj) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 31
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 112
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, ptr %f, i32 0, ptr %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14

 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
+define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14

 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
+define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
+  %f = inttoptr i64 281474417671919 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]

 ; CHECK-NEXT: .byte  1
 ; CHECK-NEXT: .byte 0
 ; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled

 ; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 31
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long 136
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll

 ; CHECK-BE-NEXT: ld 12, 0(12)
 ; CHECK-NEXT: mtctr 12
 ; CHECK-NEXT: bctrl
 ; CHECK-LE-NEXT: ld 2, 24(1)
 ; CHECK-BE-NEXT: ld 2, 40(1)
 
 ; CHECK: blr
 
-  %resolveCall2 = inttoptr i64 244837814094590 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
-  %resolveCall3 = inttoptr i64 244837814094591 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 40, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  %resolveCall2 = inttoptr i64 244837814094590 to ptr
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, ptr %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %resolveCall3 = inttoptr i64 244837814094591 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 40, ptr %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
 ; Caller frame metadata with stackmaps. This should not be optimized
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
 ; CHECK-BE: stdu 1, -80(1)
 ; CHECK-LE: stdu 1, -64(1)
 ; CHECK: Ltmp
 ; CHECK-BE: addi 1, 1, 80
 ; CHECK-LE: addi 1, 1, 64
 ; CHECK: blr
 
 define void @caller_meta_leaf() {
 entry:
   %metadata = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata
-  store i64 12, i64* %metadata
-  store i64 13, i64* %metadata
-  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  store i64 11, ptr %metadata
+  store i64 12, ptr %metadata
+  store i64 13, ptr %metadata
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, ptr %metadata)
   ret void
 }
 
 ; Test patchpoints reusing the same TargetConstant.
 ; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
 ; There is no way to verify this, since it depends on memory allocation.
 ; But I think it's useful to include as a working example.
-define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
+define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, ptr %tmp33, i64 %tmp79) {
 entry:
   %tmp80 = add i64 %tmp79, -16
-  %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64, i64* %tmp81, align 8
+  %tmp81 = inttoptr i64 %tmp80 to ptr
+  %tmp82 = load i64, ptr %tmp81, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 48, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64, i64* %tmp33, align 8
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 48, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, ptr %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
-  %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64, i64* %tmp85, align 8
+  %tmp85 = inttoptr i64 %tmp84 to ptr
+  %tmp86 = load i64, ptr %tmp85, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 48, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 48, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
 ; Test small patchpoints that don't emit calls.
 define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: small_patchpoint_codegen:
 ; CHECK:      Ltmp
 ; CHECK:      nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NEXT: nop
 ; CHECK-NOT:  nop
 ; CHECK: blr
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
 ; Trivial symbolic patchpoint codegen.
 
 declare i64 @foo(i64 %p1, i64 %p2)
 define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) {
 entry:
 ; CHECK-LABEL: trivial_symbolic_patchpoint_codegen:
 ; CHECK:       bl foo
 ; CHECK-NEXT:  nop
 ; CHECK-NEXT:  nop
 ; CHECK-NOT:   nop
 ; CHECK:       blr
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 12, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, ptr, i32, ...)
+  @llvm.experimental.patchpoint.i64(i64 9, i32 12, ptr @foo, i32 2, i64 %p1, i64 %p2)
   ret i64 %result
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
 

llvm/test/CodeGen/PowerPC/ppc64-stackmap.ll

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2
 
 define void @constantargs() {
 entry:
-  %0 = inttoptr i64 244837814094590 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 40, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296, i128 66, i128 4294967297)
+  %0 = inttoptr i64 244837814094590 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 40, ptr %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296, i128 66, i128 4294967297)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[osrinline_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
-  call void inttoptr (i64 244837814094590 to void ()*)()
+  call void inttoptr (i64 244837814094590 to ptr)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.

 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
-  %thunk = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 40, i8* %thunk, i32 0, i64 %a, i64 %b)
+  %thunk = inttoptr i64 244837814094590 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 40, ptr %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
 ; CHECK:  .long   .L{{.*}}-.L[[propertyRead_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ;
 ; FIXME: There are currently no stackmap entries. After moving to
 ; AnyRegCC, we will have entries for the object and return value.
-define i64 @propertyRead(i64* %obj) {
+define i64 @propertyRead(ptr %obj) {
 entry:
-  %resolveRead = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %resolveRead, i32 1, i64* %obj)
+  %resolveRead = inttoptr i64 244837814094590 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, ptr %resolveRead, i32 1, ptr %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK:  .long   .L{{.*}}-.L[[propertyWrite_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
+define void @propertyWrite(i64 %dummy1, ptr %obj, i64 %dummy2, i64 %a) {
 entry:
-  %resolveWrite = inttoptr i64 244837814094590 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 40, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  %resolveWrite = inttoptr i64 244837814094590 to ptr
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 40, ptr %resolveWrite, i32 2, ptr %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[jsVoidCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define void @jsVoidCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 244837814094590 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 40, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[jsIntCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define i64 @jsIntCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 244837814094590 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 40, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 28 stack map entries.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[spilledValue_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 28
 ;
 ; Check that at least one is a spilled entry from r31.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 31
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 40, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 40, ptr null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 30 stack map entries.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[spilledStackMapValue_BEGIN]]

 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{.*}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   {{.*}}
 define void @floats(float %f, double %g) {
   %ff = alloca float
   %gg = alloca double
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
-    double 1.5, float %f, double %g, float* %ff, double* %gg)
+    double 1.5, float %f, double %g, ptr %ff, ptr %gg)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/SystemZ/anyregcc-novec.ll

;CHECK-NOT: std
   %a13 = call double asm sideeffect "", "={f13}"() nounwind
   %a14 = call double asm sideeffect "", "={f14}"() nounwind
   %a15 = call double asm sideeffect "", "={f15}"() nounwind
   call anyregcc void @foo()
   call void asm sideeffect "", "{f0},{f1},{f2},{f3},{f4},{f5},{f6},{f7},{f8},{f9},{f10},{f11},{f12},{f13},{f14},{f15}"(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7, double %a8, double %a9, double %a10, double %a11, double %a12, double %a13, double %a14, double %a15)
   ret void
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/SystemZ/anyregcc-vec.ll

;CHECK-NOT: vst
   %a29 = call <2 x i64> asm sideeffect "", "={v29}"() nounwind
   %a30 = call <2 x i64> asm sideeffect "", "={v30}"() nounwind
   %a31 = call <2 x i64> asm sideeffect "", "={v31}"() nounwind
   call anyregcc void @foo()
   call void asm sideeffect "", "{v0},{v1},{v2},{v3},{v4},{v5},{v6},{v7},{v8},{v9},{v10},{v11},{v12},{v13},{v14},{v15},{v16},{v17},{v18},{v19},{v20},{v21},{v22},{v23},{v24},{v25},{v26},{v27},{v28},{v29},{v30},{v31}"(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> %a3, <2 x i64> %a4, <2 x i64> %a5, <2 x i64> %a6, <2 x i64> %a7, <2 x i64> %a8, <2 x i64> %a9, <2 x i64> %a10, <2 x i64> %a11, <2 x i64> %a12, <2 x i64> %a13, <2 x i64> %a14, <2 x i64> %a15, <2 x i64> %a16, <2 x i64> %a17, <2 x i64> %a18, <2 x i64> %a19, <2 x i64> %a20, <2 x i64> %a21, <2 x i64> %a22, <2 x i64> %a23, <2 x i64> %a24, <2 x i64> %a25, <2 x i64> %a26, <2 x i64> %a27, <2 x i64> %a28, <2 x i64> %a29, <2 x i64> %a30, <2 x i64> %a31)
   ret void
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/SystemZ/anyregcc.ll

 ; CHECK-NEXT:   .byte 4
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, i8* null, i32 2, i32 1, i32 2, i64 3)
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, ptr null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:        .long   .L{{.*}}-property_access1
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
+define i64 @property_access1(ptr %obj) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, i8* %f, i32 1, i8* %obj)
+  %f = inttoptr i64 12297829382473034410 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:        .long   .L{{.*}}-property_access2
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, i8* %f, i32 1, i64* %obj)
+  %f = inttoptr i64 12297829382473034410 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, ptr %f, i32 1, ptr %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK:        .long   .L{{.*}}-property_access3
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2

 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 15
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long  160
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
-  %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, i8* %f, i32 0, i64* %obj)
+  %f = inttoptr i64 12297829382473034410 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, ptr %f, i32 0, ptr %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK:        .long   .L{{.*}}-anyreg_test1
 ; CHECK-NEXT:   .short  0
 ; 13 locations
 ; CHECK-NEXT:   .short  13

 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
+define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, i8* %f, i32 12, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
+  %f = inttoptr i64 12297829382473034410 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, ptr %f, i32 12, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK:        .long   .L{{.*}}-anyreg_test2
 ; CHECK-NEXT:   .short  0
 ; 13 locations
 ; CHECK-NEXT:   .short  13

 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
-define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
+define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12) nounwind ssp uwtable {
 entry:
-  %f = inttoptr i64 12297829382473034410 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
+  %f = inttoptr i64 12297829382473034410 to ptr
+  %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK:      .long  .L{{.*}}-patchpoint_spilldef

 ; CHECK-NEXT: .byte  1
 ; CHECK-NEXT: .byte  0
 ; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 3
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;

 ; CHECK-NEXT: .byte  0
 ; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 15
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/SystemZ/patchpoint-invoke.ll

 ; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck %s
 
 ; Test invoking of patchpoints
 ;
-define i64 @patchpoint_invoke(i64 %p1, i64 %p2) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define i64 @patchpoint_invoke(i64 %p1, i64 %p2) personality ptr @__gxx_personality_v0 {
 entry:
 ; CHECK-LABEL: patchpoint_invoke:
 ; CHECK-NEXT:  [[FUNC_BEGIN:.L.*]]:
 ; CHECK-NEXT: .cfi_startproc
 ; CHECK:      .cfi_lsda 0, [[EXCEPTION_LABEL:.L[^ ]*]]
 ; CHECK:      aghi %r15, -160
 
 ; Unfortunately, hardcode the name of the label that begins the patchpoint:
 ; CHECK:      .Ltmp0:
 ; CHECK:      llilf   %r1, 559038736
 ; CHECK-NEXT: basr    %r14, %r1
 ; CHECK-NEXT: bcr     0, %r0
 ; CHECK-NEXT: [[PP_END:.L.*]]:
 ; CHECK:      br %r14
-  %resolveCall = inttoptr i64 559038736 to i8*
-  %result = invoke i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 10, i8* %resolveCall, i32 1, i64 %p1, i64 %p2)
+  %resolveCall = inttoptr i64 559038736 to ptr
+  %result = invoke i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 10, ptr %resolveCall, i32 1, i64 %p1, i64 %p2)
             to label %success unwind label %threw
 
 success:
   ret i64 %result
 
 threw:
-  %0 = landingpad { i8*, i32 }
-          catch i8* null
+  %0 = landingpad { ptr, i32 }
+          catch ptr null
   ret i64 0
 }
 
 ; Verify that the exception table was emitted:
 ; CHECK:      [[EXCEPTION_LABEL]]:
 ; CHECK-NEXT: .byte 255
 ; CHECK-NEXT: .byte 0
 ; CHECK-NEXT: .uleb128 .Lttbase{{[0-9]+}}-[[TTBASEREF:.Lttbaseref[0-9]+]]

 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 1
 ; CHECK-NEXT:   .quad patchpoint_invoke
 
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
 declare i32 @__gxx_personality_v0(...)

llvm/test/CodeGen/SystemZ/patchpoint.ll

 ; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck %s
 
 ; Trivial patchpoint codegen
 ;
 define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: trivial_patchpoint_codegen:
 ; CHECK:       llilf   %r1, 559038736
 ; CHECK-NEXT:  basr    %r14, %r1
 ; CHECK-NEXT:  bcr     0, %r0
 ; CHECK:       lgr     [[REG0:%r[0-9]+]], %r2
 ; CHECK:       llilf   %r1, 559038737
 ; CHECK-NEXT:  basr    %r14, %r1
 ; CHECK-NEXT:  bcr     0, %r0
 ; CHECK:       lgr     %r2, [[REG0:%r[0-9]+]]
 ; CHECK:       br      %r14
-  %resolveCall2 = inttoptr i64 559038736 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 10, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
-  %resolveCall3 = inttoptr i64 559038737 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 10, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
+  %resolveCall2 = inttoptr i64 559038736 to ptr
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 10, ptr %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
+  %resolveCall3 = inttoptr i64 559038737 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 10, ptr %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
 ; Trivial symbolic patchpoint codegen.
 ;
 
 declare i64 @foo(i64 %p1, i64 %p2)
 define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) {
 entry:
 ; CHECK-LABEL: trivial_symbolic_patchpoint_codegen:
 ; CHECK:       brasl   %r14, foo@PLT
 ; CHECK-NEXT:  bcr     0, %r0
 ; CHECK:       br      %r14
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 8, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 8, ptr @foo, i32 2, i64 %p1, i64 %p2)
   ret i64 %result
 }
 
 
 ; Caller frame metadata with stackmaps. This should not be optimized
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
 ; CHECK: aghi  %r15, -184
 ; CHECK: .Ltmp
 ; CHECK: lmg   %r14, %r15, 296(%r15)
 ; CHECK: br    %r14
 define void @caller_meta_leaf() {
 entry:
   %metadata = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata
-  store i64 12, i64* %metadata
-  store i64 13, i64* %metadata
-  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
+  store i64 11, ptr %metadata
+  store i64 12, ptr %metadata
+  store i64 13, ptr %metadata
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, ptr %metadata)
   ret void
 }
 
 ; Test patchpoints reusing the same TargetConstant.
 ; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
 ; There is no way to verify this, since it depends on memory allocation.
 ; But I think it's useful to include as a working example.
-define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
+define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, ptr %tmp33, i64 %tmp79) {
 entry:
   %tmp80 = add i64 %tmp79, -16
-  %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64, i64* %tmp81, align 8
+  %tmp81 = inttoptr i64 %tmp80 to ptr
+  %tmp82 = load i64, ptr %tmp81, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 6, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64, i64* %tmp33, align 8
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 30, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
+  %tmp83 = load i64, ptr %tmp33, align 8
   %tmp84 = add i64 %tmp83, -24
-  %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64, i64* %tmp85, align 8
+  %tmp85 = inttoptr i64 %tmp84 to ptr
+  %tmp86 = load i64, ptr %tmp85, align 8
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 6, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 30, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 30, ptr null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
   ret i64 10
 }
 
 ; Test small patchpoints that don't emit calls.
 define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: small_patchpoint_codegen:
 ; CHECK:      .Ltmp
 ; CHECK:      bcr 0, %r0
 ; CHECK:      br %r14
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 2, i8* null, i32 2, i64 %p1, i64 %p2)
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 2, ptr null, i32 2, i64 %p1, i64 %p2)
   ret void
 }
 
 ; Test large target address.
 define i64 @large_target_address_patchpoint_codegen() {
 entry:
 ; CHECK-LABEL: large_target_address_patchpoint_codegen:
 ; CHECK:        llilf   %r1, 2566957755
 ; CHECK-NEXT:   iihf    %r1, 1432778632
 ; CHECK-NEXT:   basr    %r14, %r1
-  %resolveCall2 = inttoptr i64 6153737369414576827 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, i8* %resolveCall2, i32 0)
+  %resolveCall2 = inttoptr i64 6153737369414576827 to ptr
+  %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, ptr %resolveCall2, i32 0)
   ret i64 %result
 }
 
 ; Test that the number of bytes is reflected in the instruction size and
 ; therefore cause relaxation of the initial branch.
 define void @patchpoint_size(i32 %Arg) {
 ; CHECK-LABEL: patchpoint_size:
 ; CHECK: # %bb.0:
 ; CHECK-NEXT: stmg    %r14, %r15, 112(%r15)
 ; CHECK-NEXT: .cfi_offset %r14, -48
 ; CHECK-NEXT: .cfi_offset %r15, -40
 ; CHECK-NEXT: aghi    %r15, -160
 ; CHECK-NEXT: .cfi_def_cfa_offset 320
 ; CHECK-NEXT: chi     %r2, 0
 ; CHECK-NEXT: jge     .LBB6_2
   %c = icmp eq i32 %Arg, 0
   br i1 %c, label %block0, label %patch1
 
 block0:
   call i64 @foo(i64 0, i64 0)
   br label %exit
 
 patch1:
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 65536, i8* null, i32 0)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 65536, ptr null, i32 0)
   br label %exit
 
 exit:
   ret void
 }
 
 define void @stackmap_size(i32 %Arg) {
 ; CHECK-LABEL: stackmap_size:
stackmap1:
   br label %exit
 
 exit:
   ret void
 }
 
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/SystemZ/stackmap.ll

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   3
 
 define void @constantargs() {
 entry:
-  %0 = inttoptr i64 12345 to i8*
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 14, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1, i128 66, i128 4294967297)
+  %0 = inttoptr i64 12345 to ptr
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 14, ptr %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1, i128 66, i128 4294967297)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK:        .long   .L{{.*}}-osrinline
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
-  call void inttoptr (i64 -559038737 to void ()*)()
+  call void inttoptr (i64 -559038737 to ptr)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.

 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
-  %thunk = inttoptr i64 -559038737 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 14, i8* %thunk, i32 0, i64 %a, i64 %b)
+  %thunk = inttoptr i64 -559038737 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 14, ptr %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
 ; CHECK:        .long   .L{{.*}}-propertyRead
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define i64 @propertyRead(i64* %obj) {
+define i64 @propertyRead(ptr %obj) {
 entry:
-  %resolveRead = inttoptr i64 -559038737 to i8*
-  %result = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, i8* %resolveRead, i32 1, i64* %obj)
+  %resolveRead = inttoptr i64 -559038737 to ptr
+  %result = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, ptr %resolveRead, i32 1, ptr %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK:        .long   .L{{.*}}-propertyWrite
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
+define void @propertyWrite(i64 %dummy1, ptr %obj, i64 %dummy2, i64 %a) {
 entry:
-  %resolveWrite = inttoptr i64 -559038737 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 14, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
+  %resolveWrite = inttoptr i64 -559038737 to ptr
+  call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 14, ptr %resolveWrite, i32 2, ptr %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:        .long   .L{{.*}}-jsVoidCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define void @jsVoidCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 -559038737 to i8*
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 14, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 -559038737 to ptr
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 14, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:        .long   .L{{.*}}-jsIntCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
+define i64 @jsIntCall(i64 %dummy1, ptr %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
-  %resolveCall = inttoptr i64 -559038737 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 14, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
+  %resolveCall = inttoptr i64 -559038737 to ptr
+  %result = call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 14, ptr %resolveCall, i32 2, ptr %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 17 stack map entries.
 ;
 ; CHECK:        .long .L{{.*}}-spilledValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 17
 ;
 ; Check that at least one is a spilled entry from the parameter area.
 ; Location: Indirect r15 + XX
 ; CHECK:        .byte  3
 ; CHECK-NEXT:   .byte  0
 ; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 15
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
 entry:
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 14, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 14, ptr null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 17 stack map entries.
 ;
 ; CHECK:        .long .L{{.*}}-spilledStackMapValue

 define void @spillSubReg(i64 %arg) #0 {
 bb:
   br i1 undef, label %bb1, label %bb2
 
 bb1:
   unreachable
 
 bb2:
-  %tmp = load i64, i64* inttoptr (i64 140685446136880 to i64*)
+  %tmp = load i64, ptr inttoptr (i64 140685446136880 to ptr)
   br i1 undef, label %bb16, label %bb17
 
 bb16:
   unreachable
 
 bb17:
   %tmp32 = trunc i64 %tmp to i32
   br i1 undef, label %bb60, label %bb61

 ; CHECK-NEXT:   .byte   0
 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  15
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 define void @directFrameIdx() {
 entry:
   %metadata1 = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata1
-  store i64 12, i64* %metadata1
-  store i64 13, i64* %metadata1
-  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
+  store i64 11, ptr %metadata1
+  store i64 12, ptr %metadata1
+  store i64 13, ptr %metadata1
+  call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, ptr %metadata1)
   %metadata2 = alloca i8, i32 4, align 8
   %metadata3 = alloca i16, i32 4, align 8
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 6, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 17, i32 6, ptr null, i32 0, ptr %metadata2, ptr %metadata3)
   ret void
 }
 
 ; Test a 64-bit ID.
 ;
 ; CHECK:        .quad 4294967295
 ; CHECK:        .long .L{{.*}}-longid
 ; CHECK:        .quad 4294967296
 ; CHECK:        .long .L{{.*}}-longid
 ; CHECK:        .quad 9223372036854775807
 ; CHECK:        .long .L{{.*}}-longid
 ; CHECK:        .quad -1
 ; CHECK:        .long .L{{.*}}-longid
 define void @longid() {
 entry:
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0)
-  tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, ptr null, i32 0)
+  tail call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 -1, i32 0, ptr null, i32 0)
   ret void
 }
 
 ; Map a value when %r0 and %r1 are the only free registers.
 ; The scratch registers should not be used for a live stackmap value.
 ;
 ; CHECK:        .long .L{{.*}}-clobberScratch
 ; CHECK-NEXT:   .short 0

 ; A stack frame which needs to be realigned at runtime (to meet alignment
 ; criteria for values on the stack) does not have a fixed frame size.
 ; CHECK:        .long .L{{.*}}-needsStackRealignment
 ; CHECK-NEXT:   .short 0
 ; 0 locations
 ; CHECK-NEXT:   .short 0
 define void @needsStackRealignment() {
   %val = alloca i64, i32 3, align 128
-  tail call void (...) @escape_values(i64* %val)
+  tail call void (...) @escape_values(ptr %val)
 ; Note: Adding any non-constant to the stackmap would fail because we
 ; expected to be able to address off the frame pointer.  In a realigned
 ; frame, we must use the stack pointer instead.  This is a separate bug.
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0)
   ret void
 }
 declare void @escape_values(...)
 

 ; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{.*}}
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   {{.*}}
 define void @floats(float %f, double %g) {
   %ff = alloca float
   %gg = alloca double
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
-    double 1.5, float %f, double %g, float* %ff, double* %gg)
+    double 1.5, float %f, double %g, ptr %ff, ptr %gg)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
+declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

llvm/test/CodeGen/X86/patchpoint-verifiable.mir

 # RUN: llc -mtriple=x86_64-apple-darwin -stop-after branch-folder -start-after branch-folder -o - %s | FileCheck %s
 # This test verifies that the machine verifier won't report an error when
 # verifying the PATCHPOINT instruction.
 
 --- |
 
   define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
   entry:
-    %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
+    %result = tail call i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, ptr null, i32 2, i64 %p1, i64 %p2)
     ret void
   }
 
-  declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+  declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)
 
 ...
 ---
 name:            small_patchpoint_codegen
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/CodeGen/X86/selectiondag-patchpoint-legalize.ll

 ;       Location[10]
 ;         CHECK-NEXT: .byte   1
 ;         CHECK-NEXT: .byte   0
 ;         CHECK-NEXT: .short  1
 ;         CHECK-NEXT: .short  {{.*}}
 ;         CHECK-NEXT: .short  0
 ;         CHECK-NEXT: .long   0
 
-@p32 = external global i8 addrspace(270)*
+@p32 = external global ptr addrspace(270)
 
 %struct1 = type {i32, i64}
 %struct2 = type {i1, i1, i1}
 
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
 
-define dso_local i32 @main(i32 %argc, i8** %argv) {
+define dso_local i32 @main(i32 %argc, ptr %argv) {
 entry:
   %i1reg = icmp eq i32 %argc, 5
   %i7reg = zext i1 %i1reg to i7
   %halfreg = sitofp i32 %argc to half
-  %ptr32 = load i8 addrspace(270)*, i8 addrspace(270)** @p32
+  %ptr32 = load ptr addrspace(270), ptr @p32
   %structreg1 = insertvalue %struct1 zeroinitializer, i32 %argc, 0
   %structreg2 = insertvalue %struct2 zeroinitializer, i1 %i1reg, 0
-  call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(
+  call void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(
     i64 0,
     i32 0,
-    i8* null,
+    ptr null,
     i32 0,
     i1 %i1reg,
     i7 22,
     i7 %i7reg,
     half 1.0,
     half %halfreg,
     i128 66,
     ; FIXME: fix and test vectors. At the moment even legally sized vectors
     ; are broken:
     ; https://github.com/llvm/llvm-project/issues/55613
     ;
     ; FIXME: test non-constant i128 once these are fixed:
     ;  - https://github.com/llvm/llvm-project/issues/26431
     ;  - https://github.com/llvm/llvm-project/issues/55957
-    i8 addrspace(270)* %ptr32,
+    ptr addrspace(270) %ptr32,
     ; FIXME: The stackmap record generated for structs is incorrect:
     ;  - https://github.com/llvm/llvm-project/issues/55649
     ;  - https://github.com/llvm/llvm-project/issues/55957
     %struct1 zeroinitializer,
     %struct1 %structreg1,
     %struct2 zeroinitializer,
     %struct2 %structreg2)
   ret i32 0
 }