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Differential D131257

[docs][AArch64] Label Features with Arm ARM Names
ClosedPublic

Authored by lenary on Aug 5 2022, 6:43 AM.

Details

Reviewers
dmgreen
pratlucas
tmatheson
Commits
rGb20fe2c25b17: [docs][AArch64] Label Features with Arm ARM Names
Summary

This patch adds the names of the Arm Architecture Reference Manual (ARM)
features to the corresponding Subtarget Features in the AArch64 backend
and target parser.

The aim of this is to make it clearer what architectural features a
subtarget feature might enable (so, which features a CPU must provide to
support that subtarget feature), and so make it easier to add new CPUs
in the future.

Diff Detail

Event Timeline

lenary created this revision.Aug 5 2022, 6:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2022, 6:43 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
lenary requested review of this revision.Aug 5 2022, 6:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2022, 6:43 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
lenary added reviewers: dmgreen, pratlucas, tmatheson.Aug 5 2022, 6:44 AM
Harbormaster completed remote builds in B179507: Diff 450282.Aug 5 2022, 7:34 AM
dmgreen accepted this revision.Aug 8 2022, 12:24 AM

LGTM. Looks like a useful addition. D127812 has need of some of these same FEAT_ names.

llvm/include/llvm/Support/AArch64TargetParser.h
34–35

The reference I have mentions FEAT_FP and FEAT_AdvSIMD.

llvm/lib/Target/AArch64/AArch64.td
322

Should this be FEAT_MPAM?

This revision is now accepted and ready to land.Aug 8 2022, 12:24 AM
lenary marked 2 inline comments as done.Aug 8 2022, 3:42 AM
lenary added inline comments.
llvm/include/llvm/Support/AArch64TargetParser.h
34–35

Updates incoming.

llvm/lib/Target/AArch64/AArch64.td
322

Updates incoming.

lenary updated this revision to Diff 450752.Aug 8 2022, 3:44 AM
lenary marked 2 inline comments as done.
Harbormaster completed remote builds in B179876: Diff 450752.Aug 8 2022, 5:46 AM
This revision was landed with ongoing or failed builds.Aug 9 2022, 10:46 AM
Closed by commit rGb20fe2c25b17: [docs][AArch64] Label Features with Arm ARM Names (authored by Archibald Elliott <archibald.elliott@arm.com>). · Explain Why
This revision was automatically updated to reflect the committed changes.
lenary added a commit: rGb20fe2c25b17: [docs][AArch64] Label Features with Arm ARM Names.

Revision Contents

PathSize
llvm/
include/
llvm/
Support/
85 lines
lib/
Target/
AArch64/
158 lines

Diff 451210

llvm/include/llvm/Support/AArch64TargetParser.h

Show All 19 Lines
// FIXME:This should be made into class design,to avoid dupplication. // FIXME:This should be made into class design,to avoid dupplication.
namespace llvm { namespace llvm {
class Triple; class Triple;
namespace AArch64 { namespace AArch64 {
// Arch extension modifiers for CPUs. // Arch extension modifiers for CPUs. These are labelled with their Arm ARM
// feature name (though the canonical reference for those is AArch64.td)
enum ArchExtKind : uint64_t { enum ArchExtKind : uint64_t {
AEK_INVALID = 0, AEK_INVALID = 0,
AEK_NONE = 1, AEK_NONE = 1,
AEK_CRC = 1 << 1, AEK_CRC = 1 << 1, // FEAT_CRC32
AEK_CRYPTO = 1 << 2, AEK_CRYPTO = 1 << 2,
AEK_FP = 1 << 3, AEK_FP = 1 << 3, // FEAT_FP
dmgreenUnsubmitted
Done
ReplyInline Actions

The reference I have mentions FEAT_FP and FEAT_AdvSIMD.

dmgreen: The reference I have mentions FEAT_FP and FEAT_AdvSIMD.
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

Updates incoming.

lenary: Updates incoming.
AEK_SIMD = 1 << 4, AEK_SIMD = 1 << 4, // FEAT_AdvSIMD
AEK_FP16 = 1 << 5, AEK_FP16 = 1 << 5, // FEAT_FP16
AEK_PROFILE = 1 << 6, AEK_PROFILE = 1 << 6, // FEAT_SPE
AEK_RAS = 1 << 7, AEK_RAS = 1 << 7, // FEAT_RAS, FEAT_RASv1p1
AEK_LSE = 1 << 8, AEK_LSE = 1 << 8, // FEAT_LSE
AEK_SVE = 1 << 9, AEK_SVE = 1 << 9, // FEAT_SVE
AEK_DOTPROD = 1 << 10, AEK_DOTPROD = 1 << 10, // FEAT_DotProd
AEK_RCPC = 1 << 11, AEK_RCPC = 1 << 11, // FEAT_LRCPC
AEK_RDM = 1 << 12, AEK_RDM = 1 << 12, // FEAT_RDM
AEK_SM4 = 1 << 13, AEK_SM4 = 1 << 13, // FEAT_SM4, FEAT_SM3
AEK_SHA3 = 1 << 14, AEK_SHA3 = 1 << 14, // FEAT_SHA3, FEAT_SHA512
AEK_SHA2 = 1 << 15, AEK_SHA2 = 1 << 15, // FEAT_SHA1, FEAT_SHA256
AEK_AES = 1 << 16, AEK_AES = 1 << 16, // FEAT_AES, FEAT_PMULL
AEK_FP16FML = 1 << 17, AEK_FP16FML = 1 << 17, // FEAT_FHM
AEK_RAND = 1 << 18, AEK_RAND = 1 << 18, // FEAT_RNG
AEK_MTE = 1 << 19, AEK_MTE = 1 << 19, // FEAT_MTE, FEAT_MTE2
AEK_SSBS = 1 << 20, AEK_SSBS = 1 << 20, // FEAT_SSBS, FEAT_SSBS2
AEK_SB = 1 << 21, AEK_SB = 1 << 21, // FEAT_SB
AEK_PREDRES = 1 << 22, AEK_PREDRES = 1 << 22, // FEAT_SPECRES
AEK_SVE2 = 1 << 23, AEK_SVE2 = 1 << 23, // FEAT_SVE2
AEK_SVE2AES = 1 << 24, AEK_SVE2AES = 1 << 24, // FEAT_SVE_AES, FEAT_SVE_PMULL128
AEK_SVE2SM4 = 1 << 25, AEK_SVE2SM4 = 1 << 25, // FEAT_SVE_SM4
AEK_SVE2SHA3 = 1 << 26, AEK_SVE2SHA3 = 1 << 26, // FEAT_SVE_SHA3
AEK_SVE2BITPERM = 1 << 27, AEK_SVE2BITPERM = 1 << 27, // FEAT_SVE_BitPerm
AEK_TME = 1 << 28, AEK_TME = 1 << 28, // FEAT_TME
AEK_BF16 = 1 << 29, AEK_BF16 = 1 << 29, // FEAT_BF16
AEK_I8MM = 1 << 30, AEK_I8MM = 1 << 30, // FEAT_I8MM
AEK_F32MM = 1ULL << 31, AEK_F32MM = 1ULL << 31, // FEAT_F32MM
AEK_F64MM = 1ULL << 32, AEK_F64MM = 1ULL << 32, // FEAT_F64MM
AEK_LS64 = 1ULL << 33, AEK_LS64 = 1ULL << 33, // FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA
AEK_BRBE = 1ULL << 34, AEK_BRBE = 1ULL << 34, // FEAT_BRBE
AEK_PAUTH = 1ULL << 35, AEK_PAUTH = 1ULL << 35, // FEAT_PAuth
AEK_FLAGM = 1ULL << 36, AEK_FLAGM = 1ULL << 36, // FEAT_FlagM
AEK_SME = 1ULL << 37, AEK_SME = 1ULL << 37, // FEAT_SME
AEK_SMEF64 = 1ULL << 38, AEK_SMEF64 = 1ULL << 38, // FEAT_SME_F64F64
AEK_SMEI64 = 1ULL << 39, AEK_SMEI64 = 1ULL << 39, // FEAT_SME_I16I64
AEK_HBC = 1ULL << 40, AEK_HBC = 1ULL << 40, // FEAT_HBC
AEK_MOPS = 1ULL << 41, AEK_MOPS = 1ULL << 41, // FEAT_MOPS
AEK_PERFMON = 1ULL << 42, AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3
}; };
enum class ArchKind { enum class ArchKind {
#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
#include "AArch64TargetParser.def" #include "AArch64TargetParser.def"
}; };
const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = { const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64.td

Show All 13 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "llvm/Target/Target.td" include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AArch64 Subtarget features. // AArch64 Subtarget features.
// //
// Each SubtargetFeature which corresponds to an Arm Architecture feature should
// be annotated with the respective FEAT_ feature name from the Architecture
// Reference Manual. If a SubtargetFeature enables instructions from multiple
// Arm Architecture Features, it should list all the relevant features. Not all
// FEAT_ features have a corresponding SubtargetFeature.
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
"Enable ARMv8 FP">; "Enable ARMv8 FP (FEAT_FP)">;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable Advanced SIMD instructions", [FeatureFPARMv8]>; "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>;
def FeatureSM4 : SubtargetFeature< def FeatureSM4 : SubtargetFeature<
"sm4", "HasSM4", "true", "sm4", "HasSM4", "true",
"Enable SM3 and SM4 support", [FeatureNEON]>; "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>;
def FeatureSHA2 : SubtargetFeature< def FeatureSHA2 : SubtargetFeature<
"sha2", "HasSHA2", "true", "sha2", "HasSHA2", "true",
"Enable SHA1 and SHA256 support", [FeatureNEON]>; "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>;
def FeatureSHA3 : SubtargetFeature< def FeatureSHA3 : SubtargetFeature<
"sha3", "HasSHA3", "true", "sha3", "HasSHA3", "true",
"Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>;
def FeatureAES : SubtargetFeature< def FeatureAES : SubtargetFeature<
"aes", "HasAES", "true", "aes", "HasAES", "true",
"Enable AES support", [FeatureNEON]>; "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>;
// Crypto has been split up and any combination is now valid (see the // Crypto has been split up and any combination is now valid (see the
// crypto definitions above). Also, crypto is now context sensitive: // crypto definitions above). Also, crypto is now context sensitive:
// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
// Therefore, we rely on Clang, the user interacing tool, to pass on the // Therefore, we rely on Clang, the user interacing tool, to pass on the
// appropriate crypto options. But here in the backend, crypto has very little // appropriate crypto options. But here in the backend, crypto has very little
// meaning anymore. We kept the Crypto definition here for backward // meaning anymore. We kept the Crypto definition here for backward
// compatibility, and now imply features SHA2 and AES, which was the // compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto. // "traditional" meaning of Crypto.
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
"Enable ARMv8 CRC-32 checksum instructions">; "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
"Enable ARMv8 Reliability, Availability and Serviceability Extensions">; "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
"Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">;
def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
"Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">; "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
def FeatureLDAPR : SubtargetFeature<"ldapr", "HasLDAPR", "true", def FeatureLDAPR : SubtargetFeature<"ldapr", "HasLDAPR", "true",
"Use LDAPR to lower atomic loads; experimental until we " "Use LDAPR to lower atomic loads; experimental until we "
"have more testing/a formal correctness proof">; "have more testing/a formal correctness proof">;
def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
"Enable out of line atomics to support LSE instructions">; "Enable out of line atomics to support LSE instructions">;
def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">;
def FeaturePAN : SubtargetFeature< def FeaturePAN : SubtargetFeature<
"pan", "HasPAN", "true", "pan", "HasPAN", "true",
"Enables ARM v8.1 Privileged Access-Never extension">; "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
def FeatureLOR : SubtargetFeature< def FeatureLOR : SubtargetFeature<
"lor", "HasLOR", "true", "lor", "HasLOR", "true",
"Enables ARM v8.1 Limited Ordering Regions extension">; "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
"true", "Enable RW operand CONTEXTIDR_EL2" >; "true", "Enable RW operand CONTEXTIDR_EL2" >;
def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
"Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >; "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
// This SubtargetFeature is special. It controls only whether codegen will turn
// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable ARMv8 PMUv3 Performance Monitors extension">; "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
"Full FP16", [FeatureFPARMv8]>; "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>;
def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
"Enable FP16 FML instructions", [FeatureFullFP16]>; "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
"Enable Statistical Profiling extension">; "Enable Statistical Profiling extension (FEAT_SPE)">;
def FeaturePAN_RWV : SubtargetFeature< def FeaturePAN_RWV : SubtargetFeature<
"pan-rwv", "HasPAN_RWV", "true", "pan-rwv", "HasPAN_RWV", "true",
"Enable v8.2 PAN s1e1R and s1e1W Variants", "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)",
[FeaturePAN]>; [FeaturePAN]>;
// UAO PState // UAO PState
def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
"Enable v8.2 UAO PState">; "Enable v8.2 UAO PState (FEAT_UAO)">;
def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
"true", "Enable v8.2 data Cache Clean to Point of Persistence" >; "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
"Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>; "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>;
// This flag is currently still labeled as Experimental, but when fully // This flag is currently still labeled as Experimental, but when fully
// implemented this should tell the compiler to use the zeroing pseudos to // implemented this should tell the compiler to use the zeroing pseudos to
// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive // benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
// lanes are known to be zero. The pseudos will then be expanded using the // lanes are known to be zero. The pseudos will then be expanded using the
// MOVPRFX instruction to zero the inactive lanes. This feature should only be // MOVPRFX instruction to zero the inactive lanes. This feature should only be
// enabled if MOVPRFX instructions are known to merge with the destructive // enabled if MOVPRFX instructions are known to merge with the destructive
// operations they prefix. // operations they prefix.
// //
// This feature could similarly be extended to support cheap merging of _any_ // This feature could similarly be extended to support cheap merging of _any_
// value into the inactive lanes using the MOVPRFX instruction that uses // value into the inactive lanes using the MOVPRFX instruction that uses
// merging-predication. // merging-predication.
def FeatureExperimentalZeroingPseudos def FeatureExperimentalZeroingPseudos
: SubtargetFeature<"use-experimental-zeroing-pseudos", : SubtargetFeature<"use-experimental-zeroing-pseudos",
"UseExperimentalZeroingPseudos", "true", "UseExperimentalZeroingPseudos", "true",
"Hint to the compiler that the MOVPRFX instruction is " "Hint to the compiler that the MOVPRFX instruction is "
"merged with destructive operations", "merged with destructive operations",
[]>; []>;
def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
"Enable Scalable Vector Extension 2 (SVE2) instructions", "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
[FeatureSVE, FeatureUseScalarIncVL]>; [FeatureSVE, FeatureUseScalarIncVL]>;
def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
"Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
[FeatureSVE2, FeatureAES]>;
def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>;
def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>;
def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
"Enable bit permutation SVE2 instructions", [FeatureSVE2]>; "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>;
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zero-cycle register moves">; "Has zero-cycle register moves">;
def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
"Has zero-cycle zeroing instructions for generic registers">; "Has zero-cycle zeroing instructions for generic registers">;
// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesdef FeatureDisableLatencySchedHeuristic : SubtargetFeature<
"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
"Disable latency scheduling heuristic">; "Disable latency scheduling heuristic">;
def FeatureForce32BitJumpTables def FeatureForce32BitJumpTables
: SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
"Force jump table entries to be 32-bits wide except at MinSize">; "Force jump table entries to be 32-bits wide except at MinSize">;
def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
"Enable support for RCPC extension">; "Enable support for RCPC extension (FEAT_LRCPC)">;
def FeatureUseRSqrt : SubtargetFeature< def FeatureUseRSqrt : SubtargetFeature<
"use-reciprocal-square-root", "UseRSqrt", "true", "use-reciprocal-square-root", "UseRSqrt", "true",
"Use the reciprocal square root approximation">; "Use the reciprocal square root approximation">;
def FeatureDotProd : SubtargetFeature< def FeatureDotProd : SubtargetFeature<
"dotprod", "HasDotProd", "true", "dotprod", "HasDotProd", "true",
"Enable dot product support">; "Enable dot product support (FEAT_DotProd)">;
def FeaturePAuth : SubtargetFeature< def FeaturePAuth : SubtargetFeature<
"pauth", "HasPAuth", "true", "pauth", "HasPAuth", "true",
"Enable v8.3-A Pointer Authentication extension">; "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
def FeatureJS : SubtargetFeature< def FeatureJS : SubtargetFeature<
"jsconv", "HasJS", "true", "jsconv", "HasJS", "true",
"Enable v8.3-A JavaScript FP conversion instructions", "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
[FeatureFPARMv8]>; [FeatureFPARMv8]>;
def FeatureCCIDX : SubtargetFeature< def FeatureCCIDX : SubtargetFeature<
"ccidx", "HasCCIDX", "true", "ccidx", "HasCCIDX", "true",
"Enable v8.3-A Extend of the CCSIDR number of sets">; "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
def FeatureComplxNum : SubtargetFeature< def FeatureComplxNum : SubtargetFeature<
"complxnum", "HasComplxNum", "true", "complxnum", "HasComplxNum", "true",
"Enable v8.3-A Floating-point complex number support", "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
[FeatureNEON]>; [FeatureNEON]>;
def FeatureNV : SubtargetFeature< def FeatureNV : SubtargetFeature<
"nv", "HasNV", "true", "nv", "HasNV", "true",
"Enable v8.4-A Nested Virtualization Enchancement">; "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
def FeatureMPAM : SubtargetFeature< def FeatureMPAM : SubtargetFeature<
"mpam", "HasMPAM", "true", "mpam", "HasMPAM", "true",
"Enable v8.4-A Memory system Partitioning and Monitoring extension">; "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
dmgreenUnsubmitted
Done
ReplyInline Actions

Should this be FEAT_MPAM?

dmgreen: Should this be FEAT_MPAM?
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

Updates incoming.

lenary: Updates incoming.
def FeatureDIT : SubtargetFeature< def FeatureDIT : SubtargetFeature<
"dit", "HasDIT", "true", "dit", "HasDIT", "true",
"Enable v8.4-A Data Independent Timing instructions">; "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">;
def FeatureTRACEV8_4 : SubtargetFeature< def FeatureTRACEV8_4 : SubtargetFeature<
"tracev8.4", "HasTRACEV8_4", "true", "tracev8.4", "HasTRACEV8_4", "true",
"Enable v8.4-A Trace extension">; "Enable v8.4-A Trace extension (FEAT_TRF)">;
def FeatureAM : SubtargetFeature< def FeatureAM : SubtargetFeature<
"am", "HasAM", "true", "am", "HasAM", "true",
"Enable v8.4-A Activity Monitors extension">; "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
def FeatureAMVS : SubtargetFeature< def FeatureAMVS : SubtargetFeature<
"amvs", "HasAMVS", "true", "amvs", "HasAMVS", "true",
"Enable v8.6-A Activity Monitors Virtualization support", "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
[FeatureAM]>; [FeatureAM]>;
def FeatureSEL2 : SubtargetFeature< def FeatureSEL2 : SubtargetFeature<
"sel2", "HasSEL2", "true", "sel2", "HasSEL2", "true",
"Enable v8.4-A Secure Exception Level 2 extension">; "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
def FeatureTLB_RMI : SubtargetFeature< def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true", "tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">; "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
def FeatureFlagM : SubtargetFeature< def FeatureFlagM : SubtargetFeature<
"flagm", "HasFlagM", "true", "flagm", "HasFlagM", "true",
"Enable v8.4-A Flag Manipulation Instructions">; "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">;
// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
"Enable v8.4-A RCPC instructions with Immediate Offsets", "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
[FeatureRCPC]>; [FeatureRCPC]>;
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
"NegativeImmediates", "false", "NegativeImmediates", "false",
"Convert immediates and instructions " "Convert immediates and instructions "
"to their negated or complemented " "to their negated or complemented "
"equivalent when the immediate does " "equivalent when the immediate does "
"not fit in the encoding.">; "not fit in the encoding.">;
def FeatureLSLFast : SubtargetFeature< def FeatureLSLFast : SubtargetFeature<
"lsl-fast", "HasLSLFast", "true", "lsl-fast", "HasLSLFast", "true",
"CPU has a fastpath logical shift of up to 3 places">; "CPU has a fastpath logical shift of up to 3 places">;
def FeatureAggressiveFMA : def FeatureAggressiveFMA :
SubtargetFeature<"aggressive-fma", SubtargetFeature<"aggressive-fma",
"HasAggressiveFMA", "HasAggressiveFMA",
"true", "true",
"Enable Aggressive FMA for floating-point.">; "Enable Aggressive FMA for floating-point.">;
def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
"Enable alternative NZCV format for floating point comparisons">; "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
"an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction" >; "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
def FeatureSB : SubtargetFeature<"sb", "HasSB", def FeatureSB : SubtargetFeature<"sb", "HasSB",
"true", "Enable v8.5 Speculation Barrier" >; "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >;
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
"true", "Enable Speculative Store Bypass Safe bit" >; "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >;
def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
"Enable v8.5a execution and data prediction invalidation instructions" >; "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >;
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
"true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
"true", "Enable Branch Target Identification" >; "true", "Enable Branch Target Identification (FEAT_BTI)" >;
def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
"true", "Enable Random Number generation instructions" >; "true", "Enable Random Number generation instructions (FEAT_RNG)" >;
def FeatureMTE : SubtargetFeature<"mte", "HasMTE", def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
"true", "Enable Memory Tagging Extension" >; "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >;
def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
"true", "Enable Trace Buffer Extension">; "true", "Enable Trace Buffer Extension (FEAT_TRBE)">;
def FeatureETE : SubtargetFeature<"ete", "HasETE", def FeatureETE : SubtargetFeature<"ete", "HasETE",
"true", "Enable Embedded Trace Extension", "true", "Enable Embedded Trace Extension (FEAT_ETE)",
[FeatureTRBE]>; [FeatureTRBE]>;
def FeatureTME : SubtargetFeature<"tme", "HasTME", def FeatureTME : SubtargetFeature<"tme", "HasTME",
"true", "Enable Transactional Memory Extension" >; "true", "Enable Transactional Memory Extension (FEAT_TME)" >;
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals", "AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global " "true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">; "that allows a memory tag in the upper address bits">;
def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
"true", "Enable BFloat16 Extension" >; "true", "Enable BFloat16 Extension (FEAT_BF16)" >;
def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
"true", "Enable Matrix Multiply Int8 Extension">; "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">;
def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
"true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>; "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>;
def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
"true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>; "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>;
def FeatureXS : SubtargetFeature<"xs", "HasXS", def FeatureXS : SubtargetFeature<"xs", "HasXS",
"true", "Enable Armv8.7-A limited-TLB-maintenance instruction">; "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
"true", "Enable Armv8.7-A WFET and WFIT instruction">; "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">;
def FeatureHCX : SubtargetFeature< def FeatureHCX : SubtargetFeature<
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">; "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">; "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
"true", "Enable Armv8.8-A Hinted Conditional Branches Extension">; "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS",
"true", "Enable Armv8.8-A memcpy and memset acceleration instructions">; "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">;
def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
"true", "Enable Branch Record Buffer Extension">; "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
"true", "Enable extra register in the Statistical Profiling Extension">; "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">; "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
def FeatureEnhancedCounterVirtualization : def FeatureEnhancedCounterVirtualization :
SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
"true", "Enable enhanced counter virtualization extension">; "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
def FeatureRME : SubtargetFeature<"rme", "HasRME", def FeatureRME : SubtargetFeature<"rme", "HasRME",
"true", "Enable Realm Management Extension">; "true", "Enable Realm Management Extension (FEAT_RME)">;
def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
"Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>; "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true", def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
"Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>; "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>;
def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true", def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
"Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>; "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
"Apple A7 (the CPU formerly known as Cyclone)">; "Apple A7 (the CPU formerly known as Cyclone)">;
def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
"Enable Exception Level 2 Virtual Memory System Architecture">; "Enable Exception Level 2 Virtual Memory System Architecture">;
def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
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