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Differential D131045

[NFC][AArch64] Precommit test to optimize instruction selection for aarch64_neon_pmull64 intrinsic.
ClosedPublic

Authored by mingmingl on Aug 2 2022, 11:11 PM.

Details

Reviewers
efriedma
dmgreen
Commits
rG3e6d1a6f5426: [NFC][AArch64] Precommit test to optimize instruction selection for…
Summary

Add test cases when instruction selection for aarch64_neon_pmull64 intrinsic is sub-optimal.

This is to prepare for D131047, and makes diff clearer.

Diff Detail

Unit TestsFailed

TimeTest
60,090 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases::scariness_score_test.cpp
60,110 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp

Event Timeline

mingmingl created this revision.Aug 2 2022, 11:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 2 2022, 11:11 PM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
mingmingl requested review of this revision.Aug 2 2022, 11:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 2 2022, 11:11 PM
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mingmingl mentioned this in D131044: [NFC] [AArch64] Precommit test case for a tablegen pattern for llvm.aarch64.neon.pmull64.Aug 2 2022, 11:28 PM
Harbormaster completed remote builds in B178948: Diff 449548.Aug 3 2022, 12:32 AM
mingmingl updated this revision to Diff 452479.Aug 13 2022, 10:59 PM

DO NOT SEND

Diffbase to show an alternative approach

Harbormaster completed remote builds in B181135: Diff 452479.Aug 13 2022, 11:54 PM
mingmingl updated this revision to Diff 452553.Aug 14 2022, 12:11 PM

add another test case test2 in llvm/test/CodeGen/AArch64/aarch64-pmull2.ll

Harbormaster completed remote builds in B181192: Diff 452553.Aug 14 2022, 12:59 PM
mingmingl updated this revision to Diff 453220.Aug 17 2022, 1:03 AM

simplify test case a little bit

mingmingl updated this revision to Diff 453226.Aug 17 2022, 1:08 AM

simplify test case, by removing unnecessary xor, etc

Harbormaster completed remote builds in B181696: Diff 453226.Aug 17 2022, 1:53 AM
mingmingl updated this revision to Diff 454052.Aug 19 2022, 10:14 AM
mingmingl retitled this revision from [NFC][AArch64] Precommit test for a tablegen pattern for aarch64_neon_pmull64 to [NFC][AArch64] Precommit test to optimize instruction selection for aarch64_neon_pmull64 intrinsic..
mingmingl edited the summary of this revision. (Show Details)
mingmingl added reviewers: efriedma, dmgreen.

Update revision title and summary. Use same comments for NFC and actual patch, so only assembly diff is shown in phabricator UI (not comment diff)

From discussion with colleagues I should probably ask for review for both pre-commit tests and the actual change in the first place to ensure the quality of new test cases (e.g., not overly sensitive to changes that might make it brittle/likely to fail for unrelated reasons, not insufficiently minimized so that it's hard to maintain/read/possibly and more likely to fail for unrelated reasons, have good readability in terms of naming, etc)

So do it now and will remember to ask reviews for both in the future. Hope it's not too late!

mingmingl mentioned this in D131047: [AArch64] Change aarch64_neon_pmull{,64} intrinsic ISel through a new SDNode..Aug 19 2022, 10:31 AM
dmgreen accepted this revision.Aug 19 2022, 10:39 AM

Oh yeah - LGTM

This revision is now accepted and ready to land.Aug 19 2022, 10:39 AM
Harbormaster completed remote builds in B182260: Diff 454052.Aug 19 2022, 11:05 AM
This revision was landed with ongoing or failed builds.Aug 19 2022, 1:18 PM
Closed by commit rG3e6d1a6f5426: [NFC][AArch64] Precommit test to optimize instruction selection for… (authored by mingmingl). · Explain Why
This revision was automatically updated to reflect the committed changes.
mingmingl added a commit: rG3e6d1a6f5426: [NFC][AArch64] Precommit test to optimize instruction selection for….

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
59 lines
40 lines

Diff 449548

llvm/test/CodeGen/AArch64/aarch64-pmull2.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK
; Test that PMULL2 are codegen'ed when only one (of two) operands
; are in higher-half register already.
;
; This is a big win (saves multiple moves) since user code intends to execute {pmull, pmull2} instruction
; on {lower, higher} half of the same SIMD register.
define void @test(ptr %0, ptr %1) {
; CHECK-LABEL: test:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x1]
; CHECK-NEXT: mov w8, #56824
; CHECK-NEXT: mov w9, #61186
; CHECK-NEXT: movk w8, #40522, lsl #16
; CHECK-NEXT: movk w9, #29710, lsl #16
; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: fmov d2, x9
; CHECK-NEXT: mov x11, v1.d[1]
; CHECK-NEXT: fmov d3, x8
; CHECK-NEXT: fmov d4, x10
; CHECK-NEXT: pmull v0.1q, v0.1d, v2.1d
; CHECK-NEXT: fmov d5, x11
; CHECK-NEXT: pmull v1.1q, v1.1d, v2.1d
; CHECK-NEXT: pmull v2.1q, v4.1d, v3.1d
; CHECK-NEXT: pmull v3.1q, v5.1d, v3.1d
; CHECK-NEXT: ldp q4, q5, [x0]
; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b
; CHECK-NEXT: eor v1.16b, v1.16b, v3.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: eor v1.16b, v5.16b, v1.16b
; CHECK-NEXT: stp q0, q1, [x1]
; CHECK-NEXT: ret
%3 = load <2 x i64>, ptr %1
%4 = getelementptr inbounds <2 x i64>, ptr %1, i64 1
%5 = load <2 x i64>, ptr %4
%6 = extractelement <2 x i64> %3, i64 1
%7 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %6, i64 2655706616)
%8 = extractelement <2 x i64> %5, i64 1
%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 2655706616)
%10 = load <2 x i64>, ptr %0
%11 = getelementptr inbounds i8, ptr %0, i64 16
%12 = load <2 x i64>, ptr %11
%13 = extractelement <2 x i64> %3, i64 0
%14 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %13, i64 1947135746)
%15 = extractelement <2 x i64> %5, i64 0
%16 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %15, i64 1947135746)
%17 = xor <16 x i8> %14, %7
%18 = bitcast <16 x i8> %17 to <2 x i64>
%19 = xor <16 x i8> %16, %9
%20 = bitcast <16 x i8> %19 to <2 x i64>
%21 = xor <2 x i64> %10, %18
%22 = xor <2 x i64> %12, %20
store <2 x i64> %21, ptr %1
store <2 x i64> %22, ptr %4
ret void
}
declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)

llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

Show All 25 Lines
define void @test2(ptr %0, i64 %1, i64 %2, <2 x i64> %3) { define void @test2(ptr %0, i64 %1, i64 %2, <2 x i64> %3) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov x9, v0.d[1] ; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: add x8, x0, x1, lsl #4 ; CHECK-NEXT: add x8, x0, x1, lsl #4
; CHECK-NEXT: ldr d0, [x8, #8] ; CHECK-NEXT: ldr d0, [x8, #8]
; CHECK-NEXT: fmov d1, x9 ; CHECK-NEXT: fmov d1, x9
; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
%7 = load i64, ptr %6, align 8
%8 = extractelement <2 x i64> %3, i64 1
%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 %7)
store <16 x i8> %9, ptr %5, align 16
ret void
}
; test3 clones test2, but swaps lhs with rhs, to test that non-extract
; operand will be canonicalized to the rhs.
define void @test3(ptr %0, i64 %1, i64 %2, <2 x i64> %3) {
; CHECK-LABEL: test3:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: add x8, x0, x1, lsl #4
; CHECK-NEXT: ldr d0, [x8, #8]
; CHECK-NEXT: fmov d1, x9
; CHECK-NEXT: pmull v0.1q, v0.1d, v1.1d ; CHECK-NEXT: pmull v0.1q, v0.1d, v1.1d
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1 %5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1 %6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
%7 = load i64, ptr %6, align 8 %7 = load i64, ptr %6, align 8
%8 = extractelement <2 x i64> %3, i64 1 %8 = extractelement <2 x i64> %3, i64 1
%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %8) %9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %8)
store <16 x i8> %9, ptr %5, align 16 store <16 x i8> %9, ptr %5, align 16
ret void ret void
} }
define void @test3(ptr %0, i64 %1, i64 %2, i64 %3) { define void @test4(ptr %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, x1, lsl #4 ; CHECK-NEXT: add x8, x0, x1, lsl #4
; CHECK-NEXT: fmov d0, x3 ; CHECK-NEXT: fmov d0, x3
; CHECK-NEXT: ldr d1, [x8, #8] ; CHECK-NEXT: ldr d1, [x8, #8]
; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d ; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d
; CHECK-NEXT: str q0, [x8] ; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1 %5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1 %6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
%7 = load i64, ptr %6, align 8 %7 = load i64, ptr %6, align 8
%8 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %3) %8 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %3)
store <16 x i8> %8, ptr %5, align 16 store <16 x i8> %8, ptr %5, align 16
ret void ret void
} }
define void @test5(ptr %0, <2 x i64> %1, i64 %2) {
; CHECK-LABEL: test5:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: fmov d0, x1
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%4 = extractelement <2 x i64> %1, i64 1
%5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
store <16 x i8> %5, ptr %0, align 16
ret void
}
declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)