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Differential D130424

AMDGPU: Adjust register allocation priority values down
ClosedPublic

Authored by arsenm on Jul 23 2022, 8:21 AM.

Details

Reviewers
foad
rampitec
Group Reviewers
Restricted Project
Summary

Set the priorities consistently to number of registers in the tuple -

  1. Previously we started at 1, and also tried to give SGPR higher

values than VGPRs. There's no point in assigning SGPRs higher values
now that those are allocated in a separate regalloc run.




This avoids overflowing the 5 bits used for the class priority in the

allocation heuristic for 32 element tuples. This avoids some cases

where smaller registers unexpectedly get prioritized over larger.
Diff Detail
Event Timeline
arsenm created this revision.Jul 23 2022, 8:21 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJul 23 2022, 8:21 AM
Herald added subscribers: kosarev, kerbowa, hiraditya and 7 others.  ·  View Herald Transcript
arsenm requested review of this revision.Jul 23 2022, 8:21 AM
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Harbormaster completed remote builds in B177182: Diff 447072.Jul 23 2022, 9:19 AM
arsenm added a child revision: D130427: RegAllocGreedy: Avoid overflowing priority bitfields.Jul 23 2022, 9:56 AM
foad accepted this revision.Jul 25 2022, 2:19 AM
LGTM, thanks!



Set the priorities consistently to number of registers in the tuple - 1.



I wonder if we will need to tweak this when we have properly allocatable 16-bit registers for GFX11.
This revision is now accepted and ready to land.Jul 25 2022, 2:19 AM
arsenm closed this revision.Jul 25 2022, 12:47 PM
cb0c71e8b198aedd7569c0561ad3efba1d3d5766
Revision Contents
Diff 447072
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Show First 20 Lines • Show All 343 Lines • ▼ Show 20 Linesdef M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> {

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




// TODO: Do we need to set DwarfRegAlias on register tuples?
// TODO: Do we need to set DwarfRegAlias on register tuples?




def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,

                              (add (sequence "SGPR%u_LO16", 0, 105))> {
                              (add (sequence "SGPR%u_LO16", 0, 105))> {

  let AllocationPriority = 9;
  let AllocationPriority = 0;

  let Size = 16;
  let Size = 16;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,

                              (add (sequence "SGPR%u_HI16", 0, 105))> {
                              (add (sequence "SGPR%u_HI16", 0, 105))> {

  let isAllocatable = 0;
  let isAllocatable = 0;

  let Size = 16;
  let Size = 16;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




// SGPR 32-bit registers
// SGPR 32-bit registers

def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

                            (add (sequence "SGPR%u", 0, 105))> {
                            (add (sequence "SGPR%u", 0, 105))> {

  // Give all SGPR classes higher priority than VGPR classes, because
  // Give all SGPR classes higher priority than VGPR classes, because

  // we want to spill SGPRs to VGPRs.
  // we want to spill SGPRs to VGPRs.

  let AllocationPriority = 9;
  let AllocationPriority = 0;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




// SGPR 64-bit registers
// SGPR 64-bit registers

def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;
def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;




// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs.
// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs.

▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
}
}




def Reg16Types : RegisterTypes<[i16, f16]>;
def Reg16Types : RegisterTypes<[i16, f16]>;

def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>;
def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>;




let HasVGPR = 1 in {
let HasVGPR = 1 in {

def VGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
def VGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,

                              (add (sequence "VGPR%u_LO16", 0, 255))> {
                              (add (sequence "VGPR%u_LO16", 0, 255))> {

  let AllocationPriority = 1;
  let AllocationPriority = 0;

  let Size = 16;
  let Size = 16;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

}
}




def VGPR_HI16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,
def VGPR_HI16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,

                              (add (sequence "VGPR%u_HI16", 0, 255))> {
                              (add (sequence "VGPR%u_HI16", 0, 255))> {

  let AllocationPriority = 1;
  let AllocationPriority = 0;

  let Size = 16;
  let Size = 16;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

}
}




// VGPR 32-bit registers
// VGPR 32-bit registers

// i16/f16 only on VI+
// i16/f16 only on VI+

def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,
def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,

                            (add (sequence "VGPR%u", 0, 255))> {
                            (add (sequence "VGPR%u", 0, 255))> {

  let AllocationPriority = 1;
  let AllocationPriority = 0;

  let Size = 32;
  let Size = 32;

  let Weight = 1;
  let Weight = 1;

}
}

} // End HasVGPR = 1
} // End HasVGPR = 1




// VGPR 64-bit registers
// VGPR 64-bit registers

def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">;
def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">;




Show All 27 Linesdef AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,

  let isAllocatable = 0;
  let isAllocatable = 0;

  let Size = 16;
  let Size = 16;

  let GeneratePressureSet = 0;
  let GeneratePressureSet = 0;

}
}




// AccVGPR 32-bit registers
// AccVGPR 32-bit registers

def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

                            (add (sequence "AGPR%u", 0, 255))> {
                            (add (sequence "AGPR%u", 0, 255))> {

  let AllocationPriority = 1;
  let AllocationPriority = 0;

  let Size = 32;
  let Size = 32;

  let Weight = 1;
  let Weight = 1;

}
}

} // End HasAGPR = 1
} // End HasAGPR = 1




// AGPR 64-bit registers
// AGPR 64-bit registers

def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">;
def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">;




▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
let GeneratePressureSet = 0, HasSGPR = 1 in {
let GeneratePressureSet = 0, HasSGPR = 1 in {

// Subset of SReg_32 without M0 for SMRD instructions and alike.
// Subset of SReg_32 without M0 for SMRD instructions and alike.

// See comments in SIInstructions.td for more info.
// See comments in SIInstructions.td for more info.

def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,

  (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
  (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,

   SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE,
   SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE,

   SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,
   SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,

   SRC_VCCZ, SRC_EXECZ, SRC_SCC)> {
   SRC_VCCZ, SRC_EXECZ, SRC_SCC)> {

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_LO16_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SReg_LO16_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i16, f16], 16,

  (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16,
  (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16,

   XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16,
   XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16,

   TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16,
   TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16,

   SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16,
   SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16,

   SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> {
   SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> {

  let Size = 16;
  let Size = 16;

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,

  (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> {
  (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> {

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_LO16_XEXEC_HI : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SReg_LO16_XEXEC_HI : SIRegisterClass<"AMDGPU", [i16, f16], 16,

  (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> {
  (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> {

  let Size = 16;
  let Size = 16;

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,

  (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
  (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_LO16_XM0 : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SReg_LO16_XM0 : SIRegisterClass<"AMDGPU", [i16, f16], 16,

  (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> {
  (add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> {

  let Size = 16;
  let Size = 16;

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}




def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,
def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16], 16,

  (add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> {
  (add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> {

  let Size = 16;
  let Size = 16;

  let AllocationPriority = 10;
  let AllocationPriority = 0;

}
}

} // End GeneratePressureSet = 0
} // End GeneratePressureSet = 0




// Register class for all scalar registers (SGPRs + Special Registers)
// Register class for all scalar registers (SGPRs + Special Registers)

def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,

  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> {
  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> {

  let AllocationPriority = 10;
  let AllocationPriority = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




let GeneratePressureSet = 0 in {
let GeneratePressureSet = 0 in {

def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

  (add SReg_32, LDS_DIRECT_CLASS)> {
  (add SReg_32, LDS_DIRECT_CLASS)> {

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,
def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,

                            (add SGPR_64Regs)> {
                            (add SGPR_64Regs)> {

  let CopyCost = 1;
  let CopyCost = 1;

  let AllocationPriority = 11;
  let AllocationPriority = 1;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32,
def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32,

                            (add TTMP_64Regs)> {
                            (add TTMP_64Regs)> {

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,

  (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SGPR_NULL64, TTMP_64, TBA, TMA)> {
  (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SGPR_NULL64, TTMP_64, TBA, TMA)> {

  let CopyCost = 1;
  let CopyCost = 1;

  let AllocationPriority = 13;
  let AllocationPriority = 1;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,

  (add SReg_64_XEXEC, EXEC)> {
  (add SReg_64_XEXEC, EXEC)> {

  let CopyCost = 1;
  let CopyCost = 1;

  let AllocationPriority = 13;
  let AllocationPriority = 1;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32,
def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32,

  (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> {
  (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> {

  let CopyCost = 1;
  let CopyCost = 1;

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32,
def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32,

  (add SReg_1_XEXEC, EXEC, EXEC_LO)> {
  (add SReg_1_XEXEC, EXEC, EXEC_LO)> {

  let CopyCost = 1;
  let CopyCost = 1;

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasSGPR = 1;
  let HasSGPR = 1;

}
}




multiclass SRegClass<int numRegs, int priority,
multiclass SRegClass<int numRegs,

                     list<ValueType> regTypes,
                     list<ValueType> regTypes,

                     SIRegisterTuples regList,
                     SIRegisterTuples regList,

                     SIRegisterTuples ttmpList = regList,
                     SIRegisterTuples ttmpList = regList,

                     int copyCost = !sra(!add(numRegs, 1), 1)> {
                     int copyCost = !sra(!add(numRegs, 1), 1)> {

  defvar hasTTMP = !ne(regList, ttmpList);
  defvar hasTTMP = !ne(regList, ttmpList);

  defvar suffix = !cast<string>(!mul(numRegs, 32));
  defvar suffix = !cast<string>(!mul(numRegs, 32));

  defvar sgprName = !strconcat("SGPR_", suffix);
  defvar sgprName = !strconcat("SGPR_", suffix);

  defvar ttmpName = !strconcat("TTMP_", suffix);
  defvar ttmpName = !strconcat("TTMP_", suffix);




  let AllocationPriority = priority, CopyCost = copyCost, HasSGPR = 1 in {
  let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in {

    def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> {
    def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> {

    }
    }




    if hasTTMP then {
    if hasTTMP then {

      def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> {
      def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> {

        let isAllocatable = 0;
        let isAllocatable = 0;

      }
      }

    }
    }




    def SReg_ # suffix :
    def SReg_ # suffix :

      SIRegisterClass<"AMDGPU", regTypes, 32,
      SIRegisterClass<"AMDGPU", regTypes, 32,

                    !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]),
                    !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]),

                    !if(hasTTMP,
                    !if(hasTTMP,

                        !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]),
                        !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]),

                        (add)))> {
                        (add)))> {

      let isAllocatable = 0;
      let isAllocatable = 0;

    }
    }

  }
  }

}
}




defm "" : SRegClass<3, 14, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>;
defm "" : SRegClass<3, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>;

defm "" : SRegClass<4, 15, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], SGPR_128Regs, TTMP_128Regs>;
defm "" : SRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16], SGPR_128Regs, TTMP_128Regs>;

defm "" : SRegClass<5, 16, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>;
defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>;

defm "" : SRegClass<6, 17, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>;
defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>;

defm "" : SRegClass<7, 18, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>;
defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>;

defm "" : SRegClass<8, 19, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], SGPR_256Regs, TTMP_256Regs>;
defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], SGPR_256Regs, TTMP_256Regs>;

defm "" : SRegClass<16, 20, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>;
defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>;

defm "" : SRegClass<32, 21, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;




def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

                                 (add VGPR_32, LDS_DIRECT_CLASS)> {
                                 (add VGPR_32, LDS_DIRECT_CLASS)> {

  let isAllocatable = 0;
  let isAllocatable = 0;

  let HasVGPR = 1;
  let HasVGPR = 1;

}
}




// Register class for all vector registers (VGPRs + Interpolation Registers)
// Register class for all vector registers (VGPRs + Interpolation Registers)

class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :

    SIRegisterClass<"AMDGPU", regTypes, 32, regList> {
    SIRegisterClass<"AMDGPU", regTypes, 32, regList> {

  let Size = !mul(numRegs, 32);
  let Size = !mul(numRegs, 32);




  // Requires n v_mov_b32 to copy
  // Requires n v_mov_b32 to copy

  let CopyCost = numRegs;
  let CopyCost = numRegs;

  let AllocationPriority = numRegs;
  let AllocationPriority = !sub(numRegs, 1);

  let Weight = numRegs;
  let Weight = numRegs;

}
}




// Define a register tuple class, along with one requiring an even
// Define a register tuple class, along with one requiring an even

// aligned base register.
// aligned base register.

multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {

  let HasVGPR = 1 in {
  let HasVGPR = 1 in {

    // Define the regular class.
    // Define the regular class.

▲ Show 20 Lines • Show All 380 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
Show First 20 Lines • Show All 518 Lines • ▼ Show 20 Lines
}
}




define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg2, i64 %arg3, <2 x half> %arg4, <2 x half> %arg5) #3 {
define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg2, i64 %arg3, <2 x half> %arg4, <2 x half> %arg5) #3 {

; GFX908-LABEL: introduced_copy_to_sgpr:
; GFX908-LABEL: introduced_copy_to_sgpr:

; GFX908:       ; %bb.0: ; %bb
; GFX908:       ; %bb.0: ; %bb

; GFX908-NEXT:    global_load_ushort v24, v[0:1], off glc
; GFX908-NEXT:    global_load_ushort v24, v[0:1], off glc

; GFX908-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX908-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x8

; GFX908-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x10
; GFX908-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x10

; GFX908-NEXT:    s_load_dword s8, s[4:5], 0x18
; GFX908-NEXT:    s_load_dword s6, s[4:5], 0x18

; GFX908-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x0
; GFX908-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x0

; GFX908-NEXT:    v_mov_b32_e32 v1, 0
; GFX908-NEXT:    v_mov_b32_e32 v1, 0

; GFX908-NEXT:    s_waitcnt lgkmcnt(0)
; GFX908-NEXT:    s_waitcnt lgkmcnt(0)

; GFX908-NEXT:    v_cvt_f32_u32_e32 v0, s1
; GFX908-NEXT:    v_cvt_f32_u32_e32 v0, s1

; GFX908-NEXT:    s_sub_i32 s4, 0, s1
; GFX908-NEXT:    s_sub_i32 s4, 0, s1

; GFX908-NEXT:    s_lshr_b32 s11, s8, 16
; GFX908-NEXT:    s_lshr_b32 s5, s6, 16

; GFX908-NEXT:    v_cvt_f32_f16_e32 v25, s8
; GFX908-NEXT:    v_cvt_f32_f16_e32 v25, s6

; GFX908-NEXT:    v_rcp_iflag_f32_e32 v0, v0
; GFX908-NEXT:    v_rcp_iflag_f32_e32 v0, v0

; GFX908-NEXT:    s_lshl_b64 s[8:9], s[2:3], 5
; GFX908-NEXT:    s_lshl_b64 s[10:11], s[2:3], 5

; GFX908-NEXT:    v_cvt_f32_f16_e32 v26, s11
; GFX908-NEXT:    v_cvt_f32_f16_e32 v26, s5

; GFX908-NEXT:    s_or_b32 s8, s8, 28
; GFX908-NEXT:    s_or_b32 s10, s10, 28

; GFX908-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX908-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0

; GFX908-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX908-NEXT:    v_cvt_u32_f32_e32 v0, v0

; GFX908-NEXT:    v_mov_b32_e32 v7, s3
; GFX908-NEXT:    v_mov_b32_e32 v7, s3

; GFX908-NEXT:    s_mov_b32 s10, 0
; GFX908-NEXT:    s_lshl_b64 s[6:7], s[8:9], 5

; GFX908-NEXT:    v_mov_b32_e32 v6, s2
; GFX908-NEXT:    v_mov_b32_e32 v6, s2

; GFX908-NEXT:    v_mul_lo_u32 v2, s4, v0
; GFX908-NEXT:    v_mul_lo_u32 v2, s4, v0

; GFX908-NEXT:    s_lshl_b64 s[4:5], s[6:7], 5
; GFX908-NEXT:    s_mov_b32 s4, 0

; GFX908-NEXT:    v_mul_hi_u32 v2, v0, v2
; GFX908-NEXT:    v_mul_hi_u32 v2, v0, v2

; GFX908-NEXT:    v_add_u32_e32 v0, v0, v2
; GFX908-NEXT:    v_add_u32_e32 v0, v0, v2

; GFX908-NEXT:    v_mul_hi_u32 v0, s0, v0
; GFX908-NEXT:    v_mul_hi_u32 v0, s0, v0

; GFX908-NEXT:    v_mov_b32_e32 v2, s8
; GFX908-NEXT:    v_mov_b32_e32 v2, s10

; GFX908-NEXT:    v_mov_b32_e32 v3, s9
; GFX908-NEXT:    v_mov_b32_e32 v3, s11

; GFX908-NEXT:    v_mul_lo_u32 v4, v0, s1
; GFX908-NEXT:    v_mul_lo_u32 v4, v0, s1

; GFX908-NEXT:    v_add_u32_e32 v5, 1, v0
; GFX908-NEXT:    v_add_u32_e32 v5, 1, v0

; GFX908-NEXT:    v_sub_u32_e32 v4, s0, v4
; GFX908-NEXT:    v_sub_u32_e32 v4, s0, v4

; GFX908-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4
; GFX908-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4

; GFX908-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX908-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc

; GFX908-NEXT:    v_subrev_u32_e32 v5, s1, v4
; GFX908-NEXT:    v_subrev_u32_e32 v5, s1, v4

; GFX908-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX908-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc

; GFX908-NEXT:    v_add_u32_e32 v5, 1, v0
; GFX908-NEXT:    v_add_u32_e32 v5, 1, v0

; GFX908-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4
; GFX908-NEXT:    v_cmp_le_u32_e32 vcc, s1, v4

; GFX908-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX908-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc

; GFX908-NEXT:    v_lshlrev_b64 v[4:5], 5, v[0:1]
; GFX908-NEXT:    v_lshlrev_b64 v[4:5], 5, v[0:1]

; GFX908-NEXT:    s_waitcnt vmcnt(0)
; GFX908-NEXT:    s_waitcnt vmcnt(0)

; GFX908-NEXT:    v_readfirstlane_b32 s0, v24
; GFX908-NEXT:    v_readfirstlane_b32 s0, v24

; GFX908-NEXT:    s_and_b32 s0, 0xffff, s0
; GFX908-NEXT:    s_and_b32 s0, 0xffff, s0

; GFX908-NEXT:    s_mul_i32 s1, s7, s0
; GFX908-NEXT:    s_mul_i32 s1, s9, s0

; GFX908-NEXT:    s_mul_hi_u32 s7, s6, s0
; GFX908-NEXT:    s_mul_hi_u32 s5, s8, s0

; GFX908-NEXT:    s_mul_i32 s0, s6, s0
; GFX908-NEXT:    s_mul_i32 s0, s8, s0

; GFX908-NEXT:    s_add_i32 s1, s7, s1
; GFX908-NEXT:    s_add_i32 s1, s5, s1

; GFX908-NEXT:    s_lshl_b64 s[6:7], s[0:1], 5
; GFX908-NEXT:    s_lshl_b64 s[8:9], s[0:1], 5

; GFX908-NEXT:    s_branch .LBB3_2
; GFX908-NEXT:    s_branch .LBB3_2

; GFX908-NEXT:  .LBB3_1: ; %bb12
; GFX908-NEXT:  .LBB3_1: ; %bb12

; GFX908-NEXT:    ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT:    ; in Loop: Header=BB3_2 Depth=1

; GFX908-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0
; GFX908-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0

; GFX908-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX908-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc

; GFX908-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
; GFX908-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4

; GFX908-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX908-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc

; GFX908-NEXT:  .LBB3_2: ; %bb9
; GFX908-NEXT:  .LBB3_2: ; %bb9

; GFX908-NEXT:    ; =>This Loop Header: Depth=1
; GFX908-NEXT:    ; =>This Loop Header: Depth=1

; GFX908-NEXT:    ; Child Loop BB3_5 Depth 2
; GFX908-NEXT:    ; Child Loop BB3_5 Depth 2

; GFX908-NEXT:    s_cbranch_scc0 .LBB3_1
; GFX908-NEXT:    s_cbranch_scc0 .LBB3_1

; GFX908-NEXT:  ; %bb.3: ; %bb14
; GFX908-NEXT:  ; %bb.3: ; %bb14

; GFX908-NEXT:    ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT:    ; in Loop: Header=BB3_2 Depth=1

; GFX908-NEXT:    v_mov_b32_e32 v8, 0
; GFX908-NEXT:    v_mov_b32_e32 v8, 0

; GFX908-NEXT:    v_mov_b32_e32 v9, 0
; GFX908-NEXT:    v_mov_b32_e32 v9, 0

; GFX908-NEXT:    global_load_dwordx2 v[8:9], v[8:9], off
; GFX908-NEXT:    global_load_dwordx2 v[8:9], v[8:9], off

; GFX908-NEXT:    s_mov_b32 s11, s10
; GFX908-NEXT:    s_mov_b32 s5, s4

; GFX908-NEXT:    v_mov_b32_e32 v13, s11
; GFX908-NEXT:    v_mov_b32_e32 v13, s5

; GFX908-NEXT:    v_mov_b32_e32 v15, s11
; GFX908-NEXT:    v_mov_b32_e32 v15, s5

; GFX908-NEXT:    v_mov_b32_e32 v17, s11
; GFX908-NEXT:    v_mov_b32_e32 v17, s5

; GFX908-NEXT:    v_mov_b32_e32 v12, s10
; GFX908-NEXT:    v_mov_b32_e32 v12, s4

; GFX908-NEXT:    v_mov_b32_e32 v14, s10
; GFX908-NEXT:    v_mov_b32_e32 v14, s4

; GFX908-NEXT:    v_mov_b32_e32 v16, s10
; GFX908-NEXT:    v_mov_b32_e32 v16, s4

; GFX908-NEXT:    v_cmp_gt_i64_e64 s[0:1], 0, v[6:7]
; GFX908-NEXT:    v_cmp_gt_i64_e64 s[0:1], 0, v[6:7]

; GFX908-NEXT:    v_mov_b32_e32 v11, v3
; GFX908-NEXT:    v_mov_b32_e32 v11, v3

; GFX908-NEXT:    v_mov_b32_e32 v19, v13
; GFX908-NEXT:    v_mov_b32_e32 v19, v13

; GFX908-NEXT:    v_mov_b32_e32 v10, v2
; GFX908-NEXT:    v_mov_b32_e32 v10, v2

; GFX908-NEXT:    v_mov_b32_e32 v18, v12
; GFX908-NEXT:    v_mov_b32_e32 v18, v12

; GFX908-NEXT:    s_waitcnt vmcnt(0)
; GFX908-NEXT:    s_waitcnt vmcnt(0)

; GFX908-NEXT:    v_readfirstlane_b32 s2, v8
; GFX908-NEXT:    v_readfirstlane_b32 s2, v8

; GFX908-NEXT:    v_readfirstlane_b32 s3, v9
; GFX908-NEXT:    v_readfirstlane_b32 s3, v9

; GFX908-NEXT:    s_add_u32 s2, s2, 1
; GFX908-NEXT:    s_add_u32 s2, s2, 1

; GFX908-NEXT:    s_addc_u32 s3, s3, 0
; GFX908-NEXT:    s_addc_u32 s3, s3, 0

; GFX908-NEXT:    s_mul_hi_u32 s9, s4, s2
; GFX908-NEXT:    s_mul_hi_u32 s5, s6, s2

; GFX908-NEXT:    s_mul_i32 s11, s5, s2
; GFX908-NEXT:    s_mul_i32 s11, s7, s2

; GFX908-NEXT:    s_mul_i32 s8, s4, s2
; GFX908-NEXT:    s_mul_i32 s10, s6, s2

; GFX908-NEXT:    s_mul_i32 s2, s4, s3
; GFX908-NEXT:    s_mul_i32 s2, s6, s3

; GFX908-NEXT:    s_add_i32 s2, s9, s2
; GFX908-NEXT:    s_add_i32 s2, s5, s2

; GFX908-NEXT:    s_add_i32 s9, s2, s11
; GFX908-NEXT:    s_add_i32 s5, s2, s11

; GFX908-NEXT:    s_branch .LBB3_5
; GFX908-NEXT:    s_branch .LBB3_5

; GFX908-NEXT:  .LBB3_4: ; %bb58
; GFX908-NEXT:  .LBB3_4: ; %bb58

; GFX908-NEXT:    ; in Loop: Header=BB3_5 Depth=2
; GFX908-NEXT:    ; in Loop: Header=BB3_5 Depth=2

; GFX908-NEXT:    v_add_co_u32_sdwa v8, vcc, v8, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX908-NEXT:    v_add_co_u32_sdwa v8, vcc, v8, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0

; GFX908-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX908-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc

; GFX908-NEXT:    v_cmp_gt_i64_e32 vcc, 0, v[8:9]
; GFX908-NEXT:    v_cmp_gt_i64_e32 vcc, 0, v[8:9]

; GFX908-NEXT:    v_mov_b32_e32 v20, s7
; GFX908-NEXT:    v_mov_b32_e32 v20, s9

; GFX908-NEXT:    v_add_co_u32_e64 v10, s[2:3], s6, v10
; GFX908-NEXT:    v_add_co_u32_e64 v10, s[2:3], s8, v10

; GFX908-NEXT:    v_addc_co_u32_e64 v11, s[2:3], v11, v20, s[2:3]
; GFX908-NEXT:    v_addc_co_u32_e64 v11, s[2:3], v11, v20, s[2:3]

; GFX908-NEXT:    s_cbranch_vccz .LBB3_1
; GFX908-NEXT:    s_cbranch_vccz .LBB3_1

; GFX908-NEXT:  .LBB3_5: ; %bb16
; GFX908-NEXT:  .LBB3_5: ; %bb16

; GFX908-NEXT:    ; Parent Loop BB3_2 Depth=1
; GFX908-NEXT:    ; Parent Loop BB3_2 Depth=1

; GFX908-NEXT:    ; => This Inner Loop Header: Depth=2
; GFX908-NEXT:    ; => This Inner Loop Header: Depth=2

; GFX908-NEXT:    v_mov_b32_e32 v21, s9
; GFX908-NEXT:    v_mov_b32_e32 v21, s5

; GFX908-NEXT:    v_add_co_u32_e32 v20, vcc, s8, v10
; GFX908-NEXT:    v_add_co_u32_e32 v20, vcc, s10, v10

; GFX908-NEXT:    v_addc_co_u32_e32 v21, vcc, v11, v21, vcc
; GFX908-NEXT:    v_addc_co_u32_e32 v21, vcc, v11, v21, vcc

; GFX908-NEXT:    global_load_dword v28, v[20:21], off offset:-12 glc
; GFX908-NEXT:    global_load_dword v28, v[20:21], off offset:-12 glc

; GFX908-NEXT:    s_waitcnt vmcnt(0)
; GFX908-NEXT:    s_waitcnt vmcnt(0)

; GFX908-NEXT:    global_load_dword v27, v[20:21], off offset:-8 glc
; GFX908-NEXT:    global_load_dword v27, v[20:21], off offset:-8 glc

; GFX908-NEXT:    s_waitcnt vmcnt(0)
; GFX908-NEXT:    s_waitcnt vmcnt(0)

; GFX908-NEXT:    global_load_dword v22, v[20:21], off offset:-4 glc
; GFX908-NEXT:    global_load_dword v22, v[20:21], off offset:-4 glc

; GFX908-NEXT:    s_waitcnt vmcnt(0)
; GFX908-NEXT:    s_waitcnt vmcnt(0)

; GFX908-NEXT:    global_load_dword v20, v[20:21], off glc
; GFX908-NEXT:    global_load_dword v20, v[20:21], off glc

Show All 27 Lines
; GFX908-NEXT:    v_add_f32_e32 v19, v19, v21
; GFX908-NEXT:    v_add_f32_e32 v19, v19, v21

; GFX908-NEXT:    s_branch .LBB3_4
; GFX908-NEXT:    s_branch .LBB3_4

;
;

; GFX90A-LABEL: introduced_copy_to_sgpr:
; GFX90A-LABEL: introduced_copy_to_sgpr:

; GFX90A:       ; %bb.0: ; %bb
; GFX90A:       ; %bb.0: ; %bb

; GFX90A-NEXT:    global_load_ushort v28, v[0:1], off glc
; GFX90A-NEXT:    global_load_ushort v28, v[0:1], off glc

; GFX90A-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX90A-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0

; GFX90A-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8
; GFX90A-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x8

; GFX90A-NEXT:    s_load_dwordx2 s[10:11], s[4:5], 0x10
; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0x10

; GFX90A-NEXT:    s_load_dword s2, s[4:5], 0x18
; GFX90A-NEXT:    s_load_dword s3, s[4:5], 0x18

; GFX90A-NEXT:    v_mov_b32_e32 v1, 0
; GFX90A-NEXT:    v_mov_b32_e32 v1, 0

; GFX90A-NEXT:    s_mov_b32 s8, 0

; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)

; GFX90A-NEXT:    s_lshl_b64 s[4:5], s[0:1], 5

; GFX90A-NEXT:    v_cvt_f32_u32_e32 v0, s7
; GFX90A-NEXT:    v_cvt_f32_u32_e32 v0, s7

; GFX90A-NEXT:    s_sub_i32 s9, 0, s7
; GFX90A-NEXT:    s_sub_i32 s12, 0, s7

; GFX90A-NEXT:    s_lshl_b64 s[4:5], s[10:11], 5
; GFX90A-NEXT:    s_lshr_b32 s13, s3, 16

; GFX90A-NEXT:    s_or_b32 s4, s4, 28
; GFX90A-NEXT:    v_cvt_f32_f16_e32 v2, s3

; GFX90A-NEXT:    v_rcp_iflag_f32_e32 v0, v0
; GFX90A-NEXT:    v_rcp_iflag_f32_e32 v0, v0

; GFX90A-NEXT:    s_lshr_b32 s12, s2, 16
; GFX90A-NEXT:    v_cvt_f32_f16_e32 v3, s13

; GFX90A-NEXT:    v_pk_mov_b32 v[6:7], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT:    s_lshl_b64 s[10:11], s[8:9], 5

; GFX90A-NEXT:    v_cvt_f32_f16_e32 v2, s2
; GFX90A-NEXT:    s_or_b32 s10, s10, 28

; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX90A-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0

; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT:    v_cvt_u32_f32_e32 v0, v0

; GFX90A-NEXT:    v_cvt_f32_f16_e32 v3, s12
; GFX90A-NEXT:    s_mov_b32 s2, 0

; GFX90A-NEXT:    s_lshl_b64 s[2:3], s[0:1], 5
; GFX90A-NEXT:    v_pk_mov_b32 v[4:5], s[8:9], s[8:9] op_sel:[0,1]

; GFX90A-NEXT:    v_pk_mov_b32 v[4:5], s[10:11], s[10:11] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[6:7], s[10:11], s[10:11] op_sel:[0,1]

; GFX90A-NEXT:    v_mul_lo_u32 v8, s9, v0
; GFX90A-NEXT:    v_mul_lo_u32 v8, s12, v0

; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v8
; GFX90A-NEXT:    v_mul_hi_u32 v8, v0, v8

; GFX90A-NEXT:    v_add_u32_e32 v0, v0, v8
; GFX90A-NEXT:    v_add_u32_e32 v0, v0, v8

; GFX90A-NEXT:    v_mul_hi_u32 v0, s6, v0
; GFX90A-NEXT:    v_mul_hi_u32 v0, s6, v0

; GFX90A-NEXT:    v_mul_lo_u32 v8, v0, s7
; GFX90A-NEXT:    v_mul_lo_u32 v8, v0, s7

; GFX90A-NEXT:    v_sub_u32_e32 v8, s6, v8
; GFX90A-NEXT:    v_sub_u32_e32 v8, s6, v8

; GFX90A-NEXT:    v_add_u32_e32 v9, 1, v0
; GFX90A-NEXT:    v_add_u32_e32 v9, 1, v0

; GFX90A-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
; GFX90A-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8

; GFX90A-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX90A-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc

; GFX90A-NEXT:    v_subrev_u32_e32 v9, s7, v8
; GFX90A-NEXT:    v_subrev_u32_e32 v9, s7, v8

; GFX90A-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
; GFX90A-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc

; GFX90A-NEXT:    v_add_u32_e32 v9, 1, v0
; GFX90A-NEXT:    v_add_u32_e32 v9, 1, v0

; GFX90A-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
; GFX90A-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8

; GFX90A-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX90A-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc

; GFX90A-NEXT:    v_lshlrev_b64 v[8:9], 5, v[0:1]
; GFX90A-NEXT:    v_lshlrev_b64 v[8:9], 5, v[0:1]

; GFX90A-NEXT:    v_pk_mov_b32 v[10:11], 0, 0
; GFX90A-NEXT:    v_pk_mov_b32 v[10:11], 0, 0

; GFX90A-NEXT:    s_waitcnt vmcnt(0)
; GFX90A-NEXT:    s_waitcnt vmcnt(0)

; GFX90A-NEXT:    v_readfirstlane_b32 s4, v28
; GFX90A-NEXT:    v_readfirstlane_b32 s3, v28

; GFX90A-NEXT:    s_and_b32 s4, 0xffff, s4
; GFX90A-NEXT:    s_and_b32 s3, 0xffff, s3

; GFX90A-NEXT:    s_mul_i32 s1, s1, s4
; GFX90A-NEXT:    s_mul_i32 s1, s1, s3

; GFX90A-NEXT:    s_mul_hi_u32 s5, s0, s4
; GFX90A-NEXT:    s_mul_hi_u32 s6, s0, s3

; GFX90A-NEXT:    s_mul_i32 s0, s0, s4
; GFX90A-NEXT:    s_mul_i32 s0, s0, s3

; GFX90A-NEXT:    s_add_i32 s1, s5, s1
; GFX90A-NEXT:    s_add_i32 s1, s6, s1

; GFX90A-NEXT:    s_lshl_b64 s[4:5], s[0:1], 5
; GFX90A-NEXT:    s_lshl_b64 s[6:7], s[0:1], 5

; GFX90A-NEXT:    s_branch .LBB3_2
; GFX90A-NEXT:    s_branch .LBB3_2

; GFX90A-NEXT:  .LBB3_1: ; %bb12
; GFX90A-NEXT:  .LBB3_1: ; %bb12

; GFX90A-NEXT:    ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT:    ; in Loop: Header=BB3_2 Depth=1

; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v0
; GFX90A-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v0

; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX90A-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc

; GFX90A-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
; GFX90A-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8

; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v9, vcc
; GFX90A-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v9, vcc

; GFX90A-NEXT:  .LBB3_2: ; %bb9
; GFX90A-NEXT:  .LBB3_2: ; %bb9

; GFX90A-NEXT:    ; =>This Loop Header: Depth=1
; GFX90A-NEXT:    ; =>This Loop Header: Depth=1

; GFX90A-NEXT:    ; Child Loop BB3_5 Depth 2
; GFX90A-NEXT:    ; Child Loop BB3_5 Depth 2

; GFX90A-NEXT:    s_cbranch_scc0 .LBB3_1
; GFX90A-NEXT:    s_cbranch_scc0 .LBB3_1

; GFX90A-NEXT:  ; %bb.3: ; %bb14
; GFX90A-NEXT:  ; %bb.3: ; %bb14

; GFX90A-NEXT:    ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT:    ; in Loop: Header=BB3_2 Depth=1

; GFX90A-NEXT:    global_load_dwordx2 v[12:13], v[10:11], off
; GFX90A-NEXT:    global_load_dwordx2 v[12:13], v[10:11], off

; GFX90A-NEXT:    s_mov_b32 s9, s8
; GFX90A-NEXT:    s_mov_b32 s3, s2

; GFX90A-NEXT:    v_pk_mov_b32 v[16:17], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[16:17], s[2:3], s[2:3] op_sel:[0,1]

; GFX90A-NEXT:    v_pk_mov_b32 v[18:19], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[18:19], s[2:3], s[2:3] op_sel:[0,1]

; GFX90A-NEXT:    v_pk_mov_b32 v[20:21], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[20:21], s[2:3], s[2:3] op_sel:[0,1]

; GFX90A-NEXT:    v_cmp_gt_i64_e64 s[0:1], 0, v[4:5]
; GFX90A-NEXT:    v_cmp_gt_i64_e64 s[0:1], 0, v[4:5]

; GFX90A-NEXT:    v_pk_mov_b32 v[14:15], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[14:15], v[6:7], v[6:7] op_sel:[0,1]

; GFX90A-NEXT:    v_pk_mov_b32 v[22:23], v[16:17], v[16:17] op_sel:[0,1]
; GFX90A-NEXT:    v_pk_mov_b32 v[22:23], v[16:17], v[16:17] op_sel:[0,1]

; GFX90A-NEXT:    s_waitcnt vmcnt(0)
; GFX90A-NEXT:    s_waitcnt vmcnt(0)

; GFX90A-NEXT:    v_readfirstlane_b32 s6, v12
; GFX90A-NEXT:    v_readfirstlane_b32 s3, v12

; GFX90A-NEXT:    v_readfirstlane_b32 s7, v13
; GFX90A-NEXT:    v_readfirstlane_b32 s8, v13

; GFX90A-NEXT:    s_add_u32 s6, s6, 1
; GFX90A-NEXT:    s_add_u32 s3, s3, 1

; GFX90A-NEXT:    s_addc_u32 s7, s7, 0
; GFX90A-NEXT:    s_addc_u32 s9, s8, 0

; GFX90A-NEXT:    s_mul_hi_u32 s9, s2, s6
; GFX90A-NEXT:    s_mul_hi_u32 s10, s4, s3

; GFX90A-NEXT:    s_mul_i32 s7, s2, s7
; GFX90A-NEXT:    s_mul_i32 s11, s5, s3

; GFX90A-NEXT:    s_mul_i32 s10, s3, s6
; GFX90A-NEXT:    s_mul_i32 s8, s4, s3

; GFX90A-NEXT:    s_add_i32 s7, s9, s7
; GFX90A-NEXT:    s_mul_i32 s3, s4, s9

; GFX90A-NEXT:    s_mul_i32 s6, s2, s6
; GFX90A-NEXT:    s_add_i32 s3, s10, s3

; GFX90A-NEXT:    s_add_i32 s7, s7, s10
; GFX90A-NEXT:    s_add_i32 s3, s3, s11

; GFX90A-NEXT:    s_branch .LBB3_5
; GFX90A-NEXT:    s_branch .LBB3_5

; GFX90A-NEXT:  .LBB3_4: ; %bb58
; GFX90A-NEXT:  .LBB3_4: ; %bb58

; GFX90A-NEXT:    ; in Loop: Header=BB3_5 Depth=2
; GFX90A-NEXT:    ; in Loop: Header=BB3_5 Depth=2

; GFX90A-NEXT:    v_add_co_u32_sdwa v12, vcc, v12, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX90A-NEXT:    v_add_co_u32_sdwa v12, vcc, v12, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0

; GFX90A-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX90A-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v13, vcc

; GFX90A-NEXT:    v_mov_b32_e32 v24, s5
; GFX90A-NEXT:    v_mov_b32_e32 v24, s7

; GFX90A-NEXT:    v_add_co_u32_e32 v14, vcc, s4, v14
; GFX90A-NEXT:    v_add_co_u32_e32 v14, vcc, s6, v14

; GFX90A-NEXT:    v_addc_co_u32_e32 v15, vcc, v15, v24, vcc
; GFX90A-NEXT:    v_addc_co_u32_e32 v15, vcc, v15, v24, vcc

; GFX90A-NEXT:    v_cmp_gt_i64_e32 vcc, 0, v[12:13]
; GFX90A-NEXT:    v_cmp_gt_i64_e32 vcc, 0, v[12:13]

; GFX90A-NEXT:    s_cbranch_vccz .LBB3_1
; GFX90A-NEXT:    s_cbranch_vccz .LBB3_1

; GFX90A-NEXT:  .LBB3_5: ; %bb16
; GFX90A-NEXT:  .LBB3_5: ; %bb16

; GFX90A-NEXT:    ; Parent Loop BB3_2 Depth=1
; GFX90A-NEXT:    ; Parent Loop BB3_2 Depth=1

; GFX90A-NEXT:    ; => This Inner Loop Header: Depth=2
; GFX90A-NEXT:    ; => This Inner Loop Header: Depth=2

; GFX90A-NEXT:    v_mov_b32_e32 v25, s7
; GFX90A-NEXT:    v_mov_b32_e32 v25, s3

; GFX90A-NEXT:    v_add_co_u32_e32 v24, vcc, s6, v14
; GFX90A-NEXT:    v_add_co_u32_e32 v24, vcc, s8, v14

; GFX90A-NEXT:    v_addc_co_u32_e32 v25, vcc, v15, v25, vcc
; GFX90A-NEXT:    v_addc_co_u32_e32 v25, vcc, v15, v25, vcc

; GFX90A-NEXT:    global_load_dword v30, v[24:25], off offset:-12 glc
; GFX90A-NEXT:    global_load_dword v30, v[24:25], off offset:-12 glc

; GFX90A-NEXT:    s_waitcnt vmcnt(0)
; GFX90A-NEXT:    s_waitcnt vmcnt(0)

; GFX90A-NEXT:    global_load_dword v29, v[24:25], off offset:-8 glc
; GFX90A-NEXT:    global_load_dword v29, v[24:25], off offset:-8 glc

; GFX90A-NEXT:    s_waitcnt vmcnt(0)
; GFX90A-NEXT:    s_waitcnt vmcnt(0)

; GFX90A-NEXT:    global_load_dword v26, v[24:25], off offset:-4 glc
; GFX90A-NEXT:    global_load_dword v26, v[24:25], off offset:-4 glc

; GFX90A-NEXT:    s_waitcnt vmcnt(0)
; GFX90A-NEXT:    s_waitcnt vmcnt(0)

; GFX90A-NEXT:    global_load_dword v26, v[24:25], off glc
; GFX90A-NEXT:    global_load_dword v26, v[24:25], off glc

▲ Show 20 Lines • Show All 358 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
Show All 22 Lines
; GCN-LABEL: {{^}}load_v2i32:
; GCN-LABEL: {{^}}load_v2i32:

; SICIVI-DAG: s_mov_b32 s3, 0
; SICIVI-DAG: s_mov_b32 s3, 0

; SICIVI-DAG: s_mov_b32 s2, s1
; SICIVI-DAG: s_mov_b32 s2, s1

; SICIVI-DAG: s_mov_b32 s1, s3
; SICIVI-DAG: s_mov_b32 s1, s3

; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4

; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10

; GFX9-DAG: s_mov_b32 s6, s1
; GFX9-DAG: s_mov_b32 s2, s1

; GFX9-DAG: s_mov_b32 s7, 0
; GFX9-DAG: s_mov_b32 s3, 0

; GFX9-DAG: s_mov_b32 s1, s7
; GFX9-DAG: s_mov_b32 s1, s3

; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[6:7], 0x10
; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10

define amdgpu_vs <2 x float> @load_v2i32(<2 x i32> addrspace(6)* inreg %p0, <2 x i32> addrspace(6)* inreg %p1) #0 {
define amdgpu_vs <2 x float> @load_v2i32(<2 x i32> addrspace(6)* inreg %p0, <2 x i32> addrspace(6)* inreg %p1) #0 {

  %gep1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(6)* %p1, i32 2
  %gep1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(6)* %p1, i32 2

  %r0 = load <2 x i32>, <2 x i32> addrspace(6)* %p0
  %r0 = load <2 x i32>, <2 x i32> addrspace(6)* %p0

  %r1 = load <2 x i32>, <2 x i32> addrspace(6)* %gep1
  %r1 = load <2 x i32>, <2 x i32> addrspace(6)* %gep1

  %r = add <2 x i32> %r0, %r1
  %r = add <2 x i32> %r0, %r1

  %r2 = bitcast <2 x i32> %r to <2 x float>
  %r2 = bitcast <2 x i32> %r to <2 x float>

  ret <2 x float> %r2
  ret <2 x float> %r2

}
}

▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}load_v2float:
; GCN-LABEL: {{^}}load_v2float:

; SICIVI-DAG: s_mov_b32 s3, 0
; SICIVI-DAG: s_mov_b32 s3, 0

; SICIVI-DAG: s_mov_b32 s2, s1
; SICIVI-DAG: s_mov_b32 s2, s1

; SICIVI-DAG: s_mov_b32 s1, s3
; SICIVI-DAG: s_mov_b32 s1, s3

; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4

; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10

; GFX9-DAG: s_mov_b32 s6, s1
; GFX9-DAG: s_mov_b32 s2, s1

; GFX9-DAG: s_mov_b32 s7, 0
; GFX9-DAG: s_mov_b32 s3, 0

; GFX9-DAG: s_mov_b32 s1, s7
; GFX9-DAG: s_mov_b32 s1, s3

; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0

; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[6:7], 0x10
; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10

define amdgpu_vs <2 x float> @load_v2float(<2 x float> addrspace(6)* inreg %p0, <2 x float> addrspace(6)* inreg %p1) #0 {
define amdgpu_vs <2 x float> @load_v2float(<2 x float> addrspace(6)* inreg %p0, <2 x float> addrspace(6)* inreg %p1) #0 {

  %gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(6)* %p1, i32 2
  %gep1 = getelementptr inbounds <2 x float>, <2 x float> addrspace(6)* %p1, i32 2

  %r0 = load <2 x float>, <2 x float> addrspace(6)* %p0
  %r0 = load <2 x float>, <2 x float> addrspace(6)* %p0

  %r1 = load <2 x float>, <2 x float> addrspace(6)* %gep1
  %r1 = load <2 x float>, <2 x float> addrspace(6)* %gep1

  %r = fadd <2 x float> %r0, %r1
  %r = fadd <2 x float> %r0, %r1

  ret <2 x float> %r
  ret <2 x float> %r

}
}




▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
Show All 20 Linesbody:             |

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF

  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT: bb.1:

  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   dead %3:vreg_64 = IMPLICIT_DEF

  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]

  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]

  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF

  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT: bb.2:

  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   undef %5.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
  ; CHECK-NEXT:   undef %6.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {

  ; CHECK-NEXT:     internal %5.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31:av_1024_align2 = COPY [[COPY]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
  ; CHECK-NEXT:     internal %6.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31:av_1024_align2 = COPY [[COPY]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31

  ; CHECK-NEXT:   }
  ; CHECK-NEXT:   }

  ; CHECK-NEXT:   %5.sub0:av_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   %6.sub0:av_1024_align2 = IMPLICIT_DEF

  ; CHECK-NEXT:   S_NOP 0, implicit %5.sub0
  ; CHECK-NEXT:   S_NOP 0, implicit %6.sub0

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT: bb.3:

  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   S_NOP 0, implicit %5
  ; CHECK-NEXT:   S_NOP 0, implicit %6

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT: bb.4:

  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF

  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT: bb.5:

  ; CHECK-NEXT:   undef %3.sub0:vreg_1024_align2 = COPY [[DEF]]
  ; CHECK-NEXT:   undef %4.sub0:vreg_1024_align2 = COPY [[DEF]]

  ; CHECK-NEXT:   S_NOP 0, implicit %3
  ; CHECK-NEXT:   S_NOP 0, implicit %4

  bb.0:
  bb.0:

    %0:vgpr_32 = IMPLICIT_DEF
    %0:vgpr_32 = IMPLICIT_DEF

    %1:vreg_1024_align2 = IMPLICIT_DEF
    %1:vreg_1024_align2 = IMPLICIT_DEF

    %2:vreg_1024_align2 = COPY %1
    %2:vreg_1024_align2 = COPY %1




  bb.1:
  bb.1:

    %5:vreg_64 = IMPLICIT_DEF

    S_NOP 0, implicit %1
    S_NOP 0, implicit %1

    S_NOP 0, implicit %1
    S_NOP 0, implicit %1

    %1:vreg_1024_align2 = IMPLICIT_DEF
    %1:vreg_1024_align2 = IMPLICIT_DEF

    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc




  bb.3:
  bb.3:

    %2.sub0:vreg_1024_align2 = IMPLICIT_DEF
    %2.sub0:vreg_1024_align2 = IMPLICIT_DEF

    S_NOP 0, implicit %2.sub0
    S_NOP 0, implicit %2.sub0

Show All 12 Lines
llvm/test/CodeGen/AMDGPU/indirect-call.ll
Show First 20 Lines • Show All 1,138 Lines • ▼ Show 20 Lines
; GCN-NEXT:    v_writelane_b32 v40, s59, 27
; GCN-NEXT:    v_writelane_b32 v40, s59, 27

; GCN-NEXT:    v_writelane_b32 v40, s60, 28
; GCN-NEXT:    v_writelane_b32 v40, s60, 28

; GCN-NEXT:    v_writelane_b32 v40, s61, 29
; GCN-NEXT:    v_writelane_b32 v40, s61, 29

; GCN-NEXT:    v_writelane_b32 v40, s62, 30
; GCN-NEXT:    v_writelane_b32 v40, s62, 30

; GCN-NEXT:    v_writelane_b32 v40, s63, 31
; GCN-NEXT:    v_writelane_b32 v40, s63, 31

; GCN-NEXT:    s_mov_b64 s[6:7], exec
; GCN-NEXT:    s_mov_b64 s[6:7], exec

; GCN-NEXT:    s_movk_i32 s4, 0x7b
; GCN-NEXT:    s_movk_i32 s4, 0x7b

; GCN-NEXT:  .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT:  .LBB6_1: ; =>This Inner Loop Header: Depth=1

; GCN-NEXT:    v_readfirstlane_b32 s10, v0
; GCN-NEXT:    v_readfirstlane_b32 s8, v0

; GCN-NEXT:    v_readfirstlane_b32 s11, v1
; GCN-NEXT:    v_readfirstlane_b32 s9, v1

; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]

; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT:    s_and_saveexec_b64 s[10:11], vcc

; GCN-NEXT:    s_swappc_b64 s[30:31], s[10:11]
; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]

; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1

; GCN-NEXT:    s_xor_b64 exec, exec, s[8:9]
; GCN-NEXT:    s_xor_b64 exec, exec, s[10:11]

; GCN-NEXT:    s_cbranch_execnz .LBB6_1
; GCN-NEXT:    s_cbranch_execnz .LBB6_1

; GCN-NEXT:  ; %bb.2:
; GCN-NEXT:  ; %bb.2:

; GCN-NEXT:    s_mov_b64 exec, s[6:7]
; GCN-NEXT:    s_mov_b64 exec, s[6:7]

; GCN-NEXT:    v_readlane_b32 s63, v40, 31
; GCN-NEXT:    v_readlane_b32 s63, v40, 31

; GCN-NEXT:    v_readlane_b32 s62, v40, 30
; GCN-NEXT:    v_readlane_b32 s62, v40, 30

; GCN-NEXT:    v_readlane_b32 s61, v40, 29
; GCN-NEXT:    v_readlane_b32 s61, v40, 29

; GCN-NEXT:    v_readlane_b32 s60, v40, 28
; GCN-NEXT:    v_readlane_b32 s60, v40, 28

; GCN-NEXT:    v_readlane_b32 s59, v40, 27
; GCN-NEXT:    v_readlane_b32 s59, v40, 27

▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
; GCN-NEXT:    v_writelane_b32 v40, s59, 27
; GCN-NEXT:    v_writelane_b32 v40, s59, 27

; GCN-NEXT:    v_writelane_b32 v40, s60, 28
; GCN-NEXT:    v_writelane_b32 v40, s60, 28

; GCN-NEXT:    v_writelane_b32 v40, s61, 29
; GCN-NEXT:    v_writelane_b32 v40, s61, 29

; GCN-NEXT:    v_writelane_b32 v40, s62, 30
; GCN-NEXT:    v_writelane_b32 v40, s62, 30

; GCN-NEXT:    v_writelane_b32 v40, s63, 31
; GCN-NEXT:    v_writelane_b32 v40, s63, 31

; GCN-NEXT:    v_mov_b32_e32 v41, v0
; GCN-NEXT:    v_mov_b32_e32 v41, v0

; GCN-NEXT:    s_mov_b64 s[4:5], exec
; GCN-NEXT:    s_mov_b64 s[4:5], exec

; GCN-NEXT:  .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT:  .LBB7_1: ; =>This Inner Loop Header: Depth=1

; GCN-NEXT:    v_readfirstlane_b32 s8, v1
; GCN-NEXT:    v_readfirstlane_b32 s6, v1

; GCN-NEXT:    v_readfirstlane_b32 s9, v2
; GCN-NEXT:    v_readfirstlane_b32 s7, v2

; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]
; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[6:7], v[1:2]

; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc

; GCN-NEXT:    v_mov_b32_e32 v0, v41
; GCN-NEXT:    v_mov_b32_e32 v0, v41

; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]

; GCN-NEXT:    ; implicit-def: $vgpr1_vgpr2
; GCN-NEXT:    ; implicit-def: $vgpr1_vgpr2

; GCN-NEXT:    s_xor_b64 exec, exec, s[6:7]
; GCN-NEXT:    s_xor_b64 exec, exec, s[8:9]

; GCN-NEXT:    s_cbranch_execnz .LBB7_1
; GCN-NEXT:    s_cbranch_execnz .LBB7_1

; GCN-NEXT:  ; %bb.2:
; GCN-NEXT:  ; %bb.2:

; GCN-NEXT:    s_mov_b64 exec, s[4:5]
; GCN-NEXT:    s_mov_b64 exec, s[4:5]

; GCN-NEXT:    v_mov_b32_e32 v0, v41
; GCN-NEXT:    v_mov_b32_e32 v0, v41

; GCN-NEXT:    v_readlane_b32 s63, v40, 31
; GCN-NEXT:    v_readlane_b32 s63, v40, 31

; GCN-NEXT:    v_readlane_b32 s62, v40, 30
; GCN-NEXT:    v_readlane_b32 s62, v40, 30

; GCN-NEXT:    v_readlane_b32 s61, v40, 29
; GCN-NEXT:    v_readlane_b32 s61, v40, 29

; GCN-NEXT:    v_readlane_b32 s60, v40, 28
; GCN-NEXT:    v_readlane_b32 s60, v40, 28

▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; GCN-NEXT:    v_writelane_b32 v40, s58, 26
; GCN-NEXT:    v_writelane_b32 v40, s58, 26

; GCN-NEXT:    v_writelane_b32 v40, s59, 27
; GCN-NEXT:    v_writelane_b32 v40, s59, 27

; GCN-NEXT:    v_writelane_b32 v40, s60, 28
; GCN-NEXT:    v_writelane_b32 v40, s60, 28

; GCN-NEXT:    v_writelane_b32 v40, s61, 29
; GCN-NEXT:    v_writelane_b32 v40, s61, 29

; GCN-NEXT:    v_writelane_b32 v40, s62, 30
; GCN-NEXT:    v_writelane_b32 v40, s62, 30

; GCN-NEXT:    v_writelane_b32 v40, s63, 31
; GCN-NEXT:    v_writelane_b32 v40, s63, 31

; GCN-NEXT:    s_mov_b64 s[4:5], exec
; GCN-NEXT:    s_mov_b64 s[4:5], exec

; GCN-NEXT:  .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT:  .LBB8_1: ; =>This Inner Loop Header: Depth=1

; GCN-NEXT:    v_readfirstlane_b32 s8, v1
; GCN-NEXT:    v_readfirstlane_b32 s6, v1

; GCN-NEXT:    v_readfirstlane_b32 s9, v2
; GCN-NEXT:    v_readfirstlane_b32 s7, v2

; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[8:9], v[1:2]
; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[6:7], v[1:2]

; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc

; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]

; GCN-NEXT:    v_mov_b32_e32 v3, v0
; GCN-NEXT:    v_mov_b32_e32 v3, v0

; GCN-NEXT:    ; implicit-def: $vgpr1_vgpr2
; GCN-NEXT:    ; implicit-def: $vgpr1_vgpr2

; GCN-NEXT:    ; implicit-def: $vgpr0
; GCN-NEXT:    ; implicit-def: $vgpr0

; GCN-NEXT:    s_xor_b64 exec, exec, s[6:7]
; GCN-NEXT:    s_xor_b64 exec, exec, s[8:9]

; GCN-NEXT:    s_cbranch_execnz .LBB8_1
; GCN-NEXT:    s_cbranch_execnz .LBB8_1

; GCN-NEXT:  ; %bb.2:
; GCN-NEXT:  ; %bb.2:

; GCN-NEXT:    s_mov_b64 exec, s[4:5]
; GCN-NEXT:    s_mov_b64 exec, s[4:5]

; GCN-NEXT:    v_mov_b32_e32 v0, v3
; GCN-NEXT:    v_mov_b32_e32 v0, v3

; GCN-NEXT:    v_readlane_b32 s63, v40, 31
; GCN-NEXT:    v_readlane_b32 s63, v40, 31

; GCN-NEXT:    v_readlane_b32 s62, v40, 30
; GCN-NEXT:    v_readlane_b32 s62, v40, 30

; GCN-NEXT:    v_readlane_b32 s61, v40, 29
; GCN-NEXT:    v_readlane_b32 s61, v40, 29

; GCN-NEXT:    v_readlane_b32 s60, v40, 28
; GCN-NEXT:    v_readlane_b32 s60, v40, 28

▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
; GCN-NEXT:    v_writelane_b32 v40, s58, 26
; GCN-NEXT:    v_writelane_b32 v40, s58, 26

; GCN-NEXT:    v_writelane_b32 v40, s59, 27
; GCN-NEXT:    v_writelane_b32 v40, s59, 27

; GCN-NEXT:    v_writelane_b32 v40, s60, 28
; GCN-NEXT:    v_writelane_b32 v40, s60, 28

; GCN-NEXT:    v_writelane_b32 v40, s61, 29
; GCN-NEXT:    v_writelane_b32 v40, s61, 29

; GCN-NEXT:    v_writelane_b32 v40, s62, 30
; GCN-NEXT:    v_writelane_b32 v40, s62, 30

; GCN-NEXT:    v_writelane_b32 v40, s63, 31
; GCN-NEXT:    v_writelane_b32 v40, s63, 31

; GCN-NEXT:    s_mov_b64 s[4:5], exec
; GCN-NEXT:    s_mov_b64 s[4:5], exec

; GCN-NEXT:  .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT:  .LBB9_1: ; =>This Inner Loop Header: Depth=1

; GCN-NEXT:    v_readfirstlane_b32 s8, v0
; GCN-NEXT:    v_readfirstlane_b32 s6, v0

; GCN-NEXT:    v_readfirstlane_b32 s9, v1
; GCN-NEXT:    v_readfirstlane_b32 s7, v1

; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[8:9], v[0:1]
; GCN-NEXT:    v_cmp_eq_u64_e32 vcc, s[6:7], v[0:1]

; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc

; GCN-NEXT:    s_swappc_b64 s[30:31], s[8:9]
; GCN-NEXT:    s_swappc_b64 s[30:31], s[6:7]

; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1
; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1

; GCN-NEXT:    s_xor_b64 exec, exec, s[6:7]
; GCN-NEXT:    s_xor_b64 exec, exec, s[8:9]

; GCN-NEXT:    s_cbranch_execnz .LBB9_1
; GCN-NEXT:    s_cbranch_execnz .LBB9_1

; GCN-NEXT:  ; %bb.2:
; GCN-NEXT:  ; %bb.2:

; GCN-NEXT:    s_mov_b64 exec, s[4:5]
; GCN-NEXT:    s_mov_b64 exec, s[4:5]

; GCN-NEXT:    v_readlane_b32 s63, v40, 31
; GCN-NEXT:    v_readlane_b32 s63, v40, 31

; GCN-NEXT:    v_readlane_b32 s62, v40, 30
; GCN-NEXT:    v_readlane_b32 s62, v40, 30

; GCN-NEXT:    v_readlane_b32 s61, v40, 29
; GCN-NEXT:    v_readlane_b32 s61, v40, 29

; GCN-NEXT:    v_readlane_b32 s60, v40, 28
; GCN-NEXT:    v_readlane_b32 s60, v40, 28

; GCN-NEXT:    v_readlane_b32 s59, v40, 27
; GCN-NEXT:    v_readlane_b32 s59, v40, 27

▲ Show 20 Lines • Show All 130 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
Show First 20 Lines • Show All 1,013 Lines • ▼ Show 20 Lines
; GFX9-NEXT:    exp null off, off, off, off done vm
; GFX9-NEXT:    exp null off, off, off, off done vm

; GFX9-NEXT:    s_endpgm
; GFX9-NEXT:    s_endpgm

;
;

; GFX10-32-LABEL: wqm_deriv_loop:
; GFX10-32-LABEL: wqm_deriv_loop:

; GFX10-32:       ; %bb.0: ; %.entry
; GFX10-32:       ; %bb.0: ; %.entry

; GFX10-32-NEXT:    s_mov_b32 s0, exec_lo
; GFX10-32-NEXT:    s_mov_b32 s0, exec_lo

; GFX10-32-NEXT:    s_wqm_b32 exec_lo, exec_lo
; GFX10-32-NEXT:    s_wqm_b32 exec_lo, exec_lo

; GFX10-32-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX10-32-NEXT:    v_cvt_i32_f32_e32 v0, v0

; GFX10-32-NEXT:    s_mov_b32 s2, 0
; GFX10-32-NEXT:    s_mov_b32 s1, 0

; GFX10-32-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0

; GFX10-32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
; GFX10-32-NEXT:    s_and_saveexec_b32 s2, vcc_lo

; GFX10-32-NEXT:    s_xor_b32 s1, exec_lo, s1
; GFX10-32-NEXT:    s_xor_b32 s2, exec_lo, s2

; GFX10-32-NEXT:    s_cbranch_execz .LBB7_3
; GFX10-32-NEXT:    s_cbranch_execz .LBB7_3

; GFX10-32-NEXT:  ; %bb.1: ; %.demote0
; GFX10-32-NEXT:  ; %bb.1: ; %.demote0

; GFX10-32-NEXT:    s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT:    s_andn2_b32 s0, s0, exec_lo

; GFX10-32-NEXT:    s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT:    s_cbranch_scc0 .LBB7_9

; GFX10-32-NEXT:  ; %bb.2: ; %.demote0
; GFX10-32-NEXT:  ; %bb.2: ; %.demote0

; GFX10-32-NEXT:    s_wqm_b32 s3, s0
; GFX10-32-NEXT:    s_wqm_b32 s3, s0

; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s3
; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s3

; GFX10-32-NEXT:  .LBB7_3: ; %.continue0.preheader
; GFX10-32-NEXT:  .LBB7_3: ; %.continue0.preheader

; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s2

; GFX10-32-NEXT:    s_mov_b32 s3, 0
; GFX10-32-NEXT:    s_mov_b32 s2, 0

; GFX10-32-NEXT:    s_branch .LBB7_5
; GFX10-32-NEXT:    s_branch .LBB7_5

; GFX10-32-NEXT:  .LBB7_4: ; %.continue1
; GFX10-32-NEXT:  .LBB7_4: ; %.continue1

; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1

; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s3

; GFX10-32-NEXT:    s_add_i32 s3, s3, 1
; GFX10-32-NEXT:    s_add_i32 s2, s2, 1

; GFX10-32-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s3, v1
; GFX10-32-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s2, v1

; GFX10-32-NEXT:    s_or_b32 s2, vcc_lo, s2
; GFX10-32-NEXT:    s_or_b32 s1, vcc_lo, s1

; GFX10-32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s1

; GFX10-32-NEXT:    s_cbranch_execz .LBB7_8
; GFX10-32-NEXT:    s_cbranch_execz .LBB7_8

; GFX10-32-NEXT:  .LBB7_5: ; %.continue0
; GFX10-32-NEXT:  .LBB7_5: ; %.continue0

; GFX10-32-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX10-32-NEXT:    ; =>This Inner Loop Header: Depth=1

; GFX10-32-NEXT:    s_mov_b32 s1, s0
; GFX10-32-NEXT:    s_mov_b32 s3, s0

; GFX10-32-NEXT:    v_cndmask_b32_e64 v0, s3, 0, s1
; GFX10-32-NEXT:    v_cndmask_b32_e64 v0, s2, 0, s3

; GFX10-32-NEXT:    s_xor_b32 s1, s0, -1
; GFX10-32-NEXT:    s_xor_b32 s3, s0, -1

; GFX10-32-NEXT:    v_mov_b32_e32 v2, v0
; GFX10-32-NEXT:    v_mov_b32_e32 v2, v0

; GFX10-32-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1

; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1

; GFX10-32-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
; GFX10-32-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec

; GFX10-32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0
; GFX10-32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0

; GFX10-32-NEXT:    s_or_b32 s1, s1, vcc_lo
; GFX10-32-NEXT:    s_or_b32 s3, s3, vcc_lo

; GFX10-32-NEXT:    s_and_saveexec_b32 s4, s1
; GFX10-32-NEXT:    s_and_saveexec_b32 s4, s3

; GFX10-32-NEXT:    s_xor_b32 s1, exec_lo, s4
; GFX10-32-NEXT:    s_xor_b32 s3, exec_lo, s4

; GFX10-32-NEXT:    s_cbranch_execz .LBB7_4
; GFX10-32-NEXT:    s_cbranch_execz .LBB7_4

; GFX10-32-NEXT:  ; %bb.6: ; %.demote1
; GFX10-32-NEXT:  ; %bb.6: ; %.demote1

; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1

; GFX10-32-NEXT:    s_andn2_b32 s0, s0, exec_lo
; GFX10-32-NEXT:    s_andn2_b32 s0, s0, exec_lo

; GFX10-32-NEXT:    s_cbranch_scc0 .LBB7_9
; GFX10-32-NEXT:    s_cbranch_scc0 .LBB7_9

; GFX10-32-NEXT:  ; %bb.7: ; %.demote1
; GFX10-32-NEXT:  ; %bb.7: ; %.demote1

; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1
; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1

; GFX10-32-NEXT:    s_wqm_b32 s4, s0
; GFX10-32-NEXT:    s_wqm_b32 s4, s0

; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s4
; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s4

; GFX10-32-NEXT:    s_branch .LBB7_4
; GFX10-32-NEXT:    s_branch .LBB7_4

; GFX10-32-NEXT:  .LBB7_8: ; %.return
; GFX10-32-NEXT:  .LBB7_8: ; %.return

; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s1

; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s0
; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s0

; GFX10-32-NEXT:    v_mov_b32_e32 v0, 0x3c00
; GFX10-32-NEXT:    v_mov_b32_e32 v0, 0x3c00

; GFX10-32-NEXT:    v_bfrev_b32_e32 v1, 60
; GFX10-32-NEXT:    v_bfrev_b32_e32 v1, 60

; GFX10-32-NEXT:    exp mrt0 v0, v0, v1, v1 done compr vm
; GFX10-32-NEXT:    exp mrt0 v0, v0, v1, v1 done compr vm

; GFX10-32-NEXT:    s_endpgm
; GFX10-32-NEXT:    s_endpgm

; GFX10-32-NEXT:  .LBB7_9:
; GFX10-32-NEXT:  .LBB7_9:

; GFX10-32-NEXT:    s_mov_b32 exec_lo, 0
; GFX10-32-NEXT:    s_mov_b32 exec_lo, 0

; GFX10-32-NEXT:    exp null off, off, off, off done vm
; GFX10-32-NEXT:    exp null off, off, off, off done vm

▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; GFX908: v_accvgpr_write_b32
; GFX908: v_accvgpr_write_b32

; GFX908:  global_load_
; GFX908:  global_load_

; GFX900:     buffer_store_dword v
; GFX900:     buffer_store_dword v

; GFX900:     buffer_load_dword v
; GFX900:     buffer_load_dword v

; GFX908-NOT: buffer_
; GFX908-NOT: buffer_

; GFX908-DAG: v_accvgpr_read_b32
; GFX908-DAG: v_accvgpr_read_b32




; GFX900: NumVgprs: 256
; GFX900: NumVgprs: 256

; GFX908: NumVgprs: 252
; GFX908: NumVgprs: 254

; GFX900: ScratchSize: 2052
; GFX900: ScratchSize: 1796

; GFX908: ScratchSize: 0
; GFX908: ScratchSize: 0

; GFX900: VGPRBlocks: 63
; GFX900: VGPRBlocks: 63

; GFX908: VGPRBlocks: 62
; GFX908: VGPRBlocks: 63

; GFX900: NumVGPRsForWavesPerEU: 256
; GFX900: NumVGPRsForWavesPerEU: 256

; GFX908: NumVGPRsForWavesPerEU: 252
; GFX908: NumVGPRsForWavesPerEU: 25

define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(<32 x float> addrspace(1)* %p) #1 {
define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(<32 x float> addrspace(1)* %p) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %p1 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p, i32 %tid
  %p1 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p, i32 %tid

  %p2 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p1, i32 %tid
  %p2 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p1, i32 %tid

  %p3 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p2, i32 %tid
  %p3 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p2, i32 %tid

  %p4 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p3, i32 %tid
  %p4 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p3, i32 %tid

  %p5 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p4, i32 %tid
  %p5 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p4, i32 %tid

  %p6 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p5, i32 %tid
  %p6 = getelementptr inbounds <32 x float>, <32 x float> addrspace(1)* %p5, i32 %tid

▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/srem64.ll
Show First 20 Lines • Show All 1,949 Lines • ▼ Show 20 Lines; GCN-IR-NEXT:    s_setpc_b64 s[30:31]

  %result = srem i64 %x, 32768
  %result = srem i64 %x, 32768

  ret i64 %result
  ret i64 %result

}
}




define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {

; GCN-LABEL: s_test_srem24_k_num_i64:
; GCN-LABEL: s_test_srem24_k_num_i64:

; GCN:       ; %bb.0:
; GCN:       ; %bb.0:

; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9

; GCN-NEXT:    s_mov_b32 s6, 0x41c00000

; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_waitcnt lgkmcnt(0)

; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40

; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4

; GCN-NEXT:    s_ashr_i32 s5, s4, 30
; GCN-NEXT:    s_mov_b32 s5, 0x41c00000

; GCN-NEXT:    s_or_b32 s5, s5, 1
; GCN-NEXT:    s_ashr_i32 s6, s4, 30

; GCN-NEXT:    v_mov_b32_e32 v3, s5
; GCN-NEXT:    s_or_b32 s6, s6, 1

; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0

; GCN-NEXT:    v_mov_b32_e32 v3, s6

; GCN-NEXT:    s_mov_b32 s3, 0xf000
; GCN-NEXT:    s_mov_b32 s3, 0xf000

; GCN-NEXT:    s_mov_b32 s2, -1
; GCN-NEXT:    s_mov_b32 s2, -1

; GCN-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1

; GCN-NEXT:    v_trunc_f32_e32 v1, v1
; GCN-NEXT:    v_trunc_f32_e32 v1, v1

; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s5

; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1

; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|

; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc

; GCN-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
; GCN-NEXT:    v_add_i32_e32 v0, vcc, v1, v0

; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4

; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0

; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24

; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0

; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0

; GCN-NEXT:    s_endpgm
; GCN-NEXT:    s_endpgm

;
;

; GCN-IR-LABEL: s_test_srem24_k_num_i64:
; GCN-IR-LABEL: s_test_srem24_k_num_i64:

; GCN-IR:       ; %bb.0:
; GCN-IR:       ; %bb.0:

; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9

; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000

; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)

; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40

; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4

; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000

; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
; GCN-IR-NEXT:    s_ashr_i32 s6, s4, 30

; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
; GCN-IR-NEXT:    s_or_b32 s6, s6, 1

; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0

; GCN-IR-NEXT:    v_mov_b32_e32 v3, s6

; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000

; GCN-IR-NEXT:    s_mov_b32 s2, -1
; GCN-IR-NEXT:    s_mov_b32 s2, -1

; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1

; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1

; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s5

; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1

; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|

; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc

; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1

; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4

; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0

; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24

; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0

▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; GCN-NEXT:    v_writelane_b32 v40, s47, 15
; GCN-NEXT:    v_writelane_b32 v40, s47, 15

; GCN-NEXT:    v_writelane_b32 v40, s48, 16
; GCN-NEXT:    v_writelane_b32 v40, s48, 16

; GCN-NEXT:    v_writelane_b32 v40, s49, 17
; GCN-NEXT:    v_writelane_b32 v40, s49, 17

; GCN-NEXT:    v_mov_b32_e32 v41, v31
; GCN-NEXT:    v_mov_b32_e32 v41, v31

; GCN-NEXT:    s_mov_b32 s44, s15
; GCN-NEXT:    s_mov_b32 s44, s15

; GCN-NEXT:    s_mov_b32 s45, s14
; GCN-NEXT:    s_mov_b32 s45, s14

; GCN-NEXT:    s_mov_b32 s46, s13
; GCN-NEXT:    s_mov_b32 s46, s13

; GCN-NEXT:    s_mov_b32 s47, s12
; GCN-NEXT:    s_mov_b32 s47, s12

; GCN-NEXT:    s_mov_b64 s[36:37], s[10:11]
; GCN-NEXT:    s_mov_b64 s[34:35], s[10:11]

; GCN-NEXT:    s_mov_b64 s[38:39], s[8:9]
; GCN-NEXT:    s_mov_b64 s[36:37], s[8:9]

; GCN-NEXT:    s_mov_b64 s[40:41], s[6:7]
; GCN-NEXT:    s_mov_b64 s[38:39], s[6:7]

; GCN-NEXT:    s_mov_b64 s[42:43], s[4:5]
; GCN-NEXT:    s_mov_b64 s[40:41], s[4:5]

; GCN-NEXT:    s_mov_b64 s[4:5], 0
; GCN-NEXT:    s_mov_b64 s[4:5], 0

; GCN-NEXT:    v_mov_b32_e32 v0, 0
; GCN-NEXT:    v_mov_b32_e32 v0, 0

; GCN-NEXT:    v_mov_b32_e32 v1, 0
; GCN-NEXT:    v_mov_b32_e32 v1, 0

; GCN-NEXT:    v_and_b32_e32 v2, 0x3ff, v41
; GCN-NEXT:    v_and_b32_e32 v2, 0x3ff, v41

; GCN-NEXT:    v_mov_b32_e32 v43, 0
; GCN-NEXT:    v_mov_b32_e32 v43, 0

; GCN-NEXT:    flat_load_dword v44, v[0:1]
; GCN-NEXT:    flat_load_dword v44, v[0:1]

; GCN-NEXT:    v_mov_b32_e32 v45, 0x7fc00000
; GCN-NEXT:    v_mov_b32_e32 v45, 0x7fc00000

; GCN-NEXT:    s_getpc_b64 s[48:49]
; GCN-NEXT:    s_getpc_b64 s[48:49]

; GCN-NEXT:    s_add_u32 s48, s48, spam@rel32@lo+4
; GCN-NEXT:    s_add_u32 s48, s48, spam@rel32@lo+4

; GCN-NEXT:    s_addc_u32 s49, s49, spam@rel32@hi+12
; GCN-NEXT:    s_addc_u32 s49, s49, spam@rel32@hi+12

; GCN-NEXT:    v_lshlrev_b32_e32 v42, 2, v2
; GCN-NEXT:    v_lshlrev_b32_e32 v42, 2, v2

; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

; GCN-NEXT:    v_cmp_eq_f32_e64 s[34:35], 0, v44
; GCN-NEXT:    v_cmp_eq_f32_e64 s[42:43], 0, v44

; GCN-NEXT:    s_branch .LBB1_3
; GCN-NEXT:    s_branch .LBB1_3

; GCN-NEXT:  .LBB1_1: ; %bb10
; GCN-NEXT:  .LBB1_1: ; %bb10

; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1

; GCN-NEXT:    s_or_b64 exec, exec, s[6:7]
; GCN-NEXT:    s_or_b64 exec, exec, s[6:7]

; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0
; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0

; GCN-NEXT:  .LBB1_2: ; %bb18
; GCN-NEXT:  .LBB1_2: ; %bb18

; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1

; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0
; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0

Show All 25 Lines
; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0

; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]

; GCN-NEXT:    s_mov_b64 s[6:7], 0
; GCN-NEXT:    s_mov_b64 s[6:7], 0

; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]

; GCN-NEXT:    s_cbranch_execnz .LBB1_4
; GCN-NEXT:    s_cbranch_execnz .LBB1_4

; GCN-NEXT:  ; %bb.7: ; %bb11
; GCN-NEXT:  ; %bb.7: ; %bb11

; GCN-NEXT:    ; in Loop: Header=BB1_4 Depth=2
; GCN-NEXT:    ; in Loop: Header=BB1_4 Depth=2

; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]

; GCN-NEXT:    s_mov_b64 s[4:5], s[42:43]
; GCN-NEXT:    s_mov_b64 s[4:5], s[40:41]

; GCN-NEXT:    s_mov_b64 s[6:7], s[40:41]
; GCN-NEXT:    s_mov_b64 s[6:7], s[38:39]

; GCN-NEXT:    s_mov_b64 s[8:9], s[38:39]
; GCN-NEXT:    s_mov_b64 s[8:9], s[36:37]

; GCN-NEXT:    s_mov_b64 s[10:11], s[36:37]
; GCN-NEXT:    s_mov_b64 s[10:11], s[34:35]

; GCN-NEXT:    s_mov_b32 s12, s47
; GCN-NEXT:    s_mov_b32 s12, s47

; GCN-NEXT:    s_mov_b32 s13, s46
; GCN-NEXT:    s_mov_b32 s13, s46

; GCN-NEXT:    s_mov_b32 s14, s45
; GCN-NEXT:    s_mov_b32 s14, s45

; GCN-NEXT:    s_mov_b32 s15, s44
; GCN-NEXT:    s_mov_b32 s15, s44

; GCN-NEXT:    v_mov_b32_e32 v31, v41
; GCN-NEXT:    v_mov_b32_e32 v31, v41

; GCN-NEXT:    s_swappc_b64 s[30:31], s[48:49]
; GCN-NEXT:    s_swappc_b64 s[30:31], s[48:49]

; GCN-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
; GCN-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0

; GCN-NEXT:    s_mov_b64 s[4:5], 0
; GCN-NEXT:    s_mov_b64 s[4:5], 0

; GCN-NEXT:    s_mov_b64 s[6:7], 0
; GCN-NEXT:    s_mov_b64 s[6:7], 0

; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc
; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc

; GCN-NEXT:    s_cbranch_execnz .LBB1_4
; GCN-NEXT:    s_cbranch_execnz .LBB1_4

; GCN-NEXT:  ; %bb.8: ; %bb14
; GCN-NEXT:  ; %bb.8: ; %bb14

; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1

; GCN-NEXT:    s_or_b64 exec, exec, s[8:9]
; GCN-NEXT:    s_or_b64 exec, exec, s[8:9]

; GCN-NEXT:    s_and_saveexec_b64 s[4:5], s[34:35]
; GCN-NEXT:    s_and_saveexec_b64 s[4:5], s[42:43]

; GCN-NEXT:    s_cbranch_execnz .LBB1_10
; GCN-NEXT:    s_cbranch_execnz .LBB1_10

; GCN-NEXT:  ; %bb.9: ; %bb16
; GCN-NEXT:  ; %bb.9: ; %bb16

; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1

; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]

; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0
; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], 0

; GCN-NEXT:  .LBB1_10: ; %bb17
; GCN-NEXT:  .LBB1_10: ; %bb17

; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1

; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], 0
; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], 0

▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/urem64.ll
Show First 20 Lines • Show All 1,410 Lines • ▼ Show 20 Lines; GCN-IR-NEXT:    s_endpgm

  store i64 %result, i64 addrspace(1)* %out
  store i64 %result, i64 addrspace(1)* %out

  ret void
  ret void

}
}




define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {

; GCN-LABEL: s_test_urem24_k_den_i64:
; GCN-LABEL: s_test_urem24_k_den_i64:

; GCN:       ; %bb.0:
; GCN:       ; %bb.0:

; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9

; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
; GCN-NEXT:    s_movk_i32 s4, 0x5b7f

; GCN-NEXT:    s_mov_b32 s7, 0xf000
; GCN-NEXT:    s_mov_b32 s7, 0xf000

; GCN-NEXT:    s_mov_b32 s6, -1
; GCN-NEXT:    s_mov_b32 s6, -1

; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_waitcnt lgkmcnt(0)

; GCN-NEXT:    s_lshr_b32 s2, s3, 8
; GCN-NEXT:    s_lshr_b32 s2, s3, 8

; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2

; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
; GCN-NEXT:    s_mov_b32 s3, 0x46b6fe00

; GCN-NEXT:    s_mov_b32 s5, s1
; GCN-NEXT:    s_mov_b32 s5, s1

; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0

; GCN-NEXT:    v_trunc_f32_e32 v1, v1
; GCN-NEXT:    v_trunc_f32_e32 v1, v1

; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1

; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
; GCN-NEXT:    v_mad_f32 v0, -v1, s3, v0

; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s3

; GCN-NEXT:    s_mov_b32 s4, s0

; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc

; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3

; GCN-NEXT:    v_mov_b32_e32 v1, 0
; GCN-NEXT:    v_mov_b32_e32 v1, 0

; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc

; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4

; GCN-NEXT:    s_mov_b32 s4, s0

; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0

; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0

; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0

; GCN-NEXT:    s_endpgm
; GCN-NEXT:    s_endpgm

;
;

; GCN-IR-LABEL: s_test_urem24_k_den_i64:
; GCN-IR-LABEL: s_test_urem24_k_den_i64:

; GCN-IR:       ; %bb.0:
; GCN-IR:       ; %bb.0:

; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9

; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
; GCN-IR-NEXT:    s_movk_i32 s4, 0x5b7f

; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000

; GCN-IR-NEXT:    s_mov_b32 s6, -1
; GCN-IR-NEXT:    s_mov_b32 s6, -1

; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)

; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8

; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2

; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
; GCN-IR-NEXT:    s_mov_b32 s3, 0x46b6fe00

; GCN-IR-NEXT:    s_mov_b32 s5, s1
; GCN-IR-NEXT:    s_mov_b32 s5, s1

; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0

; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1

; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1

; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s3, v0

; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s3

; GCN-IR-NEXT:    s_mov_b32 s4, s0

; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc

; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3

; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0

; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc

; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4

; GCN-IR-NEXT:    s_mov_b32 s4, s0

; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0

; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0

; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0

; GCN-IR-NEXT:    s_endpgm
; GCN-IR-NEXT:    s_endpgm

  %x.shr = lshr i64 %x, 40
  %x.shr = lshr i64 %x, 40

  %result = urem i64 %x.shr, 23423
  %result = urem i64 %x.shr, 23423

  store i64 %result, i64 addrspace(1)* %out
  store i64 %result, i64 addrspace(1)* %out

  ret void
  ret void

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