[AArch64InstPrinter] Introduce register markup tags emission

[antoniofrighetto]

Summary

AArch64 assembly syntax emission now leverages markup tags for registers, if enabled.

[david-arm]

LGTM!

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

1473–1474

nit: You could write this in fewer lines I think with just:

if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
  printRegName(O, Reg);
else
  printRegName(O, Reg, AArch64::vreg);
O << LayoutSuffix;

[antoniofrighetto]

@david-arm, thanks for the nit, had missed this. I just updated the diff w/ that change included. Mind committing it on my behalf (GitHub account associated to this profile, as I do not have commit access)? Thank you.

[antoniofrighetto]

/cc @MaskRay

[MaskRay]

Hmmm sorry, I hadn't seen this when pushing 1b726f0a4ceec0747782545f3d4727f5914ee04b . This needs a rebase and ideally this patch can add a few tests.

[antoniofrighetto]

@MaskRay, yeah, sorry, I should have probably specified it :/ Essentially, the other commit 4e9907977465 was relying on this one, so this one should have been pushed before, as the other contained the test (which leverages on this change too). Hence, there should be no need to actually introduce tests for this one, as already introduced in the other commit.

[MaskRay]

You may need to rebase this patch now. I think this changes many instructions not covered by MC/Disassembler/AArch64/marked-up.txt. Having better coverage will be appreicated.

[antoniofrighetto]

@MaskRay, rebased to trunk & added more coverage test!

[MaskRay]

llvm/test/MC/Disassembler/AArch64/marked-up.txt fails.
See Build 280780: pre-merge checks x64 windows failed · x64 debian failed

[MaskRay]

The last update still failed the test. If the patch has a dependency, you can click "Edit Related Revisions" to state so.

llvm/test/MC/Disassembler/AArch64/marked-up.txt

16

It's better to use an instruction family name

For st64b, I pick the extension name.

[antoniofrighetto]

@MaskRay, fixed by extending properly the patch. Coverage test preserved, and added a further one for completeness.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

public:
   AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                      const MCRegisterInfo &MRI);
 
   bool applyTargetSpecificCLOption(StringRef Opt) override;
 
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printRegName(raw_ostream &OS, unsigned RegNo, unsigned AltIdx) const;
 
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
   virtual void printInstruction(const MCInst *MI, uint64_t Address,
                                 const MCSubtargetInfo &STI, raw_ostream &O);
   virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
                                const MCSubtargetInfo &STI, raw_ostream &O);
   virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
   }
   return false;
 }
 
 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
 }
 
+void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo,
+                                      unsigned AltIdx) const {
+  OS << markup("<reg:") << getRegisterName(RegNo, AltIdx) << markup(">");
+}
+
 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                    StringRef Annot, const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
   // Check for special encodings and print the canonical alias instead.
 
   unsigned Opcode = MI->getOpcode();
 
   if (Opcode == AArch64::SYSxt)
if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
       case 31:
         // *xtw is only valid for signed 64-bit operations.
         if (Is64Bit && IsSigned)
           AsmMnemonic = "sxtw";
         break;
       }
 
       if (AsmMnemonic) {
-        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
-          << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
+        O << '\t' << AsmMnemonic << '\t';
+        printRegName(O, Op0.getReg());
+        O << ", ";
+        printRegName(O, getWRegFromXReg(Op1.getReg()));
         printAnnotation(O, Annot);
         return;
       }
     }
 
     // All immediate shifts are aliases, implemented using the Bitfield
     // instruction. In all cases the immediate shift amount shift must be in
     // the range 0 to (reg.size -1).
if (Op2.isImm() && Op3.isImm()) {
         O << ", " << markup("<imm:") << "#" << shift << markup(">");
         printAnnotation(O, Annot);
         return;
       }
     }
 
     // SBFIZ/UBFIZ aliases
     if (Op2.getImm() > Op3.getImm()) {
-      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
-        << getRegisterName(Op0.getReg()) << ", "
-        << getRegisterName(Op1.getReg()) << ", " << markup("<imm:") << "#"
-        << (Is64Bit ? 64 : 32) - Op2.getImm() << markup(">") << ", "
-        << markup("<imm:") << "#" << Op3.getImm() + 1 << markup(">");
+      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
+      printRegName(O, Op0.getReg());
+      O << ", ";
+      printRegName(O, Op1.getReg());
+      O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
+        << markup(">") << ", " << markup("<imm:") << "#" << Op3.getImm() + 1
+        << markup(">");
       printAnnotation(O, Annot);
       return;
     }
 
     // Otherwise SBFX/UBFX is the preferred form
-    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
-      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
-      << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
+    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
+    printRegName(O, Op0.getReg());
+    O << ", ";
+    printRegName(O, Op1.getReg());
+    O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
       << markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
       << markup(">");
     printAnnotation(O, Annot);
     return;
   }
 
   if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
     const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
     const MCOperand &Op2 = MI->getOperand(2);
     int ImmR = MI->getOperand(3).getImm();
     int ImmS = MI->getOperand(4).getImm();
 
     if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
         (ImmR == 0 || ImmS < ImmR) &&
         STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
       // BFC takes precedence over its entire range, sligtly differently to BFI.
       int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
       int LSB = (BitWidth - ImmR) % BitWidth;
       int Width = ImmS + 1;
 
-      O << "\tbfc\t" << getRegisterName(Op0.getReg()) << ", " << markup("<imm:")
-        << "#" << LSB << markup(">") << ", " << markup("<imm:") << "#" << Width
-        << markup(">");
+      O << "\tbfc\t";
+      printRegName(O, Op0.getReg());
+      O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
+        << markup("<imm:") << "#" << Width << markup(">");
       printAnnotation(O, Annot);
       return;
     } else if (ImmS < ImmR) {
       // BFI alias
       int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
       int LSB = (BitWidth - ImmR) % BitWidth;
       int Width = ImmS + 1;
 
-      O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
-        << getRegisterName(Op2.getReg()) << ", " << markup("<imm:") << "#"
-        << LSB << markup(">") << ", " << markup("<imm:") << "#" << Width
-        << markup(">");
+      O << "\tbfi\t";
+      printRegName(O, Op0.getReg());
+      O << ", ";
+      printRegName(O, Op2.getReg());
+      O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
+        << markup("<imm:") << "#" << Width << markup(">");
       printAnnotation(O, Annot);
       return;
     }
 
     int LSB = ImmR;
     int Width = ImmS - ImmR + 1;
     // Otherwise BFXIL the preferred form
-    O << "\tbfxil\t" << getRegisterName(Op0.getReg()) << ", "
-      << getRegisterName(Op2.getReg()) << ", " << markup("<imm:") << "#" << LSB
-      << markup(">") << ", " << markup("<imm:") << "#" << Width << markup(">");
+    O << "\tbfxil\t";
+    printRegName(O, Op0.getReg());
+    O << ", ";
+    printRegName(O, Op2.getReg());
+    O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
+      << markup("<imm:") << "#" << Width << markup(">");
     printAnnotation(O, Annot);
     return;
   }
 
   // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
   // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
   // printed.
   if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
        Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
       MI->getOperand(1).isExpr()) {
     if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
       O << "\tmovz\t";
     else
       O << "\tmovn\t";
 
-    O << getRegisterName(MI->getOperand(0).getReg()) << ", " << markup("<imm:")
-      << "#";
+    printRegName(O, MI->getOperand(0).getReg());
+    O << ", " << markup("<imm:") << "#";
     MI->getOperand(1).getExpr()->print(O, &MAI);
     O << markup(">");
     return;
   }
 
   if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
       MI->getOperand(2).isExpr()) {
-    O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
-      << markup("<imm:") << "#";
+    O << "\tmovk\t";
+    printRegName(O, MI->getOperand(0).getReg());
+    O << ", " << markup("<imm:") << "#";
     MI->getOperand(2).getExpr()->print(O, &MAI);
     O << markup(">");
     return;
   }
 
   // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
   // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
   // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
   // that can represent the move is the MOV alias, and the rest get printed
   // normally.
   if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
     int Shift = MI->getOperand(2).getImm();
     uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
 
     if (AArch64_AM::isMOVZMovAlias(Value, Shift,
                                    Opcode == AArch64::MOVZXi ? 64 : 32)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
-        << markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
-        << markup(">");
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
 
   if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
     int Shift = MI->getOperand(2).getImm();
     uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
     if (RegWidth == 32)
       Value = Value & 0xffffffff;
 
     if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
-        << markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
-        << markup(">");
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
 
   if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
       (MI->getOperand(1).getReg() == AArch64::XZR ||
        MI->getOperand(1).getReg() == AArch64::WZR) &&
       MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
     uint64_t Value = AArch64_AM::decodeLogicalImmediate(
         MI->getOperand(2).getImm(), RegWidth);
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
-      O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
-        << markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
-        << markup(">");
+      O << "\tmov\t";
+      printRegName(O, MI->getOperand(0).getReg());
+      O << ", " << markup("<imm:") << "#"
+        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
       return;
     }
   }
 
   if (Opcode == AArch64::CompilerBarrier) {
     O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
     printAnnotation(O, Annot);
     return;
void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                         StringRef Annot,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   unsigned Opcode = MI->getOpcode();
   StringRef Layout;
 
   bool IsTbx;
   if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
-    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
-      << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
+    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
+    printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
+    O << ", ";
 
     unsigned ListOpNum = IsTbx ? 2 : 1;
     printVectorList(MI, ListOpNum, STI, O, "");
 
-    O << ", "
-      << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
+    O << ", ";
+    printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
     printAnnotation(O, Annot);
     return;
   }
 
   if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
     O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
 
     // Now onto the operands: first a vector list with possible lane
     // specifier. E.g. { v0 }[2]
     int OpNum = LdStDesc->ListOperand;
     printVectorList(MI, OpNum++, STI, O, "");
 
     if (LdStDesc->HasLane)
       O << '[' << MI->getOperand(OpNum++).getImm() << ']';
 
     // Next the address: [xN]
     unsigned AddrReg = MI->getOperand(OpNum++).getReg();
-    O << ", [" << getRegisterName(AddrReg) << ']';
+    O << ", [";
+    printRegName(O, AddrReg);
+    O << ']';
 
     // Finally, there might be a post-indexed offset.
     if (LdStDesc->NaturalOffset != 0) {
       unsigned Reg = MI->getOperand(OpNum++).getReg();
-      if (Reg != AArch64::XZR)
-        O << ", " << getRegisterName(Reg);
-      else {
+      if (Reg != AArch64::XZR) {
+        O << ", ";
+        printRegName(O, Reg);
+      } else {
         assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
         O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
           << markup(">");
       }
     }
 
     printAnnotation(O, Annot);
     return;
#endif
   }
   else
     return false;
 
   std::string Str = Ins + Name;
   std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
 
   O << '\t' << Str;
-  if (NeedsReg)
-    O << ", " << getRegisterName(MI->getOperand(4).getReg());
+  if (NeedsReg) {
+    O << ", ";
+    printRegName(O, MI->getOperand(4).getReg());
+  }
 
   return true;
 }
 
 template <int EltSize>
 void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {

 }
 
 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
                                           const MCSubtargetInfo &STI,
                                           raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isReg() && "Non-register vreg operand!");
   unsigned Reg = Op.getReg();
-  O << getRegisterName(Reg, AArch64::vreg);
+  printRegName(O, Reg, AArch64::vreg);
 }
 
 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
                                            const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
   O << "c" << Op.getImm();
void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
                                               raw_ostream &O) {
   AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
   O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
 }
 
 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
+  O << ']';
 }
 
 template<int Scale>
 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
   O << markup("<imm:") << '#'
     << formatImm(Scale * MI->getOperand(OpNum).getImm()) << markup(">");
if (MO.isImm()) {
     assert(MO.isExpr() && "Unexpected operand type!");
     MO.getExpr()->print(O, &MAI);
   }
 }
 
 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
                                           unsigned Scale, raw_ostream &O) {
   const MCOperand MO1 = MI->getOperand(OpNum + 1);
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
   if (MO1.isImm()) {
     O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
       << markup(">");
   } else {
     assert(MO1.isExpr() && "Unexpected operand type!");
     O << ", ";
     MO1.getExpr()->print(O, &MAI);
   }
static_assert(size == 64 || size == 32,
                 "Template parameter must be either 32 or 64");
   unsigned Reg = MI->getOperand(OpNum).getReg();
 
   unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
   unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
 
   unsigned Even = MRI.getSubReg(Reg,  Sube);
   unsigned Odd = MRI.getSubReg(Reg,  Subo);
-  O << getRegisterName(Even) << ", " << getRegisterName(Odd);
+  printRegName(O, Even);
+  O << ", ";
+  printRegName(O, Odd);
 }
 
 void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
                                              const MCSubtargetInfo &STI,
                                              raw_ostream &O) {
   unsigned MaxRegs = 8;
   unsigned RegMask = MI->getOperand(OpNum).getImm();
 
void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
     const MCRegisterClass &FPR128RC =
         MRI.getRegClass(AArch64::FPR128RegClassID);
     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
   }
 
   for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
     if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
-      O << getRegisterName(Reg) << LayoutSuffix;
+      printRegName(O, Reg);
     else
-      O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
+      printRegName(O, Reg, AArch64::vreg);
+    O << LayoutSuffix;
 
     if (i + 1 != NumRegs)
       O << ", ";
   }
 
   O << " }";
 }
 

llvm/test/MC/Disassembler/AArch64/marked-up.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+all --mdis %s | FileCheck %s
 
 # CHECK:      b.ne  <imm:#20>
 0xa1 0x00 0x00 0x54
 # CHECK-NEXT: asr <reg:w0>, <reg:w0>, <imm:#0>
 0x00 0x7c 0x00 0x13
 # CHECK-NEXT: subs  <reg:x12>, <reg:x13>, <reg:x14>, asr <imm:#39>
 0xac 0x9d 0x8e 0xeb
 # CHECK-NEXT: ldp <reg:w3>, <reg:w2>, [<reg:x15>, <imm:#16>]!
 0xe3 0x09 0xc2 0x29
 
 ## ls64
 # CHECK-NEXT: st64b <reg:x2>, [<reg:x1>]
 0x22 0x90 0x3f 0xf8
+
+# CHECK-NEXT: bfi <reg:x4>, <reg:x5>, <imm:#52>, <imm:#11>
+0xa4 0x28 0x4c 0xb3
+# CHECK-NEXT: bfxil <reg:w9>, <reg:w10>, <imm:#0>, <imm:#1>
+0x49 0x1 0x0 0x33
+# CHECK-NEXT: sbfiz <reg:x2>, <reg:x3>, <imm:#63>, <imm:#1>
+0x62 0x0 0x41 0x93
+# CHECK-NEXT: ubfiz <reg:xzr>, <reg:xzr>, <imm:#10>, <imm:#11>
+0xff 0x2b 0x76 0xd3
+# CHECK-NEXT: sbfx  <reg:w12>, <reg:w9>, <imm:#0>, <imm:#1>
+0x2c 0x1 0x0 0x13
+# CHECK-NEXT: ubfx  <reg:xzr>, <reg:x4>, <imm:#0>, <imm:#1>
+0x9f 0x0 0x40 0xd3
+# CHECK-NEXT: tbx <reg:v0>.8b, { <reg:v6>.16b, <reg:v7>.16b }, <reg:v1>.8b
+0xc0 0x30 0x01 0x0e