[X86InstPrinter] Introduce markup tags emission

[antoniofrighetto]

Summary

x86 assembly syntax emission now leverages markup tags, if enabled.

[MaskRay]

This needs tests in llvm/test/MC/Disassembler/X86/ using -mdis.

[antoniofrighetto]

@MaskRay, test added!

llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
                                          unsigned OpNo, raw_ostream &O) {
   // Do not print the numberic target address when symbolizing.
   if (SymbolizeOperands)
     return;
 
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm()) {
+    O << markup("<imm:");
     if (PrintBranchImmAsAddress) {
       uint64_t Target = Address + Op.getImm();
       if (MAI.getCodePointerSize() == 4)
         Target &= 0xffffffff;
       O << formatHex(Target);
     } else
       O << formatImm(Op.getImm());
+    O << markup(">");
   } else {
     assert(Op.isExpr() && "unknown pcrel immediate operand");
     // If a symbolic branch target was added as a constant expression then print
     // that address in hex.
     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
     int64_t Address;
     if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
-      O << formatHex((uint64_t)Address);
+      O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
     } else {
       // Otherwise, just print the expression.
       Op.getExpr()->print(O, &MAI);
     }
   }
 }
 
 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,

llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

 
 #define DEBUG_TYPE "asm-printer"
 
 // Include the auto-generated portion of the assembly writer.
 #define PRINT_ALIAS_INSTR
 #include "X86GenAsmWriter1.inc"
 
 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << getRegisterName(RegNo);
+  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
 }
 
 void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                     StringRef Annot, const MCSubtargetInfo &STI,
                                     raw_ostream &OS) {
   printInstFlags(MI, OS, STI);
 
   // In 16-bit mode, print data16 as data32.

 }
 
 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
   } else if (Op.isImm()) {
-    O << formatImm((int64_t)Op.getImm());
+    O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
     O << "offset ";
     Op.getExpr()->print(O, &MAI);
   }
 }
 
 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
   unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
   const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
   const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
 
-  O << '[';
+  O << markup("<mem:") << '[';
 
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
     printOperand(MI, Op+X86::AddrBaseReg, O);
     NeedPlus = true;
   }
 
   if (IndexReg.getReg()) {
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
       if (NeedPlus) {
         if (DispVal > 0)
           O << " + ";
         else {
           O << " - ";
           DispVal = -DispVal;
         }
       }
-      O << formatImm(DispVal);
+      O << markup("<imm:") << formatImm(DispVal) << markup(">");
     }
   }
 
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
-  O << '[';
+  O << markup("<mem:") << '[';
   printOperand(MI, Op, O);
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // DI accesses are always ES-based.
-  O << "es:[";
+  O << "es:" << markup("<mem:") << '[';
   printOperand(MI, Op, O);
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
                                          raw_ostream &O) {
   const MCOperand &DispSpec = MI->getOperand(Op);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
 
-  O << '[';
+  O << markup("<mem:") << '[';
 
   if (DispSpec.isImm()) {
-    O << formatImm(DispSpec.getImm());
+    O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
   } else {
     assert(DispSpec.isExpr() && "non-immediate displacement?");
     DispSpec.getExpr()->print(O, &MAI);
   }
 
-  O << ']';
+  O << ']' << markup(">");
 }
 
 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
                                      raw_ostream &O) {
   if (MI->getOperand(Op).isExpr())
     return MI->getOperand(Op).getExpr()->print(O, &MAI);
 
-  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
+  O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
+    << markup(">");
 }
 
 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
                                             raw_ostream &OS) {
   const MCOperand &Op = MI->getOperand(OpNo);
   unsigned Reg = Op.getReg();
   // Override the default printing to print st(0) instead st.
   if (Reg == X86::ST0)
     OS << "st(0)";
   else
     printRegName(OS, Reg);
 }

llvm/test/MC/Disassembler/X86/marked-up-32.txt

+# RUN: llvm-mc -triple=i386 --mdis %s | FileCheck %s
+
+# CHECK: je <imm:60>
+0x0f 0x84 0x3c 0x00 0x00 0x00
+# CHECK: jecxz  <imm:-127>
+0xe3 0x81