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Differential D129805

[mlir][sparse][bufferization] fix a few memory leaks
ClosedPublic

Authored by aartbik on Jul 14 2022, 2:56 PM.

Details

Reviewers
springerm
jpienaar
bixia
Peiming
Commits
rGf30822d29c8b: [mlir][sparse][bufferization] fix a few memory leaks
Summary

Fixed some new memory leaks after migration to new
bufferization. One is expected, the other may need
some more careful analysis.

Diff Detail

Event Timeline

aartbik created this revision.Jul 14 2022, 2:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2022, 2:56 PM
Herald added subscribers: anlunx, bzcheeseman, sdasgup3 and 19 others. · View Herald Transcript
aartbik requested review of this revision.Jul 14 2022, 2:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2022, 2:56 PM
Herald added subscribers: stephenneuendorffer, nicolasvasilache. · View Herald Transcript
aartbik added reviewers: springerm, jpienaar, bixia, Peiming.Jul 14 2022, 2:57 PM
jpienaar accepted this revision.Jul 14 2022, 3:02 PM

Good for me if this avoids memory leaks in the test and these could be relaxed post

This revision is now accepted and ready to land.Jul 14 2022, 3:02 PM
This revision was landed with ongoing or failed builds.Jul 14 2022, 3:05 PM
Closed by commit rGf30822d29c8b: [mlir][sparse][bufferization] fix a few memory leaks (authored by aartbik). · Explain Why
This revision was automatically updated to reflect the committed changes.
aartbik added a commit: rGf30822d29c8b: [mlir][sparse][bufferization] fix a few memory leaks.
Harbormaster completed remote builds in B175512: Diff 444806.Jul 14 2022, 4:56 PM

Revision Contents

PathSize
mlir/
test/
Integration/
Dialect/
SparseTensor/
CPU/
7 lines
1 line

Diff 444809

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Lines func.func @entry() {
sparse_tensor.release %b4 : tensor<8x4xf64, #DCSR> sparse_tensor.release %b4 : tensor<8x4xf64, #DCSR>
sparse_tensor.release %1 : tensor<4x4xf64, #CSR> sparse_tensor.release %1 : tensor<4x4xf64, #CSR>
sparse_tensor.release %2 : tensor<4x4xf64, #DCSR> sparse_tensor.release %2 : tensor<4x4xf64, #DCSR>
sparse_tensor.release %4 : tensor<4x4xf64, #CSR> sparse_tensor.release %4 : tensor<4x4xf64, #CSR>
sparse_tensor.release %5 : tensor<4x4xf64, #DCSR> sparse_tensor.release %5 : tensor<4x4xf64, #DCSR>
sparse_tensor.release %7 : tensor<4x4xf64, #CSR> sparse_tensor.release %7 : tensor<4x4xf64, #CSR>
sparse_tensor.release %8 : tensor<4x4xf64, #DCSR> sparse_tensor.release %8 : tensor<4x4xf64, #DCSR>
// TODO(springerm): needed?
%m0 = bufferization.to_memref %0 : memref<4x4xf64>
memref.dealloc %m0 : memref<4x4xf64>
%m3 = bufferization.to_memref %3 : memref<4x4xf64>
memref.dealloc %m3 : memref<4x4xf64>
%m6 = bufferization.to_memref %6 : memref<4x4xf64>
memref.dealloc %m6 : memref<4x4xf64>
return return
} }
} }

mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines func.func @entry() {
scf.for %i = %c0 to %c4 step %c1 { scf.for %i = %c0 to %c4 step %c1 {
%v2 = vector.transfer_read %y[%i, %c0], %du: tensor<4x3xf64>, vector<3xf64> %v2 = vector.transfer_read %y[%i, %c0], %du: tensor<4x3xf64>, vector<3xf64>
vector.print %v2 : vector<3xf64> vector.print %v2 : vector<3xf64>
} }
// Release resources. // Release resources.
sparse_tensor.release %a : tensor<3x4xf64, #DCSR> sparse_tensor.release %a : tensor<3x4xf64, #DCSR>
sparse_tensor.release %0 : tensor<4x3xf64, #DCSR> sparse_tensor.release %0 : tensor<4x3xf64, #DCSR>
sparse_tensor.release %1 : tensor<4x3xf64, #DCSR>
return return
} }
} }