[PowerPC] Add an ISEL pattern for i32 MULLI.

[Esme]

Summary

We add the following ISEL pattern for i64 imm in D87384, this patch is for i32.

mul with (2^N * int16_imm) -> MULLI + RLWINM

[shchenz]

LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5502

Like this refactor.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
       return;
     }
 
     // Other cases are autogenerated.
     break;
   }
   case ISD::MUL: {
     SDValue Op1 = N->getOperand(1);
-    if (Op1.getOpcode() != ISD::Constant || Op1.getValueType() != MVT::i64)
+    if (Op1.getOpcode() != ISD::Constant ||
+        (Op1.getValueType() != MVT::i64 && Op1.getValueType() != MVT::i32))
       break;
 
     // If the multiplier fits int16, we can handle it with mulli.
     int64_t Imm = cast<ConstantSDNode>(Op1)->getZExtValue();
     unsigned Shift = countTrailingZeros<uint64_t>(Imm);
     if (isInt<16>(Imm) || !Shift)
       break;
 
     // If the shifted value fits int16, we can do this transformation:
     // (mul X, c1 << c2) -> (rldicr (mulli X, c1) c2). We do this in ISEL due to
     // DAGCombiner prefers (shl (mul X, c1), c2) -> (mul X, c1 << c2).
     uint64_t ImmSh = Imm >> Shift;
-    if (isInt<16>(ImmSh)) {
-      uint64_t SextImm = SignExtend64(ImmSh & 0xFFFF, 16);
+    if (!isInt<16>(ImmSh))
+      break;
+
+    if (Op1.getValueType() == MVT::i64) {
       SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
       SDNode *MulNode = CurDAG->getMachineNode(PPC::MULLI8, dl, MVT::i64,
                                                N->getOperand(0), SDImm);
-      CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, SDValue(MulNode, 0),
-                           getI32Imm(Shift, dl), getI32Imm(63 - Shift, dl));
+
+      SDValue Ops[] = {SDValue(MulNode, 0), getI32Imm(Shift, dl),
+                       getI32Imm(63 - Shift, dl)};
+      CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
+      return;
+    } else {
+      SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i32);
+      SDNode *MulNode = CurDAG->getMachineNode(PPC::MULLI, dl, MVT::i32,
+                                              N->getOperand(0), SDImm);
+
+      SDValue Ops[] = {SDValue(MulNode, 0), getI32Imm(Shift, dl),
+                       getI32Imm(0, dl), getI32Imm(31 - Shift, dl)};
+      CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
       return;
     }
     break;
   }
   // FIXME: Remove this once the ANDI glue bug is fixed:
   case PPCISD::ANDI_rec_1_EQ_BIT:
   case PPCISD::ANDI_rec_1_GT_BIT: {
     if (!ANDIGlueBug)

llvm/test/CodeGen/PowerPC/mulli.ll

; CHECK-NEXT:    blr
   %z = mul i64 %x, 1073733632
   %res = sub i64 %y, %z
   ret i64 %res
 }
 
 define i32 @test11(i32 %x) {
 ; CHECK-LABEL: test11:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 10
-; CHECK-NEXT:    ori 4, 4, 43680
-; CHECK-NEXT:    mullw 3, 3, 4
+; CHECK-NEXT:    mulli 3, 3, 21845
+; CHECK-NEXT:    slwi 3, 3, 5
 ; CHECK-NEXT:    blr
   %y = mul nsw i32 %x, 699040
   ret i32 %y
 }