[X86] Disable combineVectorSizedSetCCEquality for soft float.

[craig.topper]

Summary

The vector types aren't legal with soft float.
Also disable under NoImplicitFloat for good measure.

Fixes PR56351.

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

if ((!IsVectorBitCastCheap(X) || !IsVectorBitCastCheap(Y)) &&
     return SDValue();
 
   EVT VT = SetCC->getValueType(0);
   SDLoc DL(SetCC);
 
   // Use XOR (plus OR) and PTEST after SSE4.1 for 128/256-bit operands.
   // Use PCMPNEQ (plus OR) and KORTEST for 512-bit operands.
   // Otherwise use PCMPEQ (plus AND) and mask testing.
-  if ((OpSize == 128 && Subtarget.hasSSE2()) ||
+  bool NoImplicitFloatOps =
+      DAG.getMachineFunction().getFunction().hasFnAttribute(
+          Attribute::NoImplicitFloat);
+  if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
+      ((OpSize == 128 && Subtarget.hasSSE2()) ||
        (OpSize == 256 && Subtarget.hasAVX()) ||
-      (OpSize == 512 && Subtarget.useAVX512Regs())) {
+       (OpSize == 512 && Subtarget.useAVX512Regs()))) {
     bool HasPT = Subtarget.hasSSE41();
 
     // PTEST and MOVMSK are slow on Knights Landing and Knights Mill and widened
     // vector registers are essentially free. (Technically, widening registers
     // prevents load folding, but the tradeoff is worth it.)
     bool PreferKOT = Subtarget.preferMaskRegisters();
     bool NeedZExt = PreferKOT && !Subtarget.hasVLX() && OpSize != 512;
 

llvm/test/CodeGen/X86/pr56351.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+soft-float | FileCheck %s
+
+define i1 @foo(i128* %x, i128* %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq (%rdi), %rax
+; CHECK-NEXT:    movq 8(%rdi), %rcx
+; CHECK-NEXT:    xorq 8(%rsi), %rcx
+; CHECK-NEXT:    xorq (%rsi), %rax
+; CHECK-NEXT:    orq %rcx, %rax
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retq
+  %a = load i128, i128* %x, align 16
+  %b = load i128, i128* %y, align 16
+  %c = icmp eq i128 %a, %b
+  ret i1 %c
+}