[LoongArch] Add codegen support for converting between unsigned integer and floating-point

[gonglingqin]

Summary

Depends on D128899

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

For f64 -> u32 conversion on LA64, isn't ftintrz.l.d followed by movfr2gr.s enough for all values within u32's domain? Overflow is UB both in C and LLVM IR so we can technically ignore the (very) inconsistent behavior when input overflows.

(BTW I noticed AArch64 has native support for the fptoui semantics by means of the fcvtzu insn. Hope LoongArch will gain similar niceties in a future revision...)

[SixWeining]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

Thanks.

Actually we have considered the approach you mentioned. But similar to the divide-by-zero case, we choose the same approach as gcc what did.

And I'd like to discuss with you that is there anything missed. For example, the floating-point rounding and exception handling. ftintrz.l.d may not raise exception when the value is range [UINT32_MAX + 1, INT64_MAX - 1]. Not sure whehter we need to manually raise an exception.

@xry111 Hope to see inputs from you, too.

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

Ah that's nice to know. Thanks for sharing the thoughts behind the current implementation decision.

As for artificial "consistency" with gcc, I think the obvious way forward is to pursue the best practice where possible, no matter which project you're working on, then make the others adopt the verified best practice. So it doesn't matter if we're working on LLVM or gcc, we simply decide on a better way then make the other project do the same.

As for the exception handling and such, my opinion is: since UB means "anything is possible", either raising exceptions or not is okay, so we may well choose the faster one, that is, simply don't care. Of course this is different from the current behavior which is saturating for out-of-range inputs, which is arguably more useful for users, but it's UB after all so I think there's definitely room for further discussion. (Ideally/academically, one would try to gather some statistics over a wide range of software corpus, then base one's argument on that; however this doesn't change the fact that such usage is invoking UB so we may not be in a position to "accommodate" for their mistakes.)

[xry111]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

In C standard, annex F specifies C language support for the IEC 60559 (aka IEEE-754) floating-point standard. F.4 para 1 says:

If the integer type is _Bool, 6.3.1.2 applies and no floating-point exceptions are raised
(even for NaN). Otherwise, if the floating value is infinite or NaN or if the integral part
of the floating value exceeds the range of the integer type, then the ‘‘invalid’’ floating-
point exception is raised and the resulting value is unspecified.

So for this we need to raise an exception, unless (1) the user explicitly tells the compiler that he/she doesn't care about the exception (using -fno-trapping-math in GCC for example), or (2) LLVM explicitly claims it won't strictly follow IEEE-754 exception rules in the documentation.

[xry111]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

BUT, it seems LLVM defines fptoui w/o any exception specified. Clang's default is -fno-trapping-math (while GCC defaults to -ftrapping-math instead) and if you use -ftrapping-math explicitly, it will generate a different IR with llvm.experimental.constrained.fptoui.i32.f64. So yes: for a plain fptoui we don't need to raise exception.

[gonglingqin]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–153

Thanks for your suggestion, after discussion we decided to change the implementation

138–153

Thanks for your suggestion, I will change it

[gonglingqin]

Address @xen0n and @xry111's comments.

[gonglingqin]

rebase

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–139

Changes last time are lost after the rebase?

[gonglingqin]

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

138–139

Yes, thanks for your reminder. I'll fix this.

[gonglingqin]

Address @xen0n's comments, fix lost last modification during rebase, thanks again.

[xen0n]

Seems okay. Thanks!

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

 def : PatFPSetcc<SETOLE, FCMP_CLE_S,  FPR32>;
 def : PatFPSetcc<SETONE, FCMP_CNE_S,  FPR32>;
 def : PatFPSetcc<SETO,   FCMP_COR_S,  FPR32>;
 def : PatFPSetcc<SETUEQ, FCMP_CUEQ_S, FPR32>;
 def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>;
 def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>;
 def : PatFPSetcc<SETUNE, FCMP_CUNE_S, FPR32>;
 def : PatFPSetcc<SETUO,  FCMP_CUN_S,  FPR32>;
+def : PatFPSetcc<SETLT,  FCMP_CLT_S,  FPR32>;
 
 // TODO: Match signaling comparison strict_fsetccs with FCMP_S*_S instructions.
 
 /// Select
 
 def : Pat<(select GPR:$cc, FPR32:$fk, FPR32:$fj),
           (FSEL_S FPR32:$fj, FPR32:$fk, (MOVGR2CF GPR:$cc))>;
 

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 def : PatFPSetcc<SETOLE, FCMP_CLE_D,  FPR64>;
 def : PatFPSetcc<SETONE, FCMP_CNE_D,  FPR64>;
 def : PatFPSetcc<SETO,   FCMP_COR_D,  FPR64>;
 def : PatFPSetcc<SETUEQ, FCMP_CUEQ_D, FPR64>;
 def : PatFPSetcc<SETULT, FCMP_CULT_D, FPR64>;
 def : PatFPSetcc<SETULE, FCMP_CULE_D, FPR64>;
 def : PatFPSetcc<SETUNE, FCMP_CUNE_D, FPR64>;
 def : PatFPSetcc<SETUO,  FCMP_CUN_D,  FPR64>;
+def : PatFPSetcc<SETLT,  FCMP_CLT_D,  FPR64>;
 
 // TODO: Match signaling comparison strict_fsetccs with FCMP_S*_D instructions.
 
 /// Select
 
 def : Pat<(select GPR:$cc, FPR64:$fk, FPR64:$fj),
           (FSEL_D FPR64:$fj, FPR64:$fk, (MOVGR2CF GPR:$cc))>;
 

 def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FR_D R0))>;
 def : Pat<(f64 fpimm1), (FFINT_D_L (MOVGR2FR_D (ADDI_D R0, 1)))>;
 
 // Convert int to FP
 def : Pat<(f64 (sint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
           (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
 def : Pat<(f64 (sint_to_fp GPR:$src)), (FFINT_D_L (MOVGR2FR_D GPR:$src))>;
 
+def : Pat<(f64 (uint_to_fp (i64 (zexti32 (i64 GPR:$src))))),
+          (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
+
 def : Pat<(bitconvert GPR:$src), (MOVGR2FR_D GPR:$src)>;
 
 // Convert FP to int
 def : Pat<(bitconvert FPR64:$src), (MOVFR2GR_D FPR64:$src)>;
 } // Predicates = [HasBasicD, IsLA64]
 
 let Predicates = [HasBasicD, IsLA32] in {
 def : Pat<(f64 fpimm0), (FCVT_D_S (MOVGR2FR_W R0))>;
 def : Pat<(f64 fpimm0neg), (FCVT_D_S (FNEG_S (MOVGR2FR_W R0)))>;
 def : Pat<(f64 fpimm1), (FCVT_D_S (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1))))>;
 
 // Convert int to FP
 def : Pat<(f64 (sint_to_fp (i32 GPR:$src))), (FFINT_D_W (MOVGR2FR_W GPR:$src))>;
 } // Predicates = [HasBasicD, IsLA32]

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h

public:
   bool selectShiftMaskGRLen(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, Subtarget->getGRLen(), ShAmt);
   }
   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, 32, ShAmt);
   }
 
   bool selectSExti32(SDValue N, SDValue &Val);
+  bool selectZExti32(SDValue N, SDValue &Val);
 
 // Include the pieces autogenerated from the target description.
 #include "LoongArchGenDAGISel.inc"
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

bool LoongArchDAGToDAGISel::selectSExti32(SDValue N, SDValue &Val) {
   if (CurDAG->ComputeNumSignBits(N) > (VT.getSizeInBits() - 32)) {
     Val = N;
     return true;
   }
 
   return false;
 }
 
+bool LoongArchDAGToDAGISel::selectZExti32(SDValue N, SDValue &Val) {
+  if (N.getOpcode() == ISD::AND) {
+    auto *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    if (C && C->getZExtValue() == UINT64_C(0xFFFFFFFF)) {
+      Val = N.getOperand(0);
+      return true;
+    }
+  }
+  MVT VT = N.getSimpleValueType();
+  APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 32);
+  if (CurDAG->MaskedValueIsZero(N, Mask)) {
+    Val = N;
+    return true;
+  }
+
+  return false;
+}
+
 // This pass converts a legalized DAG into a LoongArch-specific DAG, ready
 // for instruction scheduling.
 FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) {
   return new LoongArchDAGToDAGISel(TM);
 }

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

void analyzeOutputArgs(CCState &CCInfo,
                          LoongArchCCAssignFn Fn) const;
 
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, GRLenVT, Custom);
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::SHL, MVT::i32, Custom);
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
+    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
   }
 
   static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
                                                ISD::SETUGT, ISD::SETUGE};
 
   if (Subtarget.hasBasicF()) {
     setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   }
   if (Subtarget.hasBasicD()) {
     setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
   }
 
   setOperationAction(ISD::BR_CC, GRLenVT, Expand);
   setOperationAction(ISD::SELECT_CC, GRLenVT, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  setOperationAction(ISD::FP_TO_UINT, GRLenVT, Custom);
+  setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom);
 
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
 
   setStackPointerRegisterToSaveRestore(LoongArch::R3);
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     return SDValue();
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
   case ISD::FP_TO_SINT:
     return lowerFP_TO_SINT(Op, DAG);
   case ISD::BITCAST:
     return lowerBITCAST(Op, DAG);
+  case ISD::FP_TO_UINT:
+    return SDValue();
+  case ISD::UINT_TO_FP:
+    return lowerUINT_TO_FP(Op, DAG);
   }
 }
 
+SDValue LoongArchTargetLowering::lowerUINT_TO_FP(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+
+  SDLoc DL(Op);
+  auto &TLI = DAG.getTargetLoweringInfo();
+  SDValue Tmp1, Tmp2;
+  SDValue Op1 = Op.getOperand(0);
+  if (Op1->getOpcode() == ISD::AssertZext ||
+      Op1->getOpcode() == ISD::AssertSext)
+    return Op;
+  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op.getOperand(0));
+  SDValue Res = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f64, Trunc);
+  SDNode *N = Res.getNode();
+  TLI.expandUINT_TO_FP(N, Tmp1, Tmp2, DAG);
+  return Tmp1;
+}
+
 SDValue LoongArchTargetLowering::lowerBITCAST(SDValue Op,
                                               SelectionDAG &DAG) const {
 
   SDLoc DL(Op);
   SDValue Op0 = Op.getOperand(0);
 
   if (Op.getValueType() == MVT::f32 && Op0.getValueType() == MVT::i32 &&
       Subtarget.is64Bit() && Subtarget.hasBasicF()) {
case ISD::BITCAST: {
     if (VT == MVT::i32 && SrcVT == MVT::f32 && Subtarget.is64Bit() &&
         Subtarget.hasBasicF()) {
       SDValue Dst =
           DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, MVT::i64, Src);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Dst));
     }
     break;
   }
+  case ISD::FP_TO_UINT: {
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+           "Unexpected custom legalisation");
+    auto &TLI = DAG.getTargetLoweringInfo();
+    SDValue Tmp1, Tmp2;
+    TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG);
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
+    break;
+  }
   }
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  const LoongArchSubtarget &Subtarget) {
   if (DCI.isBeforeLegalizeOps())
     return SDValue();

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 // typically introduced when the legalizer promotes the shift amount and
 // zero-extends it). For LoongArch, the mask is unnecessary as shifts in the
 // base ISA only read the least significant 5 bits (LA32) or 6 bits (LA64).
 def shiftMaskGRLen
     : ComplexPattern<GRLenVT, 1, "selectShiftMaskGRLen", [], [], 0>;
 def shiftMask32 : ComplexPattern<i64, 1, "selectShiftMask32", [], [], 0>;
 
 def sexti32 : ComplexPattern<i64, 1, "selectSExti32">;
+def zexti32 : ComplexPattern<i64, 1, "selectZExti32">;
 
 class shiftop<SDPatternOperator operator>
     : PatFrag<(ops node:$val, node:$count),
               (operator node:$val, (GRLenVT (shiftMaskGRLen node:$count)))>;
 class shiftopw<SDPatternOperator operator>
     : PatFrag<(ops node:$val, node:$count),
               (operator node:$val, (i64 (shiftMask32 node:$count)))>;
 

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.w.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.s $a0, $fa0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = fptosi double %a to i32
   ret i32 %1
 }
 
+define i32 @convert_double_to_u32(double %a) nounwind {
+; LA32-LABEL: convert_double_to_u32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    pcalau12i $a0, .LCPI7_0
+; LA32-NEXT:    addi.w $a0, $a0, .LCPI7_0
+; LA32-NEXT:    fld.d $fa1, $a0, 0
+; LA32-NEXT:    fsub.d $fa2, $fa0, $fa1
+; LA32-NEXT:    ftintrz.w.d $fa2, $fa2
+; LA32-NEXT:    movfr2gr.s $a0, $fa2
+; LA32-NEXT:    lu12i.w $a1, -524288
+; LA32-NEXT:    xor $a0, $a0, $a1
+; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
+; LA32-NEXT:    movcf2gr $a1, $fcc0
+; LA32-NEXT:    masknez $a0, $a0, $a1
+; LA32-NEXT:    ftintrz.w.d $fa0, $fa0
+; LA32-NEXT:    movfr2gr.s $a2, $fa0
+; LA32-NEXT:    maskeqz $a1, $a2, $a1
+; LA32-NEXT:    or $a0, $a1, $a0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_double_to_u32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, .LCPI7_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI7_0
+; LA64-NEXT:    fld.d $fa1, $a0, 0
+; LA64-NEXT:    fsub.d $fa2, $fa0, $fa1
+; LA64-NEXT:    ftintrz.w.d $fa2, $fa2
+; LA64-NEXT:    movfr2gr.s $a0, $fa2
+; LA64-NEXT:    lu12i.w $a1, -524288
+; LA64-NEXT:    xor $a0, $a0, $a1
+; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
+; LA64-NEXT:    movcf2gr $a1, $fcc0
+; LA64-NEXT:    masknez $a0, $a0, $a1
+; LA64-NEXT:    ftintrz.w.d $fa0, $fa0
+; LA64-NEXT:    movfr2gr.s $a2, $fa0
+; LA64-NEXT:    maskeqz $a1, $a2, $a1
+; LA64-NEXT:    or $a0, $a1, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fptoui double %a to i32
+  ret i32 %1
+}
+
 define i64 @convert_double_to_i64(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bl __fixdfdi
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: convert_double_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = fptosi double %a to i64
   ret i64 %1
 }
 
-define i64 @bitcast_double_to_i64(double %a) nounwind {
-; LA32-LABEL: bitcast_double_to_i64:
+define i64 @convert_double_to_u64(double %a) nounwind {
+; LA32-LABEL: convert_double_to_u64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
-; LA32-NEXT:    fst.d $fa0, $sp, 8
-; LA32-NEXT:    addi.w $a0, $sp, 8
-; LA32-NEXT:    ori $a0, $a0, 4
-; LA32-NEXT:    ld.w $a1, $a0, 0
-; LA32-NEXT:    ld.w $a0, $sp, 8
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    bl __fixunsdfdi
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
-; LA64-LABEL: bitcast_double_to_i64:
+; LA64-LABEL: convert_double_to_u64:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    movfr2gr.d $a0, $fa0
+; LA64-NEXT:    pcalau12i $a0, .LCPI9_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI9_0
+; LA64-NEXT:    fld.d $fa1, $a0, 0
+; LA64-NEXT:    fsub.d $fa2, $fa0, $fa1
+; LA64-NEXT:    ftintrz.l.d $fa2, $fa2
+; LA64-NEXT:    movfr2gr.d $a0, $fa2
+; LA64-NEXT:    lu52i.d $a1, $zero, -2048
+; LA64-NEXT:    xor $a0, $a0, $a1
+; LA64-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
+; LA64-NEXT:    movcf2gr $a1, $fcc0
+; LA64-NEXT:    masknez $a0, $a0, $a1
+; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
+; LA64-NEXT:    movfr2gr.d $a2, $fa0
+; LA64-NEXT:    maskeqz $a1, $a2, $a1
+; LA64-NEXT:    or $a0, $a1, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
-  %1 = bitcast double %a to i64
+  %1 = fptoui double %a to i64
   ret i64 %1
 }
 
-define double @bitcast_i64_to_double(i64 %a) nounwind {
+define double @convert_u8_to_double(i8 zeroext %a) nounwind {
+; LA32-LABEL: convert_u8_to_double:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.d.w $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u8_to_double:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $a0
+; LA64-NEXT:    ffint.d.w $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i8 %a to double
+  ret double %1
+}
+
+define double @convert_u16_to_double(i16 zeroext %a) nounwind {
+; LA32-LABEL: convert_u16_to_double:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.d.w $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u16_to_double:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $a0
+; LA64-NEXT:    ffint.d.w $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i16 %a to double
+  ret double %1
+}
+
+define double @convert_u32_to_double(i32 %a) nounwind {
+; LA32-LABEL: convert_u32_to_double:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    addi.w $a1, $sp, 8
+; LA32-NEXT:    ori $a1, $a1, 4
+; LA32-NEXT:    lu12i.w $a2, 275200
+; LA32-NEXT:    st.w $a2, $a1, 0
+; LA32-NEXT:    st.w $a0, $sp, 8
+; LA32-NEXT:    pcalau12i $a0, .LCPI12_0
+; LA32-NEXT:    addi.w $a0, $a0, .LCPI12_0
+; LA32-NEXT:    fld.d $fa0, $a0, 0
+; LA32-NEXT:    fld.d $fa1, $sp, 8
+; LA32-NEXT:    fsub.d $fa0, $fa1, $fa0
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u32_to_double:
+; LA64:       # %bb.0:
+; LA64-NEXT:    lu52i.d $a1, $zero, 1107
+; LA64-NEXT:    movgr2fr.d $fa0, $a1
+; LA64-NEXT:    pcalau12i $a1, .LCPI12_0
+; LA64-NEXT:    addi.d $a1, $a1, .LCPI12_0
+; LA64-NEXT:    fld.d $fa1, $a1, 0
+; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
+; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    lu52i.d $a1, $zero, 1075
+; LA64-NEXT:    or $a0, $a0, $a1
+; LA64-NEXT:    movgr2fr.d $fa1, $a0
+; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i32 %a to double
+  ret double %1
+}
+
+define double @convert_u64_to_double(i64 %a) nounwind {
+; LA32-LABEL: convert_u64_to_double:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    bl __floatundidf
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u64_to_double:
+; LA64:       # %bb.0:
+; LA64-NEXT:    srli.d $a1, $a0, 32
+; LA64-NEXT:    lu52i.d $a2, $zero, 1107
+; LA64-NEXT:    or $a1, $a1, $a2
+; LA64-NEXT:    movgr2fr.d $fa0, $a1
+; LA64-NEXT:    pcalau12i $a1, .LCPI13_0
+; LA64-NEXT:    addi.d $a1, $a1, .LCPI13_0
+; LA64-NEXT:    fld.d $fa1, $a1, 0
+; LA64-NEXT:    fsub.d $fa0, $fa0, $fa1
+; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    lu52i.d $a1, $zero, 1075
+; LA64-NEXT:    or $a0, $a0, $a1
+; LA64-NEXT:    movgr2fr.d $fa1, $a0
+; LA64-NEXT:    fadd.d $fa0, $fa1, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i64 %a to double
+  ret double %1
+}
+
+define double @bitcast_i64_to_double(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: bitcast_i64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    addi.w $a2, $sp, 8
 ; LA32-NEXT:    ori $a2, $a2, 4
 ; LA32-NEXT:    st.w $a1, $a2, 0
 ; LA32-NEXT:    st.w $a0, $sp, 8
 ; LA32-NEXT:    fld.d $fa0, $sp, 8
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: bitcast_i64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = bitcast i64 %a to double
   ret double %1
 }
+
+define i64 @bitcast_double_to_i64(double %a) nounwind {
+; LA32-LABEL: bitcast_double_to_i64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    fst.d $fa0, $sp, 8
+; LA32-NEXT:    addi.w $a0, $sp, 8
+; LA32-NEXT:    ori $a0, $a0, 4
+; LA32-NEXT:    ld.w $a1, $a0, 0
+; LA32-NEXT:    ld.w $a0, $sp, 8
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: bitcast_double_to_i64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movfr2gr.d $a0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = bitcast double %a to i64
+  ret i64 %1
+}

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.s $a0, $fa0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = fptosi float %a to i64
   ret i64 %1
 }
 
+define zeroext i8 @convert_float_to_u8(float %a) nounwind {
+; LA32-LABEL: convert_float_to_u8:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA32-NEXT:    movfr2gr.s $a0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_float_to_u8:
+; LA64:       # %bb.0:
+; LA64-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA64-NEXT:    movfr2gr.s $a0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fptoui float %a to i8
+  ret i8 %1
+}
+
+define zeroext i16 @convert_float_to_u16(float %a) nounwind {
+; LA32-LABEL: convert_float_to_u16:
+; LA32:       # %bb.0:
+; LA32-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA32-NEXT:    movfr2gr.s $a0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_float_to_u16:
+; LA64:       # %bb.0:
+; LA64-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA64-NEXT:    movfr2gr.s $a0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fptoui float %a to i16
+  ret i16 %1
+}
+
+define i32 @convert_float_to_u32(float %a) nounwind {
+; LA32-LABEL: convert_float_to_u32:
+; LA32:       # %bb.0:
+; LA32-NEXT:    pcalau12i $a0, .LCPI6_0
+; LA32-NEXT:    addi.w $a0, $a0, .LCPI6_0
+; LA32-NEXT:    fld.s $fa1, $a0, 0
+; LA32-NEXT:    fsub.s $fa2, $fa0, $fa1
+; LA32-NEXT:    ftintrz.w.s $fa2, $fa2
+; LA32-NEXT:    movfr2gr.s $a0, $fa2
+; LA32-NEXT:    lu12i.w $a1, -524288
+; LA32-NEXT:    xor $a0, $a0, $a1
+; LA32-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
+; LA32-NEXT:    movcf2gr $a1, $fcc0
+; LA32-NEXT:    masknez $a0, $a0, $a1
+; LA32-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA32-NEXT:    movfr2gr.s $a2, $fa0
+; LA32-NEXT:    maskeqz $a1, $a2, $a1
+; LA32-NEXT:    or $a0, $a1, $a0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_float_to_u32:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, .LCPI6_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI6_0
+; LA64-NEXT:    fld.s $fa1, $a0, 0
+; LA64-NEXT:    fsub.s $fa2, $fa0, $fa1
+; LA64-NEXT:    ftintrz.w.s $fa2, $fa2
+; LA64-NEXT:    movfr2gr.s $a0, $fa2
+; LA64-NEXT:    lu12i.w $a1, -524288
+; LA64-NEXT:    xor $a0, $a0, $a1
+; LA64-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
+; LA64-NEXT:    movcf2gr $a1, $fcc0
+; LA64-NEXT:    masknez $a0, $a0, $a1
+; LA64-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA64-NEXT:    movfr2gr.s $a2, $fa0
+; LA64-NEXT:    maskeqz $a1, $a2, $a1
+; LA64-NEXT:    or $a0, $a1, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fptoui float %a to i32
+  ret i32 %1
+}
+
+define i64 @convert_float_to_u64(float %a) nounwind {
+; LA32-LABEL: convert_float_to_u64:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    bl __fixunssfdi
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_float_to_u64:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, .LCPI7_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI7_0
+; LA64-NEXT:    fld.s $fa1, $a0, 0
+; LA64-NEXT:    fsub.s $fa2, $fa0, $fa1
+; LA64-NEXT:    ftintrz.w.s $fa2, $fa2
+; LA64-NEXT:    movfr2gr.s $a0, $fa2
+; LA64-NEXT:    lu52i.d $a1, $zero, -2048
+; LA64-NEXT:    xor $a0, $a0, $a1
+; LA64-NEXT:    fcmp.clt.s $fcc0, $fa0, $fa1
+; LA64-NEXT:    movcf2gr $a1, $fcc0
+; LA64-NEXT:    masknez $a0, $a0, $a1
+; LA64-NEXT:    ftintrz.w.s $fa0, $fa0
+; LA64-NEXT:    movfr2gr.s $a2, $fa0
+; LA64-NEXT:    maskeqz $a1, $a2, $a1
+; LA64-NEXT:    or $a0, $a1, $a0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fptoui float %a to i64
+  ret i64 %1
+}
+
 define float @convert_i8_to_float(i8 signext %a) nounwind {
 ; LA32-LABEL: convert_i8_to_float:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa0, $a0
 ; LA32-NEXT:    ffint.s.w $fa0, $fa0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: convert_i8_to_float:

 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64-NEXT:    ffint.s.w $fa0, $fa0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = sitofp i64 %a to float
   ret float %1
 }
 
+define float @convert_u8_to_float(i8 zeroext %a) nounwind {
+; LA32-LABEL: convert_u8_to_float:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.s.w $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u8_to_float:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $a0
+; LA64-NEXT:    ffint.s.w $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i8 %a to float
+  ret float %1
+}
+
+define float @convert_u16_to_float(i16 zeroext %a) nounwind {
+; LA32-LABEL: convert_u16_to_float:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.s.w $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u16_to_float:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $a0
+; LA64-NEXT:    ffint.s.w $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i16 %a to float
+  ret float %1
+}
+
+define float @convert_u32_to_float(i32 %a) nounwind {
+; LA32-LABEL: convert_u32_to_float:
+; LA32:       # %bb.0:
+; LA32-NEXT:    srli.w $a1, $a0, 1
+; LA32-NEXT:    andi $a2, $a0, 1
+; LA32-NEXT:    or $a1, $a2, $a1
+; LA32-NEXT:    movgr2fr.w $fa0, $a1
+; LA32-NEXT:    ffint.s.w $fa0, $fa0
+; LA32-NEXT:    fadd.s $fa0, $fa0, $fa0
+; LA32-NEXT:    slti $a1, $a0, 0
+; LA32-NEXT:    movgr2cf $fcc0, $a1
+; LA32-NEXT:    movgr2fr.w $fa1, $a0
+; LA32-NEXT:    ffint.s.w $fa1, $fa1
+; LA32-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u32_to_float:
+; LA64:       # %bb.0:
+; LA64-NEXT:    bstrpick.d $a1, $a0, 31, 1
+; LA64-NEXT:    andi $a2, $a0, 1
+; LA64-NEXT:    or $a1, $a2, $a1
+; LA64-NEXT:    movgr2fr.w $fa0, $a1
+; LA64-NEXT:    ffint.s.w $fa0, $fa0
+; LA64-NEXT:    fadd.s $fa0, $fa0, $fa0
+; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    slti $a1, $a0, 0
+; LA64-NEXT:    movgr2cf $fcc0, $a1
+; LA64-NEXT:    movgr2fr.w $fa1, $a0
+; LA64-NEXT:    ffint.s.w $fa1, $fa1
+; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i32 %a to float
+  ret float %1
+}
+
+define float @convert_u64_to_float(i64 %a) nounwind {
+; LA32-LABEL: convert_u64_to_float:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    bl __floatundisf
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: convert_u64_to_float:
+; LA64:       # %bb.0:
+; LA64-NEXT:    srli.d $a1, $a0, 1
+; LA64-NEXT:    andi $a2, $a0, 1
+; LA64-NEXT:    or $a1, $a2, $a1
+; LA64-NEXT:    movgr2fr.w $fa0, $a1
+; LA64-NEXT:    ffint.s.w $fa0, $fa0
+; LA64-NEXT:    fadd.s $fa0, $fa0, $fa0
+; LA64-NEXT:    slti $a1, $a0, 0
+; LA64-NEXT:    movgr2cf $fcc0, $a1
+; LA64-NEXT:    movgr2fr.w $fa1, $a0
+; LA64-NEXT:    ffint.s.w $fa1, $fa1
+; LA64-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = uitofp i64 %a to float
+  ret float %1
+}
+
 define i32 @bitcast_float_to_i32(float %a) nounwind {
 ; LA32-LABEL: bitcast_float_to_i32:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movfr2gr.s $a0, $fa0
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: bitcast_float_to_i32:
 ; LA64:       # %bb.0: