[LoongArch] Add codegen support for handling floating point immediates

[SixWeining]

Hello everyone. @gonglingqin is another engineer from Loongson. Please help to review her patches. Thanks.

[xen0n]

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

211–212

Are we better off handling this by just hard-coding the bit patterns then movgr2fr.w and movgr2frh.w? I don't know the exact latencies for fcvt.d.s but plain moves should be a bit faster.

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

121

nit: "will be added later"

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

211–212

Thanks for the suggestion, I will change that.

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

121

Thanks. I will change that.

[gonglingqin]

Address @xen0n's comments.

[xen0n]

LGTM but ideally someone else could take a look at this too.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

167–174

Suggest to remove useless blank lines and indent.

[gonglingqin]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

167–174

Thanks. I will change that.

[gonglingqin]

Address @SixWeining's comments.

[SixWeining]

need to rebase before landing

[xry111]

llvm/test/CodeGen/LoongArch/double-imm.ll

86

I'd suggest:

lu52i.d $a0, $zero, 0x3ff
movgr2fr.d $fa0, $a0

to reduce one instruction. The combination of lu52i.d and movgr2fr.d can always load $2^k$ as a f64 for all integral k in $[0, 1023]$.

But as it's already approved it can be done in a later revision.

[xen0n]

llvm/test/CodeGen/LoongArch/double-imm.ll

86

Wow that's some serious simplification. I don't think I've seen anything like this recently. Agreed this optimization is better done in a new patch, as it's more of a peephole kind, not deeply related to the generic handling done here.

[SixWeining]

llvm/test/CodeGen/LoongArch/double-imm.ll

86

Quite nice. Thanks for the suggestion. Let’s implement it in later patch. :)

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

 /// Loads
 
 defm : LdPat<load, FLD_S, f32>;
 
 /// Stores
 
 defm : StPat<store, FST_S, FPR32, f32>;
 
+/// Floating point constants
+
+def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>;
+def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>;
+def : Pat<(f32 fpimm1), (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1)))>;
 } // Predicates = [HasBasicF]

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 } // Predicates = [HasBasicD]
 
 // Instructions only available on LA64
 let Predicates = [HasBasicD, IsLA64] in {
 def MOVGR2FR_D  : FP_MOV<0b0000000100010100101010, "movgr2fr.d", FPR64, GPR>;
 def MOVFR2GR_D  : FP_MOV<0b0000000100010100101110, "movfr2gr.d", GPR, FPR64>;
 } // Predicates = [HasBasicD, IsLA64]
 
+// Instructions only available on LA32
+let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in {
+def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR64, GPR>;
+} // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1
+
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasBasicD] in {
 
 /// Float arithmetic operations
 

 
 /// Loads
 
 defm : LdPat<load, FLD_D, f64>;
 
 /// Stores
 
 defm : StPat<store, FST_D, FPR64, f64>;
-
 } // Predicates = [HasBasicD]
+
+/// Floating point constants
+
+let Predicates = [HasBasicD, IsLA64] in {
+def : Pat<(f64 fpimm0), (MOVGR2FR_D R0)>;
+def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FR_D R0))>;
+def : Pat<(f64 fpimm1), (FFINT_D_L (MOVGR2FR_D (ADDI_D R0, 1)))>;
+} // Predicates = [HasBasicD, IsLA64]
+
+let Predicates = [HasBasicD, IsLA32] in {
+def : Pat<(f64 fpimm0), (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0)>;
+def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0))>;
+def : Pat<(f64 fpimm1), (FCVT_D_S (FFINT_S_W (MOVGR2FR_W (ADDI_W R0, 1))))>;
+} // Predicates = [HasBasicD, IsLA32]

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

void analyzeInputArgs(CCState &CCInfo,
                         LoongArchCCAssignFn Fn) const;
   void analyzeOutputArgs(CCState &CCInfo,
                          const SmallVectorImpl<ISD::OutputArg> &Outs,
                          LoongArchCCAssignFn Fn) const;
 
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
+  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
+
+  bool isFPImmLegal(const APFloat &Imm, EVT VT,
+                    bool ForCodeSize) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT,
                    MVT::i1, Promote);
 
   // TODO: add necessary setOperationAction calls later.
   setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom);
   setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom);
 
-  setOperationAction(ISD::GlobalAddress, GRLenVT, Custom);
+  setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, GRLenVT, Custom);
 
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::SHL, MVT::i32, Custom);
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
   }
 
   static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
                                                ISD::SETUGT, ISD::SETUGE};
 
   if (Subtarget.hasBasicF()) {
     setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   }
   if (Subtarget.hasBasicD()) {
     setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
+    setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
   }
 
   setOperationAction(ISD::BR_CC, GRLenVT, Expand);
   setOperationAction(ISD::SELECT_CC, GRLenVT, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
case ISD::SRL_PARTS:
     return lowerShiftRightParts(Op, DAG, false);
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
     // This can be called for an i32 shift amount that needs to be promoted.
     assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     return SDValue();
+  case ISD::ConstantPool:
+    return lowerConstantPool(Op, DAG);
   }
 }
 
+SDValue LoongArchTargetLowering::lowerConstantPool(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT Ty = Op.getValueType();
+  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
+
+  // FIXME: Only support PC-relative addressing to access the symbol.
+  // Target flags will be added later.
+  if (!isPositionIndependent()) {
+    SDValue ConstantN = DAG.getTargetConstantPool(
+        N->getConstVal(), Ty, N->getAlign(), N->getOffset());
+    SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, ConstantN),
+                   0);
+    SDValue Addr(DAG.getMachineNode(Subtarget.is64Bit() ? LoongArch::ADDI_D
+                                                        : LoongArch::ADDI_W,
+                                    DL, Ty, AddrHi, ConstantN),
+                 0);
+    return Addr;
+  }
+  report_fatal_error("Unable to lower ConstantPool");
+}
+
 SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
                                                     SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT Ty = getPointerTy(DAG.getDataLayout());
   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
   unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
 
   // FIXME: Only support PC-relative addressing to access the symbol.
SDValue LoongArchTargetLowering::LowerReturn(
   RetOps[0] = Chain; // Update chain.
 
   // Add the glue node if we have it.
   if (Glue.getNode())
     RetOps.push_back(Glue);
 
   return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
 }
+
+bool LoongArchTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+                                           bool ForCodeSize) const {
+  assert((VT == MVT::f32 || VT == MVT::f64) && "Unexpected VT");
+
+  if (VT == MVT::f32 && !Subtarget.hasBasicF())
+    return false;
+  if (VT == MVT::f64 && !Subtarget.hasBasicD())
+    return false;
+  return (Imm.isZero() || Imm.isExactlyValue(+1.0));
+}

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

def simm12_plus1 : ImmLeaf<GRLenVT,
   [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
 
 // Return the negation of an immediate value.
 def NegImm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+// FP immediate patterns.
+def fpimm0    : PatLeaf<(fpimm), [{return N->isExactlyValue(+0.0);}]>;
+def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;
+def fpimm1    : PatLeaf<(fpimm), [{return N->isExactlyValue(+1.0);}]>;
+
 def CallSymbol: AsmOperandClass {
   let Name = "CallSymbol";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImm";
 }
 
 // A bare symbol used in call only.
 def call_symbol : Operand<iPTR> {
   let ParserMatchClass = CallSymbol;
 }
 

llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp

case MachineOperand::MO_Register:
     MCOp = MCOperand::createReg(MO.getReg());
     break;
   case MachineOperand::MO_RegisterMask:
     // Regmasks are like implicit defs.
     return false;
   case MachineOperand::MO_Immediate:
     MCOp = MCOperand::createImm(MO.getImm());
     break;
+  case MachineOperand::MO_ConstantPoolIndex:
+    MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
+    break;
   case MachineOperand::MO_GlobalAddress:
     MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
     break;
   case MachineOperand::MO_MachineBasicBlock:
     MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
     break;
   // TODO: lower special operands
   case MachineOperand::MO_BlockAddress:
   case MachineOperand::MO_ExternalSymbol:
-  case MachineOperand::MO_ConstantPoolIndex:
   case MachineOperand::MO_JumpTableIndex:
     break;
   }
   return true;
 }
 
 bool llvm::lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI,
                                               MCInst &OutMI, AsmPrinter &AP) {

llvm/test/CodeGen/LoongArch/double-imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64
+
+define double @f64_positive_zero() nounwind {
+; LA32-LABEL: f64_positive_zero:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $zero
+; LA32-NEXT:    movgr2frh.w $fa0, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f64_positive_zero:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.d $fa0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret double 0.0
+}
+
+define double @f64_negative_zero() nounwind {
+; LA32-LABEL: f64_negative_zero:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $zero
+; LA32-NEXT:    movgr2frh.w $fa0, $zero
+; LA32-NEXT:    fneg.d $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f64_negative_zero:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.d $fa0, $zero
+; LA64-NEXT:    fneg.d $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret double -0.0
+}
+
+define double @f64_constant_pi() nounwind {
+; LA32-LABEL: f64_constant_pi:
+; LA32:       # %bb.0:
+; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
+; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
+; LA32-NEXT:    fld.d $fa0, $a0, 0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f64_constant_pi:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
+; LA64-NEXT:    fld.d $fa0, $a0, 0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret double 3.1415926535897931159979634685441851615905761718750
+}
+
+define double @f64_add_fimm1(double %a) nounwind {
+; LA32-LABEL: f64_add_fimm1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $zero, 1
+; LA32-NEXT:    movgr2fr.w $fa1, $a0
+; LA32-NEXT:    ffint.s.w $fa1, $fa1
+; LA32-NEXT:    fcvt.d.s $fa1, $fa1
+; LA32-NEXT:    fadd.d $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f64_add_fimm1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $zero, 1
+; LA64-NEXT:    movgr2fr.d $fa1, $a0
+; LA64-NEXT:    ffint.d.l $fa1, $fa1
+; LA64-NEXT:    fadd.d $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fadd double %a, 1.0
+  ret double %1
+}
+
+define double @f64_positive_fimm1() nounwind {
+; LA32-LABEL: f64_positive_fimm1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $zero, 1
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.s.w $fa0, $fa0
+; LA32-NEXT:    fcvt.d.s $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f64_positive_fimm1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.d $a0, $zero, 1
+; LA64-NEXT:    movgr2fr.d $fa0, $a0
+; LA64-NEXT:    ffint.d.l $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret double 1.0
+}

llvm/test/CodeGen/LoongArch/float-imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64
+
+define float @f32_positive_zero() nounwind {
+; LA32-LABEL: f32_positive_zero:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $zero
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f32_positive_zero:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $zero
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret float 0.0
+}
+
+define float @f32_negative_zero() nounwind {
+; LA32-LABEL: f32_negative_zero:
+; LA32:       # %bb.0:
+; LA32-NEXT:    movgr2fr.w $fa0, $zero
+; LA32-NEXT:    fneg.s $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f32_negative_zero:
+; LA64:       # %bb.0:
+; LA64-NEXT:    movgr2fr.w $fa0, $zero
+; LA64-NEXT:    fneg.s $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret float -0.0
+}
+
+define float @f32_constant_pi() nounwind {
+; LA32-LABEL: f32_constant_pi:
+; LA32:       # %bb.0:
+; LA32-NEXT:    pcalau12i $a0, .LCPI2_0
+; LA32-NEXT:    addi.w $a0, $a0, .LCPI2_0
+; LA32-NEXT:    fld.s $fa0, $a0, 0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f32_constant_pi:
+; LA64:       # %bb.0:
+; LA64-NEXT:    pcalau12i $a0, .LCPI2_0
+; LA64-NEXT:    addi.d $a0, $a0, .LCPI2_0
+; LA64-NEXT:    fld.s $fa0, $a0, 0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret float 3.14159274101257324218750
+}
+
+define float @f32_add_fimm1(float %a) nounwind {
+; LA32-LABEL: f32_add_fimm1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $zero, 1
+; LA32-NEXT:    movgr2fr.w $fa1, $a0
+; LA32-NEXT:    ffint.s.w $fa1, $fa1
+; LA32-NEXT:    fadd.s $fa0, $fa0, $fa1
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f32_add_fimm1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.w $a0, $zero, 1
+; LA64-NEXT:    movgr2fr.w $fa1, $a0
+; LA64-NEXT:    ffint.s.w $fa1, $fa1
+; LA64-NEXT:    fadd.s $fa0, $fa0, $fa1
+; LA64-NEXT:    jirl $zero, $ra, 0
+  %1 = fadd float %a, 1.0
+  ret float %1
+}
+
+define float @f32_positive_fimm1() nounwind {
+; LA32-LABEL: f32_positive_fimm1:
+; LA32:       # %bb.0:
+; LA32-NEXT:    addi.w $a0, $zero, 1
+; LA32-NEXT:    movgr2fr.w $fa0, $a0
+; LA32-NEXT:    ffint.s.w $fa0, $fa0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
+; LA64-LABEL: f32_positive_fimm1:
+; LA64:       # %bb.0:
+; LA64-NEXT:    addi.w $a0, $zero, 1
+; LA64-NEXT:    movgr2fr.w $fa0, $a0
+; LA64-NEXT:    ffint.s.w $fa0, $fa0
+; LA64-NEXT:    jirl $zero, $ra, 0
+  ret float 1.0
+}