[GlobalISel] Do not crash on widening vector result

[sepavloff]

Summary

Function buildCopyToRegs did not handle properly the case when it should
make wider vector result. It happened, for example, in a function that
returns value of type <2 x f32>, which should be widen to <4 x f32> to
fit XMM register on X86. The function eventually calls
MachineIRBuilder::buildUnmerge, which does not expect that only one
destination register is specified.

Now this case is treated specifically in buildCopyToRegs.

[arsenm]

llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll

368

Can you add a few additional cases with odd elements that also are widened

378

Missing space

[arsenm]

Reverse ping

[sepavloff]

Rebased patch, added new tests

[sepavloff]

Small formatting fix

[arsenm]

LGTM

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

if (SrcTy.isVector() && !PartTy.isVector() &&
       PartSize > SrcTy.getElementType().getSizeInBits()) {
     // Vector was scalarized, and the elements extended.
     auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
     for (int i = 0, e = DstRegs.size(); i != e; ++i)
       B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
     return;
   }
 
+  if (SrcTy.isVector() && PartTy.isVector() &&
+      PartTy.getScalarSizeInBits() == SrcTy.getScalarSizeInBits() &&
+      SrcTy.getNumElements() < PartTy.getNumElements()) {
+    // A coercion like: v2f32 -> v4f32.
+    Register DstReg = DstRegs.front();
+    B.buildPadVectorWithUndefElements(DstReg, SrcReg);
+    return;
+  }
+
   LLT GCDTy = getGCDType(SrcTy, PartTy);
   if (GCDTy == PartTy) {
     // If this already evenly divisible, we can create a simple unmerge.
     B.buildUnmerge(DstRegs, SrcReg);
     return;
   }
 
   MachineRegisterInfo &MRI = *B.getMRI();

llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll

define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
   ; CHECK:   [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
   ; CHECK:   $rax = COPY [[UREM]](s64)
   ; CHECK:   RET 0, implicit $rax
   %res = urem i64 %arg1, %arg2
   ret i64 %res
 }
+
+define <2 x float> @test_const_v2f32() {
+  ; CHECK-LABEL: name: test_const_v2f32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32)
+  ; CHECK-NEXT:   $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>)
+  ; CHECK-NEXT:   RET 0, implicit $xmm0
+  ret <2 x float> <float 1.0, float 1.0>
+}
+
+define <3 x float> @test_const_v3f32() {
+  ; CHECK-LABEL: name: test_const_v3f32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)
+  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK-NEXT:   [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF]](s32)
+  ; CHECK-NEXT:   $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>)
+  ; CHECK-NEXT:   RET 0, implicit $xmm0
+  ret <3 x float> <float 1.0, float 1.0, float 1.0>
+}
+
+define <5 x float> @test_const_v5f32() {
+  ; CHECK-LABEL: name: test_const_v5f32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $rdi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
+  ; CHECK-NEXT:   G_STORE [[BUILD_VECTOR]](<5 x s32>), [[COPY]](p0) :: (store (<5 x s32>), align 32)
+  ; CHECK-NEXT:   $rax = COPY [[COPY]](p0)
+  ; CHECK-NEXT:   RET 0
+  ret <5 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
+}
+
+define <6 x float> @test_const_v6f32() {
+  ; CHECK-LABEL: name: test_const_v6f32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $rdi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
+  ; CHECK-NEXT:   G_STORE [[BUILD_VECTOR]](<6 x s32>), [[COPY]](p0) :: (store (<6 x s32>), align 32)
+  ; CHECK-NEXT:   $rax = COPY [[COPY]](p0)
+  ; CHECK-NEXT:   RET 0
+  ret <6 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>
+}