[LoongArch] Support lowering FrameIndex

[wangleiat]

Summary

Ensure callee-saved registers are accessed relative to the stackpointer.

Depends on D128429

[wangleiat]

Update test to use opaque pointers

[wangleiat]

rebase

[xen0n]

The other changes look good.

llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

68–69

This implementation is a simplified version of RISCV's getFrameIndexReference, but we're missing a stack ID check before this. I know we're not utilizing any non-default stack IDs so far but I don't know if such a check/assertion should be kept anyway.

[wangleiat]

llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

68–69

Riscv uses stackID to handle ScalableVector, which we currently don't support, at least not currently.

[xen0n]

LGTM apart from the stack ID assertion bit; @SixWeining do you think an assertion should be present nevertheless even if we're only using one type of stack currently?

[SixWeining]

In D128430#3629155, @xen0n wrote:

LGTM apart from the stack ID assertion bit; @SixWeining do you think an assertion should be present nevertheless even if we're only using one type of stack currently?

I think either is fine. I think the reason RISCV does an assertion is that it sets non-default stack ID in its .cpp code.
Considering LoongArch currently only use default stack ID which is not set by target explicitly, maybe there is no strong reason to do an assertion.

llvm/lib/Target/LoongArch/LoongArchFrameLowering.h

public:
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override {
     return MBB.erase(MI);
   }
 
+  StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
+                                     Register &FrameReg) const override;
+
   bool hasFP(const MachineFunction &MF) const override;
   bool hasBP(const MachineFunction &MF) const;
 };
 } // namespace llvm
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHFRAMELOWERING_H

llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

void LoongArchFrameLowering::emitPrologue(MachineFunction &MF,
                                           MachineBasicBlock &MBB) const {
   // TODO: Implement this when we have function calls
 }
 
 void LoongArchFrameLowering::emitEpilogue(MachineFunction &MF,
                                           MachineBasicBlock &MBB) const {
   // TODO: Implement this when we have function calls
 }
+
+StackOffset LoongArchFrameLowering::getFrameIndexReference(
+    const MachineFunction &MF, int FI, Register &FrameReg) const {
+  const MachineFrameInfo &MFI = MF.getFrameInfo();
+  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
+
+  // Callee-saved registers should be referenced relative to the stack
+  // pointer (positive offset), otherwise use the frame pointer (negative
+  // offset).
+  const auto &CSI = MFI.getCalleeSavedInfo();
+  int MinCSFI = 0;
+  int MaxCSFI = -1;
+  StackOffset Offset =
+      StackOffset::getFixed(MFI.getObjectOffset(FI) - getOffsetOfLocalArea() +
+                            MFI.getOffsetAdjustment());
+
+  if (CSI.size()) {
+    MinCSFI = CSI[0].getFrameIdx();
+    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
+  }
+
+  FrameReg = RI->getFrameRegister(MF);
+  if ((FI >= MinCSFI && FI <= MaxCSFI) || !hasFP(MF)) {
+    FrameReg = LoongArch::R3;
+    Offset += StackOffset::getFixed(MFI.getStackSize());
+  }
+
+  return Offset;
+}

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h

public:
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   void Select(SDNode *Node) override;
 
+  bool SelectBaseAddr(SDValue Addr, SDValue &Base);
+
   bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
   bool selectShiftMaskGRLen(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, Subtarget->getGRLen(), ShAmt);
   }
   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, 32, ShAmt);
   }
 
 // Include the pieces autogenerated from the target description.
 #include "LoongArchGenDAGISel.inc"
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H

llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp

if (Node->isMachineOpcode()) {
     return;
   }
 
   // Instruction Selection not handled by the auto-generated tablegen selection
   // should be handled here.
   unsigned Opcode = Node->getOpcode();
   MVT GRLenVT = Subtarget->getGRLenVT();
   SDLoc DL(Node);
+  MVT VT = Node->getSimpleValueType(0);
 
   switch (Opcode) {
   default:
     break;
   case ISD::Constant: {
     int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
-    if (Imm == 0 && Node->getSimpleValueType(0) == GRLenVT) {
+    if (Imm == 0 && VT == GRLenVT) {
       SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
                                            LoongArch::R0, GRLenVT);
       ReplaceNode(Node, New.getNode());
       return;
     }
     SDNode *Result = nullptr;
     SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
     // The instructions in the sequence are handled here.
     for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
       SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);
       if (Inst.Opc == LoongArch::LU12I_W)
         Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm);
       else
         Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SrcReg, SDImm);
       SrcReg = SDValue(Result, 0);
     }
 
     ReplaceNode(Node, Result);
     return;
   }
+  case ISD::FrameIndex: {
+    SDValue Imm = CurDAG->getTargetConstant(0, DL, GRLenVT);
+    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
+    SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
+    unsigned ADDIOp =
+        Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
+    ReplaceNode(Node, CurDAG->getMachineNode(ADDIOp, DL, VT, TFI, Imm));
+    return;
+  }
     // TODO: Add selection nodes needed later.
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }
 
+bool LoongArchDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
+  // If this is FrameIndex, select it directly. Otherwise just let it get
+  // selected to a register independently.
+  if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr))
+    Base =
+        CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getGRLenVT());
+  else
+    Base = Addr;
+  return true;
+}
+
 bool LoongArchDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
                                             SDValue &ShAmt) {
   // Shift instructions on LoongArch only read the lower 5 or 6 bits of the
   // shift amount. If there is an AND on the shift amount, we can bypass it if
   // it doesn't affect any of those bits.
   if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
     const APInt &AndMask = N->getConstantOperandAPInt(1);
 

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

def CallSymbol: AsmOperandClass {
   let PredicateMethod = "isImm";
 }
 
 // A bare symbol used in call only.
 def call_symbol : Operand<iPTR> {
   let ParserMatchClass = CallSymbol;
 }
 
+def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "LoongArchInstrFormats.td"
 include "LoongArchFloatInstrFormats.td"
 
 //===----------------------------------------------------------------------===//

 
 let Predicates = [IsLA64] in
 def : Pat<(loongarch_bstrpick GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
           (BSTRPICK_D GPR:$rj, uimm6:$msbd, uimm6:$lsbd)>;
 
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
-  def : Pat<(vt (LoadOp GPR:$rj)), (Inst GPR:$rj, 0)>;
-  def : Pat<(vt (LoadOp (add GPR:$rj, simm12:$imm12))),
-            (Inst GPR:$rj, simm12:$imm12)>;
+  def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
+  def : Pat<(vt (LoadOp (add BaseAddr:$rj, simm12:$imm12))),
+            (Inst BaseAddr:$rj, simm12:$imm12)>;
 }
 
 defm : LdPat<sextloadi8, LD_B>;
 defm : LdPat<extloadi8, LD_B>;
 defm : LdPat<sextloadi16, LD_H>;
 defm : LdPat<extloadi16, LD_H>;
 defm : LdPat<load, LD_W>, Requires<[IsLA32]>;
 defm : LdPat<zextloadi8, LD_BU>;
 defm : LdPat<zextloadi16, LD_HU>;
 let Predicates = [IsLA64] in {
 defm : LdPat<sextloadi32, LD_W, i64>;
 defm : LdPat<extloadi32, LD_W, i64>;
 defm : LdPat<zextloadi32, LD_WU, i64>;
 defm : LdPat<load, LD_D, i64>;
 } // Predicates = [IsLA64]
 
 /// Stores
 
 multiclass StPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy,
                  ValueType vt> {
-  def : Pat<(StoreOp (vt StTy:$rd), GPR:$rj),
-            (Inst StTy:$rd, GPR:$rj, 0)>;
-  def : Pat<(StoreOp (vt StTy:$rd), (add GPR:$rj, simm12:$imm12)),
-            (Inst StTy:$rd, GPR:$rj, simm12:$imm12)>;
+  def : Pat<(StoreOp (vt StTy:$rd), BaseAddr:$rj),
+            (Inst StTy:$rd, BaseAddr:$rj, 0)>;
+  def : Pat<(StoreOp (vt StTy:$rd), (add BaseAddr:$rj, simm12:$imm12)),
+            (Inst StTy:$rd, BaseAddr:$rj, simm12:$imm12)>;
 }
 
 defm : StPat<truncstorei8, ST_B, GPR, GRLenVT>;
 defm : StPat<truncstorei16, ST_H, GPR, GRLenVT>;
 defm : StPat<store, ST_W, GPR, i32>, Requires<[IsLA32]>;
 let Predicates = [IsLA64] in {
 defm : StPat<truncstorei32, ST_W, GPR, i64>;
 defm : StPat<store, ST_D, GPR, i64>;

llvm/test/CodeGen/LoongArch/frame.ll

+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+%struct.key_t = type { i32, [16 x i8] }
+
+;; FIXME: prologue and epilogue insertion must be implemented to complete this
+;; test
+
+define i32 @test() nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
+; CHECK-NEXT:    st.w $zero, $sp, 16
+; CHECK-NEXT:    st.d $zero, $sp, 8
+; CHECK-NEXT:    st.d $zero, $sp, 0
+; CHECK-NEXT:    addi.d $a0, $sp, 0
+; CHECK-NEXT:    ori $a0, $a0, 4
+; CHECK-NEXT:    bl test1
+; CHECK-NEXT:    move $a0, $zero
+; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
+; CHECK-NEXT:    jirl $zero, $ra, 0
+  %key = alloca %struct.key_t, align 4
+  call void @llvm.memset.p0i8.i64(ptr %key, i8 0, i64 20, i1 false)
+  %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
+  call void @test1(ptr %1)
+  ret i32 0
+}
+
+declare void @llvm.memset.p0i8.i64(ptr, i8, i64, i1)
+
+declare void @test1(ptr)