[PowerPC] Activate MASSV for Linux P10 and add support for finite math calls

[masoud.ataei]

Summary

Proposing to activate MASSV conversion for Linux power 10 architecture
and add support for finite math calls for those environments that still using
an old gnu toolchains.

llvm/include/llvm/Analysis/VecFuncs.def

 
 #elif defined(TLI_DEFINE_MASSV_VECFUNCS)
 // IBM MASS library's vector Functions
 
 // Floating-Point Arithmetic and Auxiliary Functions
 TLI_DEFINE_VECFUNC("cbrt", "__cbrtd2", FIXED(2))
 TLI_DEFINE_VECFUNC("cbrtf", "__cbrtf4", FIXED(4))
 TLI_DEFINE_VECFUNC("pow", "__powd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__pow_finite", "__powd2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.pow.f64", "__powd2", FIXED(2))
 TLI_DEFINE_VECFUNC("powf", "__powf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__powf_finite", "__powf4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.pow.f32", "__powf4", FIXED(4))
 
 // Exponential and Logarithmic Functions
 TLI_DEFINE_VECFUNC("exp", "__expd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__exp_finite", "__expd2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.exp.f64", "__expd2", FIXED(2))
 TLI_DEFINE_VECFUNC("expf", "__expf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__expf_finite", "__expf4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.exp.f32", "__expf4", FIXED(4))
 TLI_DEFINE_VECFUNC("exp2", "__exp2d2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.exp2.f64", "__exp2d2", FIXED(2))
 TLI_DEFINE_VECFUNC("exp2f", "__exp2f4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.exp2.f32", "__exp2f4", FIXED(4))
 TLI_DEFINE_VECFUNC("expm1", "__expm1d2", FIXED(2))
 TLI_DEFINE_VECFUNC("expm1f", "__expm1f4", FIXED(4))
 TLI_DEFINE_VECFUNC("log", "__logd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__log_finite", "__logd2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.log.f64", "__logd2", FIXED(2))
 TLI_DEFINE_VECFUNC("logf", "__logf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__logf_finite", "__logf4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.log.f32", "__logf4", FIXED(4))
 TLI_DEFINE_VECFUNC("log1p", "__log1pd2", FIXED(2))
 TLI_DEFINE_VECFUNC("log1pf", "__log1pf4", FIXED(4))
 TLI_DEFINE_VECFUNC("log10", "__log10d2", FIXED(2))
+TLI_DEFINE_VECFUNC("__log10_finite", "__log10d2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.log10.f64", "__log10d2", FIXED(2))
 TLI_DEFINE_VECFUNC("log10f", "__log10f4", FIXED(4))
+TLI_DEFINE_VECFUNC("__log10f_finite", "__log10f4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.log10.f32", "__log10f4", FIXED(4))
 TLI_DEFINE_VECFUNC("log2", "__log2d2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.log2.f64", "__log2d2", FIXED(2))
 TLI_DEFINE_VECFUNC("log2f", "__log2f4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.log2.f32", "__log2f4", FIXED(4))
 
 // Trigonometric Functions
 TLI_DEFINE_VECFUNC("sin", "__sind2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.sin.f64", "__sind2", FIXED(2))
 TLI_DEFINE_VECFUNC("sinf", "__sinf4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.sin.f32", "__sinf4", FIXED(4))
 TLI_DEFINE_VECFUNC("cos", "__cosd2", FIXED(2))
 TLI_DEFINE_VECFUNC("llvm.cos.f64", "__cosd2", FIXED(2))
 TLI_DEFINE_VECFUNC("cosf", "__cosf4", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.cos.f32", "__cosf4", FIXED(4))
 TLI_DEFINE_VECFUNC("tan", "__tand2", FIXED(2))
 TLI_DEFINE_VECFUNC("tanf", "__tanf4", FIXED(4))
 TLI_DEFINE_VECFUNC("asin", "__asind2", FIXED(2))
+TLI_DEFINE_VECFUNC("__asin_finite", "__asind2", FIXED(2))
 TLI_DEFINE_VECFUNC("asinf", "__asinf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__asinf_finite", "__asinf4", FIXED(4))
 TLI_DEFINE_VECFUNC("acos", "__acosd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__acos_finite", "__acosd2", FIXED(2))
 TLI_DEFINE_VECFUNC("acosf", "__acosf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__acosf_finite", "__acosf4", FIXED(4))
 TLI_DEFINE_VECFUNC("atan", "__atand2", FIXED(2))
 TLI_DEFINE_VECFUNC("atanf", "__atanf4", FIXED(4))
 TLI_DEFINE_VECFUNC("atan2", "__atan2d2", FIXED(2))
+TLI_DEFINE_VECFUNC("__atan2_finite", "__atan2d2", FIXED(2))
 TLI_DEFINE_VECFUNC("atan2f", "__atan2f4", FIXED(4))
+TLI_DEFINE_VECFUNC("__atan2f_finite", "__atan2f4", FIXED(4))
 
 // Hyperbolic Functions
 TLI_DEFINE_VECFUNC("sinh", "__sinhd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__sinh_finite", "__sinhd2", FIXED(2))
 TLI_DEFINE_VECFUNC("sinhf", "__sinhf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__sinhf_finite", "__sinhf4", FIXED(4))
 TLI_DEFINE_VECFUNC("cosh", "__coshd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__cosh_finite", "__coshd2", FIXED(2))
 TLI_DEFINE_VECFUNC("coshf", "__coshf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__coshf_finite", "__coshf4", FIXED(4))
 TLI_DEFINE_VECFUNC("tanh", "__tanhd2", FIXED(2))
 TLI_DEFINE_VECFUNC("tanhf", "__tanhf4", FIXED(4))
 TLI_DEFINE_VECFUNC("asinh", "__asinhd2", FIXED(2))
 TLI_DEFINE_VECFUNC("asinhf", "__asinhf4", FIXED(4))
 TLI_DEFINE_VECFUNC("acosh", "__acoshd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__acosh_finite", "__acoshd2", FIXED(2))
 TLI_DEFINE_VECFUNC("acoshf", "__acoshf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__acoshf_finite", "__acoshf4", FIXED(4))
 TLI_DEFINE_VECFUNC("atanh", "__atanhd2", FIXED(2))
+TLI_DEFINE_VECFUNC("__atanh_finite", "__atanhd2", FIXED(2))
 TLI_DEFINE_VECFUNC("atanhf", "__atanhf4", FIXED(4))
+TLI_DEFINE_VECFUNC("__atanhf_finite", "__atanhf4", FIXED(4))
 
 
 #elif defined(TLI_DEFINE_SVML_VECFUNCS)
 // Intel SVM library's Vector Functions
 
 TLI_DEFINE_VECFUNC("sin", "__svml_sin2", FIXED(2))
 TLI_DEFINE_VECFUNC("sin", "__svml_sin4", FIXED(4))
 TLI_DEFINE_VECFUNC("sin", "__svml_sin8", FIXED(8))

llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp

 /// "_P8" for Power8, "_P9" for Power9. The string is used as a suffix while
 /// generating subtarget-specific MASSV library functions. Current support
 /// includes minimum subtarget Power8 for Linux and Power7 for AIX.
 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) {
   // Assume generic when Subtarget is unavailable.
   if (!Subtarget)
     return "";
   // TODO: add _P10 enties to Linux MASS lib and remove the check for AIX
-  if (Subtarget->isAIXABI() && Subtarget->hasP10Vector())
+  if (Subtarget->hasP10Vector())
     return "_P10";
   if (Subtarget->hasP9Vector())
     return "_P9";
   if (Subtarget->hasP8Vector())
     return "_P8";
   if (Subtarget->isAIXABI())
     return "_P7";
 
bool PPCLowerMASSVEntries::lowerMASSVCall(CallInst *CI, Function &Func,
   // Handling pow(x, 0.25), pow(x, 0.75), powf(x, 0.25), powf(x, 0.75)
   if (handlePowSpecialCases(CI, Func, M))
     return true;
 
   std::string MASSVEntryName = createMASSVFuncName(Func, Subtarget);
   FunctionCallee FCache = M.getOrInsertFunction(
       MASSVEntryName, Func.getFunctionType(), Func.getAttributes());
 
-  CI->setCalledFunction(FCache);  
+  CI->setCalledFunction(FCache);
 
   return true;
 }
 
 bool PPCLowerMASSVEntries::runOnModule(Module &M) {
   bool Changed = false;
 
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
for (Function &Func : M) {
 
     if (!isMASSVFunc(Func.getName()))
       continue;
 
     // Call to lowerMASSVCall() invalidates the iterator over users upon
     // replacing the users. Precomputing the current list of users allows us to
     // replace all the call sites.
     SmallVector<User *, 4> MASSVUsers(Func.users());
-    
     for (auto *User : MASSVUsers) {
       auto *CI = dyn_cast<CallInst>(User);
       if (!CI)
         continue;
 
       Subtarget = &TM.getSubtarget<PPCSubtarget>(*CI->getParent()->getParent());
       Changed |= lowerMASSVCall(CI, Func, M, Subtarget);
     }

llvm/test/CodeGen/PowerPC/lower-massv.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR10,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s 
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s 
+; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR10,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr10  < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR10,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7   < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck -check-prefixes=CHECK-PWR7,CHECK-ALL %s
 
 declare <2 x double> @__cbrtd2(<2 x double>)
 declare <4 x float> @__cbrtf4(<4 x float>)
 
 declare <2 x double> @__powd2(<2 x double>, <2 x double>)
 declare <4 x float> @__powf4(<4 x float>, <4 x float>)
 
 declare <2 x double> @__expd2(<2 x double>)

 ; CHECK-PWR10: __cbrtd2_P10
 ; CHECK-PWR9:  __cbrtd2_P9
 ; CHECK-PWR8:  __cbrtd2_P8
 ; CHECK-PWR7:  __cbrtd2_P7
 ; CHECK-NOT:   __cbrtd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__cbrtd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @cbrt_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cbrt_f32_massv
 ; CHECK-PWR10: __cbrtf4_P10
 ; CHECK-PWR9:  __cbrtf4_P9
 ; CHECK-PWR8:  __cbrtf4_P8
 ; CHECK-PWR7:  __cbrtf4_P7
 ; CHECK-NOT:   __cbrtf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__cbrtf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; pow
 define <2 x double>  @pow_f64_massv(<2 x double> %opnd1, <2 x double> %opnd2) {
 ; CHECK-ALL-LABEL: @pow_f64_massv
 ; CHECK-PWR10: __powd2_P10
 ; CHECK-PWR9:  __powd2_P9
 ; CHECK-PWR8:  __powd2_P8
 ; CHECK-PWR7:  __powd2_P7
 ; CHECK-NOT:   __powd2_massv
 ; CHECK-ALL:   blr
 ;
  %1 = call <2 x double> @__powd2(<2 x double> %opnd1, <2 x double> %opnd2)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @pow_f32_massv(<4 x float> %opnd1, <4 x float> %opnd2) {
 ; CHECK-ALL-LABEL: @pow_f32_massv
 ; CHECK-PWR10: __powf4_P10
 ; CHECK-PWR9:  __powf4_P9
 ; CHECK-PWR8:  __powf4_P8
 ; CHECK-PWR7:  __powf4_P7
 ; CHECK-NOT:   __powf4_massv
 ; CHECK-ALL:   blr
 ;
  %1 = call <4 x float> @__powf4(<4 x float> %opnd1, <4 x float> %opnd2)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; exp
 define <2 x double>  @exp_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @exp_f64_massv
 ; CHECK-PWR10: __expd2_P10
 ; CHECK-PWR9:  __expd2_P9
 ; CHECK-PWR8:  __expd2_P8
 ; CHECK-PWR7:  __expd2_P7
 ; CHECK-NOT:   __expd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__expd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @exp_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @exp_f32_massv
 ; CHECK-PWR10: __expf4_P10
 ; CHECK-PWR9:  __expf4_P9
 ; CHECK-PWR8:  __expf4_P8
 ; CHECK-PWR7:  __expf4_P7
 ; CHECK-NOT:   __expf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__expf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; exp2
 define <2 x double>  @exp2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @exp2_f64_massv
 ; CHECK-PWR10: __exp2d2_P10
 ; CHECK-PWR9:  __exp2d2_P9
 ; CHECK-PWR8:  __exp2d2_P8
 ; CHECK-PWR7:  __exp2d2_P7
 ; CHECK-NOT:   __exp2d2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__exp2d2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @exp2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @exp2_f32_massv
 ; CHECK-PWR10: __exp2f4_P10
 ; CHECK-PWR9:  __exp2f4_P9
 ; CHECK-PWR8:  __exp2f4_P8
 ; CHECK-PWR7:  __exp2f4_P7
 ; CHECK-NOT:   __exp2f4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__exp2f4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; expm1
 define <2 x double>  @expm1_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @expm1_f64_massv
 ; CHECK-PWR10: __expm1d2_P10
 ; CHECK-PWR9:  __expm1d2_P9
 ; CHECK-PWR8:  __expm1d2_P8
 ; CHECK-PWR7:  __expm1d2_P7
 ; CHECK-NOT:   __expm1d2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__expm1d2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @expm1_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @expm1_f32_massv
 ; CHECK-PWR10: __expm1f4_P10
 ; CHECK-PWR9:  __expm1f4_P9
 ; CHECK-PWR8:  __expm1f4_P8
 ; CHECK-PWR7:  __expm1f4_P7
 ; CHECK-NOT:   __expm1f4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__expm1f4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; log
 define <2 x double>  @log_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log_f64_massv
 ; CHECK-PWR10: __logd2_P10
 ; CHECK-PWR9:  __logd2_P9
 ; CHECK-PWR8:  __logd2_P8
 ; CHECK-PWR7:  __logd2_P7
 ; CHECK-NOT:   __logd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__logd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @log_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log_f32_massv
 ; CHECK-PWR10: __logf4_P10
 ; CHECK-PWR9:  __logf4_P9
 ; CHECK-PWR8:  __logf4_P8
 ; CHECK-PWR7:  __logf4_P7
 ; CHECK-NOT:   __logf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__logf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; log1p
 define <2 x double>  @log1p_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log1p_f64_massv
 ; CHECK-PWR10: __log1pd2_P10
 ; CHECK-PWR9:  __log1pd2_P9
 ; CHECK-PWR8:  __log1pd2_P8
 ; CHECK-PWR7:  __log1pd2_P7
 ; CHECK-NOT:   __log1pd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__log1pd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @log1p_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log1p_f32_massv
 ; CHECK-PWR10: __log1pf4_P10
 ; CHECK-PWR9:  __log1pf4_P9
 ; CHECK-PWR8:  __log1pf4_P8
 ; CHECK-PWR7:  __log1pf4_P7
 ; CHECK-NOT:   __log1pf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__log1pf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; log10
 define <2 x double>  @log10_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log10_f64_massv
 ; CHECK-PWR10: __log10d2_P10
 ; CHECK-PWR9:  __log10d2_P9
 ; CHECK-PWR8:  __log10d2_P8
 ; CHECK-PWR7:  __log10d2_P7
 ; CHECK-NOT:   __log10d2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__log10d2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @log10_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log10_f32_massv
 ; CHECK-PWR10: __log10f4_P10
 ; CHECK-PWR9:  __log10f4_P9
 ; CHECK-PWR8:  __log10f4_P8
 ; CHECK-PWR7:  __log10f4_P7
 ; CHECK-NOT:   __log10f4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__log10f4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; log2
 define <2 x double>  @log2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log2_f64_massv
 ; CHECK-PWR10: __log2d2_P10
 ; CHECK-PWR9:  __log2d2_P9
 ; CHECK-PWR8:  __log2d2_P8
 ; CHECK-PWR7:  __log2d2_P7
 ; CHECK-NOT:   __log2d2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__log2d2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @log2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log2_f32_massv
 ; CHECK-PWR10: __log2f4_P10
 ; CHECK-PWR9:  __log2f4_P9
 ; CHECK-PWR8:  __log2f4_P8
 ; CHECK-PWR7:  __log2f4_P7
 ; CHECK-NOT:   __log2f4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__log2f4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; sin
 define <2 x double>  @sin_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @sin_f64_massv
 ; CHECK-PWR10: __sind2_P10
 ; CHECK-PWR9:  __sind2_P9
 ; CHECK-PWR8:  __sind2_P8
 ; CHECK-PWR7:  __sind2_P7
 ; CHECK-NOT:   __sind2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__sind2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @sin_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @sin_f32_massv
 ; CHECK-PWR10: __sinf4_P10
 ; CHECK-PWR9:  __sinf4_P9
 ; CHECK-PWR8:  __sinf4_P8
 ; CHECK-PWR7:  __sinf4_P7
 ; CHECK-NOT:   __sinf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__sinf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; cos
 define <2 x double>  @cos_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @cos_f64_massv
 ; CHECK-PWR10: __cosd2_P10
 ; CHECK-PWR9:  __cosd2_P9
 ; CHECK-PWR8:  __cosd2_P8
 ; CHECK-PWR7:  __cosd2_P7
 ; CHECK-NOT:   __cosd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__cosd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @cos_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cos_f32_massv
 ; CHECK-PWR10: __cosf4_P10
 ; CHECK-PWR9:  __cosf4_P9
 ; CHECK-PWR8:  __cosf4_P8
 ; CHECK-PWR7:  __cosf4_P7
 ; CHECK-NOT:   __cosf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__cosf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; tan
 define <2 x double>  @tan_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @tan_f64_massv
 ; CHECK-PWR10: __tand2_P10
 ; CHECK-PWR9:  __tand2_P9
 ; CHECK-PWR8:  __tand2_P8
 ; CHECK-PWR7:  __tand2_P7
 ; CHECK-NOT:   __tand2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__tand2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @tan_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @tan_f32_massv
 ; CHECK-PWR10: __tanf4_P10
 ; CHECK-PWR9:  __tanf4_P9
 ; CHECK-PWR8:  __tanf4_P8
 ; CHECK-PWR7:  __tanf4_P7
 ; CHECK-NOT:   __tanf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__tanf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; asin
 define <2 x double>  @asin_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @asin_f64_massv
 ; CHECK-PWR10: __asind2_P10
 ; CHECK-PWR9:  __asind2_P9
 ; CHECK-PWR8:  __asind2_P8
 ; CHECK-PWR7:  __asind2_P7
 ; CHECK-NOT:   __asind2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__asind2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @asin_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @asin_f32_massv
 ; CHECK-PWR10: __asinf4_P10
 ; CHECK-PWR9:  __asinf4_P9
 ; CHECK-PWR8:  __asinf4_P8
 ; CHECK-PWR7:  __asinf4_P7
 ; CHECK-NOT:   __asinf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__asinf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; acos
 define <2 x double>  @acos_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @acos_f64_massv
 ; CHECK-PWR10: __acosd2_P10
 ; CHECK-PWR9:  __acosd2_P9
 ; CHECK-PWR8:  __acosd2_P8
 ; CHECK-PWR7:  __acosd2_P7
 ; CHECK-NOT:   __acosd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__acosd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @acos_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @acos_f32_massv
 ; CHECK-PWR10: __acosf4_P10
 ; CHECK-PWR9:  __acosf4_P9
 ; CHECK-PWR8:  __acosf4_P8
 ; CHECK-PWR7:  __acosf4_P7
 ; CHECK-NOT:   __acosf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__acosf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; atan
 define <2 x double>  @atan_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atan_f64_massv
 ; CHECK-PWR10: __atand2_P10
 ; CHECK-PWR9:  __atand2_P9
 ; CHECK-PWR8:  __atand2_P8
 ; CHECK-PWR7:  __atand2_P7
 ; CHECK-NOT:   __atand2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__atand2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @atan_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atan_f32_massv
 ; CHECK-PWR10: __atanf4_P10
 ; CHECK-PWR9:  __atanf4_P9
 ; CHECK-PWR8:  __atanf4_P8
 ; CHECK-PWR7:  __atanf4_P7
 ; CHECK-NOT:   __atanf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__atanf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; atan2
 define <2 x double>  @atan2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atan2_f64_massv
 ; CHECK-PWR10: __atan2d2_P10
 ; CHECK-PWR9:  __atan2d2_P9
 ; CHECK-PWR8:  __atan2d2_P8
 ; CHECK-PWR7:  __atan2d2_P7
 ; CHECK-NOT:   __atan2d2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__atan2d2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @atan2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atan2_f32_massv
 ; CHECK-PWR10: __atan2f4_P10
 ; CHECK-PWR9:  __atan2f4_P9
 ; CHECK-PWR8:  __atan2f4_P8
 ; CHECK-PWR7:  __atan2f4_P7
 ; CHECK-NOT:   __atan2f4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__atan2f4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; sinh
 define <2 x double>  @sinh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @sinh_f64_massv
 ; CHECK-PWR10: __sinhd2_P10
 ; CHECK-PWR9:  __sinhd2_P9
 ; CHECK-PWR8:  __sinhd2_P8
 ; CHECK-PWR7:  __sinhd2_P7
 ; CHECK-NOT:   __sinhd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__sinhd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @sinh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @sinh_f32_massv
 ; CHECK-PWR10: __sinhf4_P10
 ; CHECK-PWR9:  __sinhf4_P9
 ; CHECK-PWR8:  __sinhf4_P8
 ; CHECK-PWR7:  __sinhf4_P7
 ; CHECK-NOT:   __sinhf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__sinhf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; cosh
 define <2 x double>  @cosh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @cosh_f64_massv
 ; CHECK-PWR10: __coshd2_P10
 ; CHECK-PWR9:  __coshd2_P9
 ; CHECK-PWR8:  __coshd2_P8
 ; CHECK-PWR7:  __coshd2_P7
 ; CHECK-NOT:   __coshd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__coshd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @cosh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cosh_f32_massv
 ; CHECK-PWR10: __coshf4_P10
 ; CHECK-PWR9:  __coshf4_P9
 ; CHECK-PWR8:  __coshf4_P8
 ; CHECK-PWR7:  __coshf4_P7
 ; CHECK-NOT:   __coshf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__coshf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; tanh
 define <2 x double>  @tanh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @tanh_f64_massv
 ; CHECK-PWR10: __tanhd2_P10
 ; CHECK-PWR9:  __tanhd2_P9
 ; CHECK-PWR8:  __tanhd2_P8
 ; CHECK-PWR7:  __tanhd2_P7
 ; CHECK-NOT:   __tanhd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__tanhd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @tanh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @tanh_f32_massv
 ; CHECK-PWR10: __tanhf4_P10
 ; CHECK-PWR9:  __tanhf4_P9
 ; CHECK-PWR8:  __tanhf4_P8
 ; CHECK-PWR7:  __tanhf4_P7
 ; CHECK-NOT:   __tanhf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__tanhf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; asinh
 define <2 x double>  @asinh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @asinh_f64_massv
 ; CHECK-PWR10: __asinhd2_P10
 ; CHECK-PWR9:  __asinhd2_P9
 ; CHECK-PWR8:  __asinhd2_P8
 ; CHECK-PWR7:  __asinhd2_P7
 ; CHECK-NOT:   __asinhd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__asinhd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @asinh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @asinh_f32_massv
 ; CHECK-PWR10: __asinhf4_P10
 ; CHECK-PWR9:  __asinhf4_P9
 ; CHECK-PWR8:  __asinhf4_P8
 ; CHECK-PWR7:  __asinhf4_P7
 ; CHECK-NOT:   __asinhf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__asinhf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; acosh
 define <2 x double>  @acosh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @acosh_f64_massv
 ; CHECK-PWR10: __acoshd2_P10
 ; CHECK-PWR9:  __acoshd2_P9
 ; CHECK-PWR8:  __acoshd2_P8
 ; CHECK-PWR7:  __acoshd2_P7
 ; CHECK-NOT:   __acoshd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__acoshd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @acosh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @acosh_f32_massv
 ; CHECK-PWR10: __acoshf4_P10
 ; CHECK-PWR9:  __acoshf4_P9
 ; CHECK-PWR8:  __acoshf4_P8
 ; CHECK-PWR7:  __acoshf4_P7
 ; CHECK-NOT:   __acoshf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__acoshf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 
 ; atanh
 define <2 x double>  @atanh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atanh_f64_massv
 ; CHECK-PWR10: __atanhd2_P10
 ; CHECK-PWR9:  __atanhd2_P9
 ; CHECK-PWR8:  __atanhd2_P8
 ; CHECK-PWR7:  __atanhd2_P7
 ; CHECK-NOT:   __atanhd2_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <2 x double> @__atanhd2(<2 x double> %opnd)
-  ret <2 x double> %1 
+  ret <2 x double> %1
 }
 
 define <4 x float>  @atanh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atanh_f32_massv
 ; CHECK-PWR10: __atanhf4_P10
 ; CHECK-PWR9:  __atanhf4_P9
 ; CHECK-PWR8:  __atanhf4_P8
 ; CHECK-PWR7:  __atanhf4_P7
 ; CHECK-NOT:   __atanhf4_massv
 ; CHECK-ALL:   blr
 ;
   %1 = call <4 x float> @__atanhf4(<4 x float> %opnd)
-  ret <4 x float> %1 
+  ret <4 x float> %1
 }
 

llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll

-; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR9 %s
+; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR10 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck -check-prefixes=CHECK-PWR9 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 | FileCheck -check-prefixes=CHECK-PWR8 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR10 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 | FileCheck -check-prefixes=CHECK-PWR9 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr8 | FileCheck -check-prefixes=CHECK-PWR8 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr7 | FileCheck -check-prefixes=CHECK-PWR7 %s
 
 ; Exponent is a variable
vector.body:
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
-; Exponent is a constant != 0.75 and !=0.25 and they are different 
+; Exponent is a constant != 0.75 and !=0.25 and they are different
 define void @vpow_noeq_const(double* nocapture %y, double* nocapture readonly %x) {
 ; CHECK-LABEL:       @vpow_noeq_const
 ; CHECK-PWR10:       __powd2_P10
 ; CHECK-PWR9:        __powd2_P9
 ; CHECK-PWR8:        __powd2_P8
 ; CHECK-PWR7:        __powd2_P7
 ; CHECK:             blr
 entry:
vector.body:
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
-; Exponent is a constant != 0.75 and !=0.25 and they are different 
+; Exponent is a constant != 0.75 and !=0.25 and they are different
 define void @vpow_noeq075_const(double* nocapture %y, double* nocapture readonly %x) {
 ; CHECK-LABEL:       @vpow_noeq075_const
 ; CHECK-PWR10:       __powd2_P10
 ; CHECK-PWR9:        __powd2_P9
 ; CHECK-PWR8:        __powd2_P8
 ; CHECK-PWR7:        __powd2_P7
 ; CHECK:             blr
 entry:
vector.body:
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
-; Exponent is a constant != 0.75 and !=0.25 and they are different 
+; Exponent is a constant != 0.75 and !=0.25 and they are different
 define void @vpow_noeq025_const(double* nocapture %y, double* nocapture readonly %x) {
 ; CHECK-LABEL:       @vpow_noeq025_const
 ; CHECK-PWR10:       __powd2_P10
 ; CHECK-PWR9:        __powd2_P9
 ; CHECK-PWR8:        __powd2_P8
 ; CHECK-PWR7:        __powd2_P7
 ; CHECK:             blr
 entry:

llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll

-; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR9 %s
+; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR10 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck -check-prefixes=CHECK-PWR9 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 | FileCheck -check-prefixes=CHECK-PWR8 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 | FileCheck -check-prefixes=CHECK-PWR10 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 | FileCheck -check-prefixes=CHECK-PWR9 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr8 | FileCheck -check-prefixes=CHECK-PWR8 %s
 ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr7 | FileCheck -check-prefixes=CHECK-PWR7 %s
 
 ; Exponent is a variable
vector.body:
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
-; Exponent is a constant != 0.75 and !=0.25 and they are different 
+; Exponent is a constant != 0.75 and !=0.25 and they are different
 define void @vspow_neq_const(float* nocapture %y, float* nocapture readonly %x)  {
 ; CHECK-LABEL:       @vspow_neq_const
 ; CHECK-PWR10:       __powf4_P10
 ; CHECK-PWR9:        __powf4_P9
 ; CHECK-PWR8:        __powf4_P8
 ; CHECK-PWR7:        __powf4_P7
 ; CHECK:             blr
 entry:

llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll

 ; RUN: opt -vector-library=MASSV -mtriple=powerpc64le-unknown-linux-gnu -inject-tli-mappings -loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
 ; RUN: opt -vector-library=MASSV -vec-extabi -mattr=+altivec -mtriple=powerpc64-ibm-aix-xcoff -inject-tli-mappings -loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
 
 declare double @cbrt(double) #0
 declare float @cbrtf(float) #0
 
 declare double @pow(double, double) #0
+declare double @__pow_finite(double, double) #0
 declare double @llvm.pow.f64(double, double) #0
 declare float @powf(float, float) #0
+declare float @__powf_finite(float, float) #0
 declare float @llvm.pow.f32(float, float) #0
 
 declare double @sqrt(double) #0
 declare float @sqrtf(float) #0
 
 declare double @exp(double) #0
+declare double @__exp_finite(double) #0
 declare double @llvm.exp.f64(double) #0
 declare float @expf(float) #0
+declare float @__expf_finite(float) #0
 declare float @llvm.exp.f32(float) #0
 
 declare double @exp2(double) #0
 declare double @llvm.exp2.f64(double) #0
 declare float @exp2f(float) #0
 declare float @llvm.exp2.f32(float) #0
 
 declare double @expm1(double) #0
 declare float @expm1f(float) #0
 
 declare double @log(double) #0
+declare double @__log_finite(double) #0
 declare double @llvm.log.f64(double) #0
 declare float @logf(float) #0
+declare float @__logf_finite(float) #0
 declare float @llvm.log.f32(float) #0
 
 declare double @log1p(double) #0
 declare float @log1pf(float) #0
 
 declare double @log10(double) #0
+declare double @__log10_finite(double) #0
 declare double @llvm.log10.f64(double) #0
 declare float @log10f(float) #0
+declare float @__log10f_finite(float) #0
 declare float @llvm.log10.f32(float) #0
 
 declare double @log2(double) #0
 declare double @llvm.log2.f64(double) #0
 declare float @log2f(float) #0
 declare float @llvm.log2.f32(float) #0
 
 declare double @sin(double) #0
 declare double @llvm.sin.f64(double) #0
 declare float @sinf(float) #0
 declare float @llvm.sin.f32(float) #0
 
 declare double @cos(double) #0
 declare double @llvm.cos.f64(double) #0
 declare float @cosf(float) #0
 declare float @llvm.cos.f32(float) #0
 
 declare double @tan(double) #0
 declare float @tanf(float) #0
 
 declare double @asin(double) #0
+declare double @__asin_finite(double) #0
 declare float @asinf(float) #0
+declare float @__asinf_finite(float) #0
 
 declare double @acos(double) #0
+declare double @__acos_finite(double) #0
 declare float @acosf(float) #0
+declare float @__acosf_finite(float) #0
 
 declare double @atan(double) #0
 declare float @atanf(float) #0
 
 declare double @atan2(double) #0
+declare double @__atan2_finite(double) #0
 declare float @atan2f(float) #0
+declare float @__atan2f_finite(float) #0
 
 declare double @sinh(double) #0
+declare double @__sinh_finite(double) #0
 declare float @sinhf(float) #0
+declare float @__sinhf_finite(float) #0
 
 declare double @cosh(double) #0
+declare double @__cosh_finite(double) #0
 declare float @coshf(float) #0
+declare float @__coshf_finite(float) #0
 
 declare double @tanh(double) #0
 declare float @tanhf(float) #0
 
 declare double @asinh(double) #0
 declare float @asinhf(float) #0
 
 declare double @acosh(double) #0
+declare double @__acosh_finite(double) #0
 declare float @acoshf(float) #0
+declare float @__acoshf_finite(float) #0
 
 declare double @atanh(double) #0
+declare double @__atanh_finite(double) #0
 declare float @atanhf(float) #0
+declare float @__atanhf_finite(float) #0
 
 define void @cbrt_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cbrt_f64(
 ; CHECK: __cbrtd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @pow_f64_finite(double* nocapture %varray, double* nocapture readonly %exp) {
+; CHECK-LABEL: @pow_f64_finite(
+; CHECK:  __powd2{{.*}}<2 x double>
+; CHECK:  ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %arrayidx = getelementptr inbounds double, double* %exp, i64 %iv
+  %tmp1 = load double, double* %arrayidx, align 4
+  %tmp2 = tail call double @__pow_finite(double %conv, double %tmp1)
+  %arrayidx2 = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %tmp2, double* %arrayidx2, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @pow_f64_intrinsic(double* nocapture %varray, double* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f64_intrinsic(
 ; CHECK: __powd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @pow_f32_finite(float* nocapture %varray, float* nocapture readonly %exp) {
+; CHECK-LABEL: @pow_f32_finite(
+; CHECK: __powf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %arrayidx = getelementptr inbounds float, float* %exp, i64 %iv
+  %tmp1 = load float, float* %arrayidx, align 4
+  %tmp2 = tail call float @__powf_finite(float %conv, float %tmp1)
+  %arrayidx2 = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %tmp2, float* %arrayidx2, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @pow_f32_intrinsic(float* nocapture %varray, float* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f32_intrinsic(
 ; CHECK: __powf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @exp_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @exp_f64_finite(
+; CHECK: __expd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__exp_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @exp_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @exp_f64_intrinsic(
 ; CHECK: __expd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @exp_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @exp_f32_finite(
+; CHECK: __expf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__expf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @exp_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @exp_f32_intrinsic(
 ; CHECK: __expf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @log_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @log_f64_finite(
+; CHECK: __logd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__log_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @log_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @log_f64_intrinsic(
 ; CHECK: __logd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @log_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @log_f32_finite(
+; CHECK: __logf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__logf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @log_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @log_f32_intrinsic(
 ; CHECK: __logf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @log10_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @log10_f64_finite(
+; CHECK: __log10d2(<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__log10_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @log10_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @log10_f64_intrinsic(
 ; CHECK: __log10d2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @log10_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @log10_f32_finite(
+; CHECK: __log10f4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__log10f_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @log10_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @log10_f32_intrinsic(
 ; CHECK: __log10f4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @asin_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @asin_f64_finite(
+; CHECK: __asind2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__asin_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @asin_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @asin_f32(
 ; CHECK: __asinf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @asinf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @asin_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @asin_f32_finite(
+; CHECK: __asinf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__asinf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @acos_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @acos_f64(
 ; CHECK: __acosd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @acos(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @acos_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @acos_f64_finite(
+; CHECK: __acosd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__acos_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @acos_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @acos_f32(
 ; CHECK: __acosf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @acosf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @acos_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @acos_f32_finite(
+; CHECK: __acosf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__acosf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @atan_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atan_f64(
 ; CHECK: __atand2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @atan2_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @atan2_f64_finite(
+; CHECK: __atan2d2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__atan2_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @atan2_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atan2_f32(
 ; CHECK: __atan2f4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @atan2f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @atan2_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @atan2_f32_finite(
+; CHECK: __atan2f4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__atan2f_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @sinh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @sinh_f64(
 ; CHECK: __sinhd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @sinh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @sinh_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @sinh_f64_finite(
+; CHECK: __sinhd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__sinh_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @sinh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @sinh_f32(
 ; CHECK: __sinhf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @sinhf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @sinh_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @sinh_f32_finite(
+; CHECK: __sinhf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__sinhf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @cosh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cosh_f64(
 ; CHECK: __coshd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @cosh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @cosh_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @cosh_f64_finite(
+; CHECK: __coshd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__cosh_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @cosh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @cosh_f32(
 ; CHECK: __coshf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @coshf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @cosh_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @cosh_f32_finite(
+; CHECK: __coshf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__coshf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @tanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @tanh_f64(
 ; CHECK: __tanhd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
for.body:
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @acosh_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @acosh_f64_finite(
+; CHECK: __acoshd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__acosh_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @acosh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @acosh_f32(
 ; CHECK: __acoshf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @acoshf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @acosh_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @acosh_f32_finite(
+; CHECK: __acoshf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__acoshf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @atanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f64(
 ; CHECK: __atanhd2{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atanh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @atanh_f64_finite(double* nocapture %varray) {
+; CHECK-LABEL: @atanh_f64_finite(
+; CHECK: __atanhd2{{.*}}<2 x double>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @__atanh_finite(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 define void @atanh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f32(
 ; CHECK: __atanhf4{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @atanhf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
+define void @atanh_f32_finite(float* nocapture %varray) {
+; CHECK-LABEL: @atanh_f32_finite(
+; CHECK: __atanhf4{{.*}}<4 x float>
+; CHECK: ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @__atanhf_finite(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
 attributes #0 = { nounwind }