[SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR.

[kmclaughlin]

LGTM

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 def AArch64fabd_p : PatFrag<(ops node:$pg, node:$op1, node:$op2),
                             (AArch64fabs_mt node:$pg, (AArch64fsub_p node:$pg, node:$op1, node:$op2), undef)>;
 
 // FMAs with a negated multiplication operand can be commuted.
 def AArch64fmls_p : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
                           [(AArch64fma_p node:$pred, (AArch64fneg_mt node:$pred, node:$op1, (undef)), node:$op2, node:$op3),
                            (AArch64fma_p node:$pred, node:$op2, (AArch64fneg_mt node:$pred, node:$op1, (undef)), node:$op3)]>;
 
+def AArch64fsubr_p : PatFrag<(ops node:$pg, node:$op1, node:$op2),
+                             (AArch64fsub_p node:$pg, node:$op2, node:$op1)>;
+
 def AArch64fneg_mt_nsz : PatFrag<(ops node:$pred, node:$op, node:$pt),
                                  (AArch64fneg_mt node:$pred, node:$op, node:$pt), [{
   return N->getFlags().hasNoSignedZeros();
 }]>;
 
 def SDT_AArch64Arith_Unpred : SDTypeProfile<1, 2, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>,
   SDTCisSameAs<0,1>, SDTCisSameAs<1,2>
let Predicates = [HasSVEorSME] in {
   defm FADD_ZPmI    : sve_fp_2op_i_p_zds<0b000, "fadd", "FADD_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fadd>;
   defm FSUB_ZPmI    : sve_fp_2op_i_p_zds<0b001, "fsub", "FSUB_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fsub>;
   defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", "FMUL_ZPZI", sve_fpimm_half_two, fpimm_half, fpimm_two, int_aarch64_sve_fmul>;
   defm FSUBR_ZPmI   : sve_fp_2op_i_p_zds<0b011, "fsubr", "FSUBR_ZPZI", sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fsubr>;
   defm FMAXNM_ZPmI  : sve_fp_2op_i_p_zds<0b100, "fmaxnm", "FMAXNM_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmaxnm>;
   defm FMINNM_ZPmI  : sve_fp_2op_i_p_zds<0b101, "fminnm", "FMINNM_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fminnm>;
   defm FMAX_ZPmI    : sve_fp_2op_i_p_zds<0b110, "fmax", "FMAX_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmax>;
   defm FMIN_ZPmI    : sve_fp_2op_i_p_zds<0b111, "fmin", "FMIN_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmin>;
-   
   defm FADD_ZPZI    : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fadd_p>;
   defm FSUB_ZPZI    : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fsub_p>;
   defm FMUL_ZPZI    : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_two, fpimm_half, fpimm_two, AArch64fmul_p>;
-  defm FSUBR_ZPZI   : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one>;
+  defm FSUBR_ZPZI   : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fsubr_p>;
   defm FMAXNM_ZPZI  : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fmaxnm_p>;
   defm FMINNM_ZPZI  : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fminnm_p>;
   defm FMAX_ZPZI    : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fmax_p>;
   defm FMIN_ZPZI    : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fmin_p>;
 
   let Predicates = [HasSVE, UseExperimentalZeroingPseudos] in {
     defm FADD_ZPZI    : sve_fp_2op_i_p_zds_zeroing_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fadd>;
     defm FSUB_ZPZI    : sve_fp_2op_i_p_zds_zeroing_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, int_aarch64_sve_fsub>;

llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll

 ; CHECK-NEXT:    fsub z0.d, p0/m, z0.d, #1.0
 ; CHECK-NEXT:    ret
   %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
   %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
   %out = fsub <vscale x 2 x double> %a, %splat
   ret <vscale x 2 x double> %out
 }
 
+;
+; FSUBR
+;
+
+define <vscale x 8 x half> @fsubr_h_immhalf(<vscale x 8 x half> %a) #0 {
+; CHECK-LABEL: fsubr_h_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %out = fsub <vscale x 8 x half> %splat, %a
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsubr_h_immone(<vscale x 8 x half> %a) #0 {
+; CHECK-LABEL: fsubr_h_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %out = fsub <vscale x 8 x half> %splat, %a
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x half> @fsubr_4h_immhalf(<vscale x 4 x half> %a) #0 {
+; CHECK-LABEL: fsubr_4h_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 4 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x half> %elt, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %out = fsub <vscale x 4 x half> %splat, %a
+  ret <vscale x 4 x half> %out
+}
+
+define <vscale x 4 x half> @fsubr_4h_immone(<vscale x 4 x half> %a) #0 {
+; CHECK-LABEL: fsubr_4h_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 4 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x half> %elt, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+  %out = fsub <vscale x 4 x half> %splat, %a
+  ret <vscale x 4 x half> %out
+}
+
+define <vscale x 2 x half> @fsubr_2h_immhalf(<vscale x 2 x half> %a) #0 {
+; CHECK-LABEL: fsubr_2h_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x half> %elt, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x half> %splat, %a
+  ret <vscale x 2 x half> %out
+}
+
+define <vscale x 2 x half> @fsubr_2h_immone(<vscale x 2 x half> %a) #0 {
+; CHECK-LABEL: fsubr_2h_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x half> %elt, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x half> %splat, %a
+  ret <vscale x 2 x half> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immhalf(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: fsubr_s_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %out = fsub <vscale x 4 x float> %splat, %a
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immone(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: fsubr_s_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %out = fsub <vscale x 4 x float> %splat, %a
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x float> @fsubr_2s_immhalf(<vscale x 2 x float> %a) #0 {
+; CHECK-LABEL: fsubr_2s_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x float> %elt, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x float> %splat, %a
+  ret <vscale x 2 x float> %out
+}
+
+define <vscale x 2 x float> @fsubr_2s_immone(<vscale x 2 x float> %a) #0 {
+; CHECK-LABEL: fsubr_2s_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x float> %elt, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x float> %splat, %a
+  ret <vscale x 2 x float> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immhalf(<vscale x 2 x double> %a) #0 {
+; CHECK-LABEL: fsubr_d_immhalf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x double> %splat, %a
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immone(<vscale x 2 x double> %a) #0 {
+; CHECK-LABEL: fsubr_d_immone:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fsubr z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:    ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %out = fsub <vscale x 2 x double> %splat, %a
+  ret <vscale x 2 x double> %out
+}
+
 ;; Arithmetic intrinsic declarations
 
 declare <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)
 declare <vscale x 4 x half> @llvm.maximum.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>)
 declare <vscale x 2 x half> @llvm.maximum.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>)
 declare <vscale x 4 x float> @llvm.maximum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
 declare <vscale x 2 x float> @llvm.maximum.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>)
 declare <vscale x 2 x double> @llvm.maximum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)