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Differential D128189

[AMDGPU] Increase instruction cache line size to 128 bytes for GFX11
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Authored by foad on Jun 20 2022, 5:45 AM.

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Joe_Nash
rampitec
piotr
Group Reviewers
Restricted Project
Commits
rGd7762a3b369e: [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11

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Event Timeline

foad created this revision.Jun 20 2022, 5:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2022, 5:45 AM
Herald added subscribers: kosarev, jsilvanus, kerbowa and 9 others. · View Herald Transcript
foad requested review of this revision.Jun 20 2022, 5:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2022, 5:45 AM
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foad added a reviewer: Restricted Project.Jun 20 2022, 5:46 AM
Joe_Nash accepted this revision.Jun 20 2022, 6:22 AM
This revision is now accepted and ready to land.Jun 20 2022, 6:22 AM
This revision was landed with ongoing or failed builds.Jun 20 2022, 6:27 AM
Closed by commit rGd7762a3b369e: [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11 (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGd7762a3b369e: [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11.
Harbormaster completed remote builds in B170834: Diff 438356.Jun 20 2022, 6:53 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
MCTargetDesc/
4 lines
test/
CodeGen/
AMDGPU/
4 lines

Diff 438370

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

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} }
bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
const uint32_t Encoded_s_code_end = 0xbf9f0000; const uint32_t Encoded_s_code_end = 0xbf9f0000;
const uint32_t Encoded_s_nop = 0xbf800000; const uint32_t Encoded_s_nop = 0xbf800000;
uint32_t Encoded_pad = Encoded_s_code_end; uint32_t Encoded_pad = Encoded_s_code_end;
// Instruction cache line size in bytes. // Instruction cache line size in bytes.
const unsigned Log2CacheLineSize = 6; const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
const unsigned CacheLineSize = 1u << Log2CacheLineSize; const unsigned CacheLineSize = 1u << Log2CacheLineSize;
// Extra padding amount in bytes to support prefetch mode 3. // Extra padding amount in bytes to support prefetch mode 3.
unsigned FillSize = 3 * CacheLineSize; unsigned FillSize = 3 * CacheLineSize;
if (AMDGPU::isGFX90A(STI)) { if (AMDGPU::isGFX90A(STI)) {
Encoded_pad = Encoded_s_nop; Encoded_pad = Encoded_s_nop;
FillSize = 16 * CacheLineSize; FillSize = 16 * CacheLineSize;
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} }
bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
const uint32_t Encoded_s_code_end = 0xbf9f0000; const uint32_t Encoded_s_code_end = 0xbf9f0000;
const uint32_t Encoded_s_nop = 0xbf800000; const uint32_t Encoded_s_nop = 0xbf800000;
uint32_t Encoded_pad = Encoded_s_code_end; uint32_t Encoded_pad = Encoded_s_code_end;
// Instruction cache line size in bytes. // Instruction cache line size in bytes.
const unsigned Log2CacheLineSize = 6; const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
const unsigned CacheLineSize = 1u << Log2CacheLineSize; const unsigned CacheLineSize = 1u << Log2CacheLineSize;
// Extra padding amount in bytes to support prefetch mode 3. // Extra padding amount in bytes to support prefetch mode 3.
unsigned FillSize = 3 * CacheLineSize; unsigned FillSize = 3 * CacheLineSize;
if (AMDGPU::isGFX90A(STI)) { if (AMDGPU::isGFX90A(STI)) {
Encoded_pad = Encoded_s_nop; Encoded_pad = Encoded_s_nop;
FillSize = 16 * CacheLineSize; FillSize = 16 * CacheLineSize;
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llvm/test/CodeGen/AMDGPU/s_code_end.ll

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; GCN-ASM-NEXT: .p2align 2 ; GCN-ASM-NEXT: .p2align 2
; GCN-ASM-NEXT: .type a_function,@function ; GCN-ASM-NEXT: .type a_function,@function
; GCN-NEXT: a_function{{>?}}: ; GCN-NEXT: a_function{{>?}}:
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
; GCN-ASM-NEXT: [[END_LABEL3:\.Lfunc_end.*]]: ; GCN-ASM-NEXT: [[END_LABEL3:\.Lfunc_end.*]]:
; GCN-ASM-NEXT: .size a_function, [[END_LABEL3]]-a_function ; GCN-ASM-NEXT: .size a_function, [[END_LABEL3]]-a_function
; GFX10END-ASM: .p2alignl 6, 3214868480 ; GFX10END-ASM: .p2alignl 6, 3214868480
; GFX11END-ASM: .p2alignl 6, 3214868480 ; GFX11END-ASM: .p2alignl 7, 3214868480
; GFX90AEND-ASM: .p2alignl 6, 3212836864 ; GFX90AEND-ASM: .p2alignl 6, 3212836864
; GFX10END-ASM-NEXT: .fill 48, 4, 3214868480 ; GFX10END-ASM-NEXT: .fill 48, 4, 3214868480
; GFX11END-ASM-NEXT: .fill 48, 4, 3214868480 ; GFX11END-ASM-NEXT: .fill 96, 4, 3214868480
; GFX90AEND-ASM-NEXT: .fill 256, 4, 3212836864 ; GFX90AEND-ASM-NEXT: .fill 256, 4, 3212836864
; GFX10NOEND-NOT: .fill ; GFX10NOEND-NOT: .fill
; GFX11NOEND-NOT: .fill ; GFX11NOEND-NOT: .fill
; GFX10NOEND-OBJ-NOT: s_code_end ; GFX10NOEND-OBJ-NOT: s_code_end
; GFX10END-OBJ-NEXT: s_code_end ; GFX10END-OBJ-NEXT: s_code_end
; GFX11NOEND-OBJ-NOT: s_code_end ; GFX11NOEND-OBJ-NOT: s_code_end
; GFX11END-OBJ-NEXT: s_code_end ; GFX11END-OBJ-NEXT: s_code_end
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