Some of these opcodes accept SGPRs as src0 which is incorrect. See bug 56036.
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[AMDGPU][MC][GFX11] Correct src0 for dpp and dpp8 variants of v_cvt_*_e64 ClosedPublic Authored by dp on Jun 15 2022, 4:53 AM.
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Event TimelineThis revision is now accepted and ready to land.Jun 15 2022, 6:26 AM This revision was landed with ongoing or failed builds.Jun 16 2022, 3:49 AM Closed by commit rGb26afab9d13d: [AMDGPU][MC][GFX11] Correct src0 for dpp variants of v_cvt_*_e64 (authored by dp). · Explain Why This revision was automatically updated to reflect the committed changes.
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Diff 437497 llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
llvm/test/MC/AMDGPU/gfx11_err.s
llvm/test/MC/Disassembler/AMDGPU/gfx11_asm_vop3_dpp16.txt
llvm/test/MC/Disassembler/AMDGPU/gfx11_asm_vop3_dpp8.txt
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