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Differential D127708

[AArch64][NFC] Fix a comment error
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Authored by Allen on Jun 13 2022, 7:44 PM.

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Reviewers
dmgreen
Commits
rG0cb33551ecd6: [AArch64][NFC] Fix a comment error

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Allen created this revision.Jun 13 2022, 7:44 PM
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Allen requested review of this revision.Jun 13 2022, 7:44 PM
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Allen added a comment.Jun 13 2022, 7:47 PM

@dmgreen

I'am sorry to missing apply your comment, https://reviews.llvm.org/D126700#inline-1223430
Harbormaster completed remote builds in B169606: Diff 436625.Jun 13 2022, 8:28 PM
dmgreen accepted this revision.Jun 13 2022, 9:16 PM

Oh thanks. LGTM

This revision is now accepted and ready to land.Jun 13 2022, 9:16 PM
This revision was landed with ongoing or failed builds.Jun 13 2022, 10:58 PM
Closed by commit rG0cb33551ecd6: [AArch64][NFC] Fix a comment error (authored by Allen). · Explain Why
This revision was automatically updated to reflect the committed changes.
Allen added a commit: rG0cb33551ecd6: [AArch64][NFC] Fix a comment error.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
2 lines

Diff 436625

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
"IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;
def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
"IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;
def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
"IsStoreAddressAscend", "false", "IsStoreAddressAscend", "false",
"Schedule scalar stores by ascending address">; "Schedule vector stores by ascending address">;
def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
"true", "STR of Q register with register offset is slow">; "true", "STR of Q register with register offset is slow">;
def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
"alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
"true", "Use alternative pattern for sextload convert to f32">; "true", "Use alternative pattern for sextload convert to f32">;
▲ Show 20 Lines • Show All 1,055 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp

Show All 20 Linesstatic bool needReorderStoreMI(const MachineInstr *MI) {
default: default:
return false; return false;
case AArch64::STURQi: case AArch64::STURQi:
case AArch64::STRQui: case AArch64::STRQui:
if (MI->getMF()->getSubtarget<AArch64Subtarget>().isStoreAddressAscend()) if (MI->getMF()->getSubtarget<AArch64Subtarget>().isStoreAddressAscend())
return false; return false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::STPQi: case AArch64::STPQi:
return AArch64InstrInfo::getLdStOffsetOp(*MI).getType() == MachineOperand::MO_Immediate; return AArch64InstrInfo::getLdStOffsetOp(*MI).isImm();
} }
return false; return false;
} }
// Return true if two stores with same base address may overlap writes // Return true if two stores with same base address may overlap writes
static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1,
int64_t &Off0, int64_t &Off1) { int64_t &Off0, int64_t &Off1) {
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines